Nothing Special   »   [go: up one dir, main page]

CN103123954B - A kind of manufacture method of magnetic funnel node device - Google Patents

A kind of manufacture method of magnetic funnel node device Download PDF

Info

Publication number
CN103123954B
CN103123954B CN201110371148.2A CN201110371148A CN103123954B CN 103123954 B CN103123954 B CN 103123954B CN 201110371148 A CN201110371148 A CN 201110371148A CN 103123954 B CN103123954 B CN 103123954B
Authority
CN
China
Prior art keywords
materials
hard mask
mtj
mask layer
advanced low
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201110371148.2A
Other languages
Chinese (zh)
Other versions
CN103123954A (en
Inventor
张海洋
周俊卿
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Manufacturing International Shanghai Corp
Original Assignee
Semiconductor Manufacturing International Shanghai Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Manufacturing International Shanghai Corp filed Critical Semiconductor Manufacturing International Shanghai Corp
Priority to CN201110371148.2A priority Critical patent/CN103123954B/en
Publication of CN103123954A publication Critical patent/CN103123954A/en
Application granted granted Critical
Publication of CN103123954B publication Critical patent/CN103123954B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Landscapes

  • Mram Or Spin Memory Techniques (AREA)
  • Hall/Mr Elements (AREA)

Abstract

The invention provides a kind of manufacture method of magnetic funnel node device, comprising: Semiconductor substrate is provided; Form MTJ stepped construction on the semiconductor substrate; Described formation MTJ stepped construction forms advanced low-k materials; Described advanced low-k materials is formed the hard mask layer of patterning; With the hard mask layer of described patterning for mask, remove a part of described advanced low-k materials by etch step, in described advanced low-k materials, form hole; Deposition oxide on described hard mask layer and in described hole; Remove the described oxide outside described hole by cmp step, by described oxide surface polishing, and remove described hard mask layer; Remove described advanced low-k materials, form the column structure that described oxide is formed.

Description

A kind of manufacture method of magnetic funnel node device
Technical field
The present invention relates to a kind of manufacture method of magnetic RAM part, particularly relate in the technical process manufacturing magnetic funnel node device, a kind ofly form improving one's methods of hard mask.
Background technology
Magnetic RAM (MagneticRandomAccessMemory, MRAM) device is widely used as nonvolatile memory.In a mram, data are stored by the magnetic state of memory element.Mram cell forms a memory cell jointly by a transistor and a MTJ (MTJ) usually.Described mtj structure comprises at least two electromagnetic layer and the insulating barrier for isolating described two electromagnetic layer.Described two electromagnetic layer can maintain two magnetic polarization fields of being separated by insulating barrier, and one of them is fixed magnetic layer, or are called pinned (pinned) layer, and its polarised direction is fixing; Another freely rotates magnetosphere, and its polarised direction can change with the change of external field.When the polarised direction of two electromagnetic layer is parallel, the tunnelling current flowing through mtj structure has maximum, and mtj structure cell resistance is lower; When two magnetospheric polarised direction antiparallels, the tunnelling current flowing through mtj structure has minimum value, and mtj structure cell resistance is higher.Information is read, the operation principle of Here it is mtj structure by measuring the resistance of mram cell.
As shown in Figure 1, be the existing mtj structure schematic diagram of one, wherein fixed magnetic layer 110, freely rotate magnetosphere 120 and at fixed magnetic layer 110 and the tunnel barrier layer 130 that freely rotates between magnetosphere 120.Described fixed magnetic layer 110, freely rotate magnetosphere 120 and tunnel barrier layer 130 is all cylinder (or cylindroid) type structure.
In integrated circuit fabrication process, transistor manufacture is commonly referred to front-end-of-line (FEOL) technological process, mtj stack be formed in transistor after, therefore, the formation of mtj stack should be compatible with standard last part technology (BEOL) technological process.And, due to the special nature of magnetic material, high-temperature technology flow process can not be adopted after mtj structure storehouse deposition.
In the mtj structure etching technics of mram cell, need the oxide after first forming composition on the magnetic material of mtj stack as mask, define MTJ cell region.This oxide mask is column structure, in the prior art, by directly defining the composition of column on the photoresist by photoetching process, then adopts dry etching drawing to be transferred on oxide.Because the critical dimension of column type mtj structure is very little, FA lithographic equipment must be adopted to define litho pattern, this can cause MRAM manufacturing cost to rise.In addition, manufacture mtj structure by prior art, the photoresist layer in dry etch process process after composition is easy to be consumed light, and then makes oxide mask coarse, thus causes the inconsistency of the poor and shape of formed mtj structure critical size.
Therefore need a kind of improving one's methods without the need to high-temperature technology, form the oxide mask with the column structure of good critical size and shape coincidence, thus prepare the mtj structure in mram cell.
Summary of the invention
The invention provides a kind of method, form the oxide mask with the column structure of good critical size and shape coincidence, thus prepare mtj structure.
According to the manufacture method that the invention provides a kind of magnetic funnel node device, comprising:
Semiconductor substrate is provided; Form MTJ stepped construction on the semiconductor substrate; Described formation MTJ stepped construction forms advanced low-k materials; Described advanced low-k materials is formed the hard mask layer of patterning; With the hard mask layer of described patterning for mask, remove a part of described advanced low-k materials by etch step, in described advanced low-k materials, form hole; Deposition oxide on described hard mask layer and in described hole; Remove the described oxide outside described hole by cmp step, by described oxide surface polishing, and remove described hard mask layer; Remove described advanced low-k materials, form the column structure that described oxide is formed.
Preferably, wherein said Semiconductor substrate comprises transistor and for the interconnect architecture of MTJ cell being electrically connected described transistor and formed subsequently.
Preferably, wherein said MTJ stepped construction at least comprises fixed magnetic layer, tunnel barrier layer and freely rotates magnetosphere.
Preferably, wherein said advanced low-k materials is porous low dielectric constant material.
Preferably, spin coating method is adopted to deposit described porous ultra-low dielectric constant material.
Preferably, the polymer penetration step performed after forming described advanced low-k materials.
Preferably, wherein said hard mask layer is titanium nitride (TiN) or boron nitride (BN).
Preferably, wherein said etch step is dry etching.
Preferably, after the described cmp step of execution, also heating steps is comprised.
Preferably, wherein said column structure is elliptical cylinder-shape or cylindrical.
Accompanying drawing explanation
Following accompanying drawing of the present invention in this as a part of the present invention for understanding the present invention.Shown in the drawings of one embodiment of the present of invention and description thereof, be used for explaining principle of the present invention.In the accompanying drawings,
Fig. 1 is the existing magnetic funnel node device structural representation of one;
Fig. 2 A-2J be according to one embodiment of the invention make magnetic funnel node device manufacture method flow process in the schematic diagram of each step, wherein Fig. 2 A-2I is longitdinal cross-section diagram, and Fig. 2 J is vertical view;
Fig. 3 is the process chart making magnetic funnel node device according to one embodiment of the invention.
Symbol description:
Fig. 1
110: fixed magnetic layer, 120: freely rotate magnetosphere, 130: tunnel barrier layer
Fig. 2
200: Semiconductor substrate, 210:MTJ stepped construction, 211: fixed magnetic layer, 212: tunnel barrier layer, 213: freely rotate magnetosphere, 214: the first electrode layers, 220: porous low k material, 230: hard mask layer, 240: photoresist layer, 250: hole, 260: oxide, 270: the column structure of required form.
Embodiment
Next, will more intactly describe the present invention by reference to the accompanying drawings, shown in accompanying drawing, describe inventive embodiment as the cross-sectional view of the schematic diagram of desirable embodiment of the present invention (and intermediate structure).In the accompanying drawings, in order to clear, the size in Ceng He district and relative size may be exaggerated.Further, due to such as manufacturing technology and/or tolerance, shown change of shape is caused.Therefore, embodiments of the invention should not be confined to the specific size shape in district shown here, but comprise owing to such as manufacturing the form variations caused.The district shown in figure is in fact schematic, and their shape is not intended the actual size in the district of display device and shape and is not intended to limit scope of the present invention.The present invention can implement in different forms, and should not be interpreted as the embodiment that is confined to propose here.On the contrary, provide these embodiments will expose thoroughly with complete, and scope of the present invention is fully passed to those skilled in the art.
The object of term is only to describe specific embodiment and not as restriction of the present invention as used herein.Should be noted that, when element or layer be called as " ... on ", " with ... adjacent ", " being connected to " or " being coupled to " other element or layer time, its can directly on other element or layer, with it adjacent, connect or be coupled to other element or layer, or the element that can exist between two parties or layer.On the contrary, when element be called as " directly exist ... on ", " with ... direct neighbor ", " being directly connected to " or " being directly coupled to " other element or layer time, then there is not element between two parties or layer.It should be noted that " one " of singulative, " one " and " described/should " also intention comprise plural form, unless context is known point out other mode.Also should be noted that, term " composition " and/or " comprising ", when using in these specifications, determine the existence of described feature, integer, step, operation, element and/or parts, but do not get rid of one or more other feature, integer, step, operation, element, the existence of parts and/or group or interpolation.When this uses, term "and/or" comprises any of relevant Listed Items and all combinations.
First, please refer to shown in Fig. 2 A, the dielectric layer 200 in Semiconductor substrate and Semiconductor substrate is provided.Described Semiconductor substrate comprises transistor and the inner interconnection structure for being electrically connected transistor, does not illustrate in the drawings in order to accompanying drawing is easy.Described Semiconductor substrate also comprises the dielectric layer in Semiconductor substrate, wherein also comprises interconnection structure, for the transistor be electrically connected in Semiconductor substrate and the MTJ cell formed subsequently.
Then, please refer to shown in Fig. 2 B, described Semiconductor substrate 200 forms MTJ stepped construction 210.Form described MTJ stepped construction 210 at least to comprise and form the first electrode layer 211, fixed magnetic layer 213, tunnel barrier layer 215 successively and freely rotate magnetosphere 217.In an embodiment of the present invention, described MTJ stepped construction comprises the TaN that thickness is 100 successively, and thickness is the MnIr of 150, and thickness is the CoFe of 40, and thickness is the MgO of 35, and thickness is the CoFeB of 50, and thickness is the Ru of 150.Wherein, TaN and MnIr forms fixed magnetic layer, and MgO is tunnel barrier layer, CoFeB and Ru composition freely rotates magnetosphere.
Then, please refer to shown in Fig. 2 C, described MTJ stepped construction 210 forms porous low k material 220.Generally speaking, the dielectric constant k<4 of low-k materials, for organic dielectric materials or the siliceous inorganic material of single or multiple lift, comprise the organic polymer materials such as polyimide, Parylene class, polyene chain class, the inorganic material such as the silicon dioxide fluoridized, amorphous carbon nitrogen film, hydrogen base silsesquioxane (Hydrogensilsesquioxane, HSQ, (HSiO 3/2) n), poly methyl silsesquioxane (Methylsilsesquioxane, MSQ, (CH 3siO 3/2) n) etc. silica-based porous low k material, and nanometer low-k materials.Porous low k material can adopt chemical vapour deposition technique (CVD) or spin coating method (Spin-OnDeposition, SOD) to be deposited in substrate, then through solidifying to form dielectric layer.In an embodiment of the present invention, porous low k material 220 adopts spin coating method (SOD) to deposit.Because the film at porous low k deposited on materials follows the pattern of this porous media to a great extent, the roughness of porous low k material can affect the effect as mask or diffusion impervious layer of film on it.Therefore, preferably, after deposited porous low-k materials, perform polymer penetration step filling pore, porous low k material 220 is strengthened process.
Then, please refer to shown in Fig. 2 D, described porous low k material 220 forms hard mask layer 230.The deposition process of hard mask such as adopts chemical vapour deposition (CVD), plasma enhanced chemical vapor deposition, chemical solution deposition, evaporation, or by heat treatment, such as oxidation or nitrogenize, form hard mask.Hard mask comprises oxide, nitride, oxynitride or their multiple layer combination.In an embodiment of the present invention, described hard mask layer 230 is metal hard mask, preferably, is titanium nitride (TiN) or boron nitride (BN).
Then, please refer to shown in Fig. 2 E ~ 2F, remove a part of porous low k material 220 and hard mask layer 230 by photoetching process and etch step, form the hole 250 of required form.First normal photolithographic process forms photoresist oxidant layer on hard mask layer 230, then exposes this photoresist and forms required composition, and the baking process after then exposing also uses developer that composition is developed, thus forms photoresist layer 240 as shown in Figure 2 E.Adopt conventional etching process such as dry etching to implement main etching operation subsequently, figure is transferred to hard mask layer 230 and porous low k material 220 from the photoresist of patterning, forms the hole 250 of required form as shown in Figure 2 F.Irregularly shaped such as needed for elliptical cylinder-shape, cylindrical or other any formation mtj structure of described hole 250.Photoresist layer 240 after composition is removed by photoresistance ashing (PhotoResistAshing) process after figure is transferred to hard mask layer 230 and porous low k material 220.
Subsequently, please refer to shown in Fig. 2 G, on described hard mask layer 230 and in the hole 250 of described porous low k material 220 and hard mask layer 230 formation, deposition oxide 260 is to fill hole 250.Subsequently, please refer to shown in Fig. 2 H, by cmp (ChemicalMechanicPolishing, CMP) method by the surface finish of described oxide 260, oxide 260 unnecessary for major part is removed, and removes hard mask layer 230.This chemical mechanical milling tech can adopt the grinding agent in general conventional art.Preferably, after cmp step, for the porous low k material 220 by polymer penetration step filling pore, it is made to restore to the original state by heating steps.
Finally, please refer to shown in Fig. 2 I, remove described porous low k material 220, form the column structure 270 of the required form that oxide 260 is formed.Fig. 2 J is column structure 270 vertical view in an embodiment of the invention that dielectric layer 200 in described Semiconductor substrate and MTJ stepped construction 210 are formed, and wherein column structure 270 is elliptical cylinder structure.
The Making programme of magnetic funnel node device is made as shown in Figure 3 according to one embodiment of the invention.In step 301, Semiconductor substrate is provided.In step 302, MTJ stepped construction is formed on the semiconductor substrate.In step 303, described MTJ stepped construction forms porous low k material.In step 304, described porous low k material forms hard mask layer.In step 305, remove a part of porous low k material and hard mask layer by photoetching process and etch step such as dry etching, formation elliptical cylinder-shape, the erose hole that cylindrical or other is needed for any formation mtj structure.Within step 306, on described hard mask layer and in the hole that formed of described porous low k material and hard mask layer deposition oxide to fill hole.In step 307, by chemical mechanical milling method by described oxide surface polishing, oxide unnecessary for major part is removed, and removes hard mask layer.In step 308, remove described porous low k material, form the column structure of the required form that oxide is formed.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment just for the object of illustrating and illustrate, and is not intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, more kinds of variants and modifications can also be made according to instruction of the present invention, within these variants and modifications all drop on the present invention's scope required for protection.Protection scope of the present invention defined by the appended claims and equivalent scope thereof.

Claims (8)

1. a manufacture method for magnetic funnel node device, comprising:
Semiconductor substrate is provided;
Form MTJ stepped construction on the semiconductor substrate;
Described formation MTJ stepped construction forms advanced low-k materials, and described advanced low-k materials is porous low dielectric constant material;
Perform polymer penetration step;
Described advanced low-k materials is formed the hard mask layer of patterning;
With the hard mask layer of described patterning for mask, remove a part of described advanced low-k materials by etch step, in described advanced low-k materials, form hole;
Deposition oxide on described hard mask layer and in described hole;
Remove the described oxide outside described hole by cmp step, by described oxide surface polishing, and remove described hard mask layer;
Remove described advanced low-k materials, form the column structure that described oxide is formed.
2. method according to claim 1, wherein said Semiconductor substrate comprises transistor and for the interconnect architecture of MTJ cell being electrically connected described transistor and formed subsequently.
3. method according to claim 1, wherein said MTJ stepped construction at least comprises fixed magnetic layer, tunnel barrier layer and freely rotates magnetosphere.
4. method according to claim 1, is characterized in that, adopts spin coating method to deposit described porous low dielectric constant material.
5. method according to claim 1, wherein said hard mask layer is titanium nitride (TiN) or boron nitride (BN).
6. method according to claim 1, wherein said etch step is dry etching.
7. method according to claim 1, is characterized in that, after the described cmp step of execution, also comprises heating steps.
8. method according to claim 1, wherein said column structure is elliptical cylinder-shape or cylindrical.
CN201110371148.2A 2011-11-21 2011-11-21 A kind of manufacture method of magnetic funnel node device Active CN103123954B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201110371148.2A CN103123954B (en) 2011-11-21 2011-11-21 A kind of manufacture method of magnetic funnel node device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201110371148.2A CN103123954B (en) 2011-11-21 2011-11-21 A kind of manufacture method of magnetic funnel node device

Publications (2)

Publication Number Publication Date
CN103123954A CN103123954A (en) 2013-05-29
CN103123954B true CN103123954B (en) 2015-11-25

Family

ID=48454883

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201110371148.2A Active CN103123954B (en) 2011-11-21 2011-11-21 A kind of manufacture method of magnetic funnel node device

Country Status (1)

Country Link
CN (1) CN103123954B (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104659201B (en) * 2013-11-22 2018-07-20 中芯国际集成电路制造(上海)有限公司 A kind of manufacturing method of resistance internal memory unit
US9379314B2 (en) * 2013-12-17 2016-06-28 Qualcomm Incorporated Hybrid synthetic antiferromagnetic layer for perpendicular magnetic tunnel junction (MTJ)
CN107785485B (en) * 2016-08-31 2021-06-01 中电海康集团有限公司 Preparation method of magnetic tunnel junction
WO2018195424A1 (en) * 2017-04-21 2018-10-25 Everspin Technologies, Inc. Methods for integrating magnetoresistive devices

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101060079A (en) * 2006-04-21 2007-10-24 台湾积体电路制造股份有限公司 Method of forming a low-K dielectric thin film

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030001109A (en) * 2001-06-28 2003-01-06 주식회사 하이닉스반도체 A fabricating method of capacitor using low-k sacrificial layer
US20060022286A1 (en) * 2004-07-30 2006-02-02 Rainer Leuschner Ferromagnetic liner for conductive lines of magnetic memory cells
US8542524B2 (en) * 2007-02-12 2013-09-24 Avalanche Technology, Inc. Magnetic random access memory (MRAM) manufacturing process for a small magnetic tunnel junction (MTJ) design with a low programming current requirement

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101060079A (en) * 2006-04-21 2007-10-24 台湾积体电路制造股份有限公司 Method of forming a low-K dielectric thin film

Also Published As

Publication number Publication date
CN103123954A (en) 2013-05-29

Similar Documents

Publication Publication Date Title
US10644231B2 (en) Memory device and fabrication method thereof
US6806096B1 (en) Integration scheme for avoiding plasma damage in MRAM technology
CN108232009B (en) Method for manufacturing magnetic random access memory
US10008536B2 (en) Encapsulation of magnetic tunnel junction structures in organic photopatternable dielectric material
US6713802B1 (en) Magnetic tunnel junction patterning using SiC or SiN
US10276794B1 (en) Memory device and fabrication method thereof
US11355701B2 (en) Integrated circuit
US11171284B2 (en) Memory device
CN102956816B (en) Hole hard mask formerly limits
US6635496B2 (en) Plate-through hard mask for MRAM devices
WO2004114373A2 (en) Stud formation for mram manufacturing
US20210098693A1 (en) Memory device and method for manufacturing the same
US11189791B2 (en) Integrated circuit and fabrication method thereof
CN103123954B (en) A kind of manufacture method of magnetic funnel node device
US8026112B2 (en) Method of manufacturing semiconductor device
US8519497B2 (en) Template-registered diblock copolymer mask for MRAM device formation
US6849465B2 (en) Method of patterning a magnetic memory cell bottom electrode before magnetic stack deposition
JP2005526389A (en) Method for manufacturing MRAM offset cell in double damascene structure with reduced number of etching steps
KR101202685B1 (en) Method for fabricating magnetic tunnel junction
CN111668366A (en) Top electrode contact of magnetic random access memory and preparation method thereof
KR20120094394A (en) Method for fabicating magnetic tunnel junction
US10312435B1 (en) Method for manufacturing high density magnetic tunnel junction devices using photolithographic VIAS and chemically guided block copolymer self assembly
US20210375985A1 (en) Semiconductor structure and method of forming the same
US10305031B1 (en) Method for manufacturing a chemical guidance pattern for block copolymer self assembly from photolithographically defined topographic block copolymer guided self assembly
CN111816224A (en) Preparation method of magnetic tunnel junction storage array unit and peripheral circuit thereof

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant