CN103107074B - A kind of formation method of metal gates - Google Patents
A kind of formation method of metal gates Download PDFInfo
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- CN103107074B CN103107074B CN201110357958.2A CN201110357958A CN103107074B CN 103107074 B CN103107074 B CN 103107074B CN 201110357958 A CN201110357958 A CN 201110357958A CN 103107074 B CN103107074 B CN 103107074B
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Abstract
A formation method for metal gates, comprising: provide Semiconductor substrate, and described Semiconductor substrate comprises the first transistor district and transistor seconds district; Form the alternative gate of doping on the semiconductor substrate, described alternative gate is positioned at described first crystal area under control and transistor seconds district simultaneously; The alternative gate in first crystal area under control described in first dry etching, forms the first groove, the first groove described in wet-cleaned; In the first groove, fill full metal, form the first metal gates; The alternative gate in transistor seconds district described in second dry etching, forms the second groove, and forms the second metal gates in the second groove.The removal alternative gate that method energy of the present invention is clean, improves the work function of metal gates.
Description
Technical field
The present invention relates to field of semiconductor fabrication, particularly a kind of formation method of metal gates.
Background technology
Along with the characteristic size of semiconductor device is more and more less, the also corresponding reduction of area shared by corresponding core devices, cause the energy density of unit are significantly to increase, electrical leakage problems highlights more, and power consumption also increases thereupon.Therefore, in the technique below 45 nanometers, the technique of traditional with silicon dioxide the is gate dielectric layer of material runs into bottleneck, cannot meet the technological requirement of semiconductor device; For solving above-mentioned bottleneck, adopt high-k (high k:k value is more than or equal to 10) dielectric material as gate dielectric layer at present, then, formed with metal be material grid with reduce electric leakage, power consumption is well controlled.
The technique preparing metal gates at present mainly contains two kinds of methods, is " first grid " and " post tensioned unbonded prestressed concrete " respectively." post tensioned unbonded prestressed concrete " is also called replacement grid, and when using this technique, high-dielectric-coefficient grid medium layer is without the need to through high-temperature step, so threshold voltage V
toffset very little, the reliability of chip is higher.Therefore, post tensioned unbonded prestressed concrete technique is more widely used.
Publication number is that the american documentation literature of US2002/0064964A1 discloses a kind of method using " rear grid " technique to form metal gates, comprise: Semiconductor substrate is provided, described Semiconductor substrate be formed with alternative gate and be positioned in described Semiconductor substrate and cover the interlayer dielectric layer of described alternative gate; Using described alternative gate as stop-layer, chemical mechanical milling tech (CMP) is carried out to described interlayer dielectric layer; Groove is formed after removing described alternative gate; In described groove, metal is filled, to form metal gate electrode layer by PVD method; With chemical mechanical milling method abrasive metal gate electrode layer to exposing interlayer dielectric layer, form metal gates.Because metal gates makes after source-drain area has injected again, this makes the quantity of subsequent technique be reduced, and avoids the problem that metal material is unsuitable for carrying out high-temperature process.
At current static random access memory (Static Random Access Memory, SRAM) in memory circuit, the grid of a nmos pass transistor is electrically connected with the grid of a PMOS transistor usually, in the making of existing SRAM memory, usually by the fabrication of nmos pass transistor and PMOS transistor in same grid structure, to improve SRAM integrated level, reduce process complexity.
With reference to figure 1, Fig. 1 is the plan structure schematic diagram of the SRAM memory part-structure with shared alternative gate, comprise: Semiconductor substrate (not shown), described Semiconductor substrate comprises first area 109 and second area 110, be positioned at the nmos pass transistor 80 on first area 109, be positioned at the PMOS transistor 60 on second area 110, described nmos pass transistor 80 and PMOS transistor 60 have shared alternative gate 112, described alternative gate 112 is positioned at first area 109 and second area 110 simultaneously, and the material of described alternative gate 112 is polysilicon; Dielectric layer (not shown), it is concordant with alternative gate 112 surface that described dielectric layer covers Semiconductor substrate.Because nmos pass transistor 80 is different with the work function of PMOS transistor 60, therefore the materials and process of the metal gates of nmos pass transistor 80 and the metal gates of PMOS transistor 60 is all different, needs to be formed respectively.Namely first utilize dry etch process to remove the alternative gate 112 of first area 109, in the groove that etching is formed, form the metal gates being applicable to nmos pass transistor 80 in first area 109; Then the alternative gate 112 of second area 110 is removed, the metal gates being applicable to PMOS transistor 60 in second area 110 is formed in the groove that etching is formed, above-mentioned formation method can remain polysilicon in groove, affects the work function of the metal gates of follow-up formation, affects the stability of device.
Summary of the invention
The problem that the present invention solves is to provide a kind of formation method of metal gates, is removed by the polysilicon of alternative gate clean, improves the stability of device.
For solving the problem, the invention provides a kind of formation method of metal gates, comprising:
There is provided Semiconductor substrate, described Semiconductor substrate comprises the first transistor district and transistor seconds district;
Form the alternative gate of doping on the semiconductor substrate, described alternative gate is positioned at described first crystal area under control and transistor seconds district simultaneously;
The alternative gate in first crystal area under control described in first dry etching, forms the first groove, the first groove described in wet-cleaned;
In the first groove, fill full metal, form the first metal gates;
The alternative gate in transistor seconds district described in first dry etching, forms the second groove, and forms the second metal gates in the second groove.
Optionally, the solution that described wet-cleaned adopts is tetramethyl ammonium hydroxide solution.
Optionally, the concentration range of described tetramethyl ammonium hydroxide solution is 1% ~ 10%.
Optionally, the time of described wet-cleaned is 5 ~ 10 seconds.
Optionally, described Doped ions is boron ion, phosphonium ion, arsenic ion, carbon ion or Nitrogen ion.
Optionally, described alternative gate material is polysilicon or unformed silicon.
Optionally, the gas that described first dry etching adopts is hydrogen bromide and chlorine.
Optionally, the gas that described second dry etching adopts is hydrogen bromide.
Optionally, also gate dielectric layer is formed with between described alternative gate and Semiconductor substrate.
Optionally, described Semiconductor substrate is also formed with isolation structure.
Optionally, described Semiconductor substrate is also formed with dielectric layer, described dielectric layer surface is with to be formed with isolation structure concordant with alternative gate surface.
Optionally, described first crystal area under control is PMOS transistor district, and described transistor seconds district is nmos pass transistor district.
Optionally, described first crystal area under control is nmos pass transistor district, and described transistor seconds district is PMOS transistor district.
Compared with prior art, technical solution of the present invention has the following advantages:
The alternative gate in the first dry etching first crystal area under control, after forming the first groove, wet-cleaned first groove, can remove alternative gate material remaining in the first groove, follow-uply forms the first metal gates at the first groove, improves the work function of the first metal gates;
Further, the alternative gate formed on the semiconductor substrate is the polysilicon of doping or unformed silicon, the speed of wet etching can be reduced after polysilicon or unformed silicon doping, when first groove in wet-cleaned first crystal area under control, the etch amount etching the molten alternative gate to transistor seconds district is ignored, the alternative gate width in transistor seconds district can not be reduced, ensure that the metal gates width that follow-up transistor seconds district is formed can not reduce, meet the requirement of technique, improve the stability of device;
Etching solution adopts tetramethyl ammonium hydroxide solution (TMAH), tetramethyl ammonium hydroxide solution (TMAH) is not containing metal ion, do not have the residual of metal ion after etching and pollute, can not cause damage to semiconductor device, and there is very high etching selection ratio.
Accompanying drawing explanation
Fig. 1 is the existing plan structure schematic diagram with the SRAM memory part-structure of common alternative gate;
Fig. 2 ~ Fig. 4 is the existing structural representation of method for forming metallic grid along the line of cut A-B direction shown in Fig. 1 with the SRAM memory of shared alternative gate;
Fig. 5 is the schematic flow sheet of embodiment of the present invention method for forming metallic grid;
Fig. 6 is that the embodiment of the present invention has the PMOS of shared alternative gate and the plan structure schematic diagram of nmos pass transistor;
Fig. 7 ~ Figure 11 is for embodiment of the present invention method for forming metallic grid is along the cross-sectional view in the line of cut A-B direction shown in Fig. 6.
Embodiment
Inventor finds in the manufacturing process of existing SRAM memory, when adopting dry etching to remove PMOS transistor and nmos pass transistor common gate structures, process conditions are difficult to control, polysilicon has the sidewall of groove and the intersection of gate dielectric layer that are formed after part remains in removal PMOS transistor or nmos pass transistor common gate structures, specifically please refer to Fig. 2, Fig. 2 is the existing structural representation along the line of cut A-B direction shown in Fig. 1 with the SRAM memory of shared alternative gate, comprise: Semiconductor substrate 100, described Semiconductor substrate 100 comprises first area 109 and second area 110, be positioned at the nmos pass transistor 80 on first area 109, be positioned at the PMOS transistor 60 on second area 110, described nmos pass transistor 80 and PMOS transistor 60 have shared alternative gate 112, gate dielectric layer 106 is also formed between described alternative gate 112 and Semiconductor substrate 100, with reference to figure 3, the alternative gate 112 of dry etching NMOS first area 109, form groove 104, due to the restriction of dry etch process condition, partial polysilicon 105 is remained at the intersection of groove 104 and gate dielectric layer 106, follow-up when forming the metal gates 104a of the nmos pass transistor 80 shown in Fig. 4 in groove 104, because remaining polycrystalline silicon exists, affect the work function of nmos pass transistor 80 metal gates, affect the stability of device.
Inventor studies discovery further, when dry etching, the intersection can being removed groove 104 and gate dielectric layer 106 by the flow that strengthens etching gas or the method that increases the over etchings such as etch period remains partial polysilicon, but the method for over etching, when the alternative gate 112 removing first area 109 forms groove 104, the alternative gate 112 of second area 110 and the partial polysilicon of groove 104 contact-making surface can be etched away, the width of the alternative gate 112 of second area 110 is reduced, it is follow-up when second area 110 forms the metal gates of PMOS transistor 60, the width of PMOS transistor 60 metal gates is reduced, affect the work function of the metal gates of PMOS transistor 60.
For solving the problem, inventor proposes a kind of manufacture method of metal gates, comprising: provide Semiconductor substrate, and described Semiconductor substrate comprises the first transistor district and transistor seconds district; Form the alternative gate of doping on the semiconductor substrate, described alternative gate is positioned at described first crystal area under control and transistor seconds district simultaneously; The alternative gate in first crystal area under control described in first dry etching, forms the first groove, the first groove described in wet-cleaned; In the first groove, fill full metal, form the first metal gates; The alternative gate in transistor seconds district described in second dry etching, forms the second groove, and forms the second metal gates in the second groove.Method of the present invention can be clean by the etching polysilicon of alternative gate, improves device stability.
For enabling above-mentioned purpose of the present invention, feature and advantage become apparent more, are described in detail the specific embodiment of the present invention below in conjunction with accompanying drawing.When describing the embodiment of the present invention in detail, for ease of illustrating, following schematic diagram can be disobeyed general ratio and be made partial enlargement, and described schematic diagram is example, and it should not limit the scope of the invention at this.In addition, the three-dimensional space of length, width and the degree of depth should be comprised in actual fabrication.
With reference to the schematic flow sheet that figure 5, Fig. 5 is embodiment of the present invention method for forming metallic grid, comprising:
Step S201, provides Semiconductor substrate, and described Semiconductor substrate comprises the first transistor district and transistor seconds district;
Step S202, forms the alternative gate of doping on the semiconductor substrate, and described alternative gate is positioned at described first crystal area under control and transistor seconds district simultaneously;
Step S203, the alternative gate in first crystal area under control described in the first dry etching, forms the first groove, the first groove described in wet-cleaned;
Step S204, fills full metal, forms the first metal gates in the first groove;
Step S205, the alternative gate in transistor seconds district described in the second dry etching, forms the second groove;
Step S206, fills full metal, forms the second metal gates in the second groove.
Fig. 6 is that the embodiment of the present invention has the PMOS of shared alternative gate and the plan structure schematic diagram of nmos pass transistor; Fig. 7 ~ Figure 11 is for embodiment of the present invention method for forming metallic grid is along the cross-sectional view in the line of cut A-B direction shown in Fig. 6.
In the lump with reference to figure 6 and Fig. 7, Semiconductor substrate 300 is provided, described Semiconductor substrate 300 comprises first crystal area under control I and transistor seconds district II, described first crystal area under control I is formed with transistor 50, for PMOS transistor, described transistor seconds district II is formed with transistor 30, for nmos pass transistor, PMOS transistor 50 and nmos pass transistor 30 have shared alternative gate 305, described alternative gate 305 part is positioned at first crystal area under control I and another part is positioned at transistor seconds district II, nmos pass transistor 30 and PMOS transistor 50 also comprise the source-drain area 310 and first crystal area under control I and the surperficial side wall (figure is for illustrating) around alternative gate 305 of transistor seconds district II that are arranged in alternative gate 305 both sides first crystal area under control I and transistor seconds district II.In other embodiments of the present invention, the transistor 50 that described first crystal area under control I is formed is nmos pass transistor, and the transistor 30 that transistor seconds district II is formed is PMOS transistor.
In the present embodiment, described alternative gate 305 is the polysilicon of doping, and alternative gate 305 detailed process forming gate dielectric layer 304 and doping is: form the gate dielectric membrane (not shown) covering described Semiconductor substrate 300; Adopting the method for low-pressure chemical vapor deposition to be formed and cover the doped polysilicon layer (not shown) of described gate dielectric membrane, including containing needing the gas of Doped ions in the source gas that described low-pressure chemical vapor deposition adopts; Etch described doped polysilicon layer and gate dielectric layer, form gate medium 304 on first crystal area under control I and transistor seconds district II surface and be positioned at the alternative gate 305 of the doping on gate dielectric layer 304.
Compared to forming the rear method adopting ion implantation to adulterate to alternative gate 305 of alternative gate 305, the method that the embodiment of the present invention adopts reduces can processing step, saving can cost, and damage can not be caused to grid layer 304, ion implantation energy is comparatively large, and the ion of injection is easily injected into gate dielectric layer 304.
The Doped ions of described alternative gate 305 is boron ion, phosphonium ion, arsenic ion, one in carbon ion or Nitrogen ion, the object that alternative gate 305 adulterates is, after the alternative gate 305 of follow-up dry etching first crystal area under control I forms the first groove, need to carry out wet-cleaned to the first groove, to remove polysilicon remaining in the first groove, if alternative gate 305 does not have Doped ions, due to the isotropic feature of wet-cleaned, the alternative gate 305 of transistor seconds district II and the polysilicon of the first groove interface also have part to be etched away, the width of the II alternative gate 305 in transistor seconds district is reduced, the width of the metal gates of follow-up formation also can reduce, affect the stability of device, and after alternative gate 305 is adulterated, wet-cleaned solution reduces the etch rate of the polysilicon of doping, in first groove of wet-cleaned first crystal area under control I during remaining polysilicon, the wet-cleaned time is very short, the etch amount of the alternative gate 305 of transistor seconds district II and the polysilicon of the first groove interface is ignored, the width of the alternative gate 305 of transistor seconds district II can not be reduced, the metal gate width of follow-up formation also can not reduce, remaining polysilicon can be removed, can not have an impact to the stability of device again, meet the requirement of technique.
In other embodiments of the invention, described alternative gate 305 is the unformed silicon of doping, also can reach above-mentioned effect, not repeating at this when etching alternative gate 305.
Gate dielectric layer 304 is also formed between described alternative gate 305 and Semiconductor substrate 300.
Described gate dielectric layer 304 is high dielectric constant material, is specifically as follows HfO
2, TiO
2, HfZrO, Ta
2o
3, ZrO
2, ZrSiO
2one or its combination, described gate dielectric layer 304 can be formed by atom deposition method (ALD) or other technique.
Described Semiconductor substrate 300 is also formed with dielectric layer 303, the method forming described dielectric layer 303 is: adopt chemical vapour deposition technique to form dielectric film (not shown) in Semiconductor substrate 300, described dielectric film covers alternative gate 305; Described in the method planarization of employing cmp, dielectric film is to exposing alternative gate 305 top, forms the dielectric layer 303 concordant with alternative gate 305 top.The material of described dielectric layer 303 is silicon dioxide or silicon nitride.
Also be formed with isolation structure 302 in described Semiconductor substrate 300, for the isolation between transistor, in the particular embodiment, described isolation structure 302 is shallow trench isolation (STI).
With reference to figure 8, the alternative gate 305 of first crystal area under control I described in first dry etching, form the first groove 306, first groove 306 described in wet-cleaned, concrete processing step is: form the mask layer (not shown) covering described dielectric layer 303 and alternative gate 305 surface, graphical described mask layer, exposes the surface of the alternative gate 305 of the first crystal area under control I that need etch; Adopt the alternative gate 305 of the first dry etching first crystal area under control I, form the first groove 306; First groove 306 described in wet-cleaned, removes polysilicon remaining in the first groove 306; Remove described mask layer.
Described first dry etching is plasma etching, the gas that plasma etching adopts is hydrogen bromide (HBr) and chlorine (Cl2), during the alternative gate 305 of the first dry etching first crystal area under control I, be divided into main etching and two stages of over etching, main etching removes main polysilicon, over etching removes remaining polysilicon, in the over etching stage, the amount of over etching can not be too large, the amount of over etching is generally determined by etching gas flow and etch period, the alternative gate 305 of Hua Huishi transistor seconds district II that the amount of over etching is too large and the interface of the first groove 306 present arc, the alternative gate 305 of subsequent etching transistor seconds district II is made to form the second metal gates, the width of the second metal gates reduces, affect the work function of the second metal gates, in order to the interface of the alternative gate 305 and the first groove 306 that ensure transistor seconds district II can not present arc, the over etching stage, the amount of over etching can reduce, therefore after the alternative gate 305 of the first dry etching first crystal area under control I, a small amount of polysilicon is remained at the sidewall of the first groove 306 and gate dielectric layer 304 intersection, during follow-up formation the first metal gates, due to the existence of polysilicon, affect the work function of the first metal gates, affect the stability of device.
After formation first groove 306, adopt the first groove 306 described in wet-cleaned, remove the polysilicon that the first groove 306 sidewall and gate dielectric layer 304 intersection are residual, the very thin thickness of remaining polycrystalline silicon or volume are very little, the time of wet-cleaned is 5 ~ 10S, the time of wet etching is shorter, when cleaning the first groove 306, the etch amount of the alternative gate 305 of transistor seconds district II and the polysilicon of the first groove interface is ignored, the width of the alternative gate 305 of transistor seconds district II can not be reduced, the metal gate width of follow-up formation also can not reduce, remaining polysilicon can be removed, can not have an impact to the stability of device again, meet the requirement of technique.
The solution that described wet-cleaned adopts is tetramethyl ammonium hydroxide solution (TMAH), tetramethyl ammonium hydroxide solution (TMAH) is not containing metal ion, do not have the residual of metal ion after etching and pollute, can not cause damage to semiconductor device, and there is very high etching selection ratio, described tetramethyl ammonium hydroxide solution, concentration is 1% ~ 10%, because the polysilicon of the first groove remnants is little, tetramethyl ammonium hydroxide solution concentration is too not high, avoid the impact of the alternative gate 305 on transistor seconds district II, concentration is too low, etch rate reduces, increase the wet-cleaned time, add cost of manufacture.
With reference to figure 8 and 9, full metal is filled in the first groove 306, the first metal gates 306a is formed at first crystal area under control I, described first metal gates 306a is the metal gates of PMOS transistor 50, concrete processing step is: on dielectric layer 303, form metal level, and described metal level fills full first groove 306; Metal level described in cmp, with dielectric layer 303 for stop-layer, forms the first metal gates 306a at first crystal area under control I.
The material of described first metal gates 306a is one in aluminium, copper, nickel, chromium, titanium, titanium tungsten, tantalum and nickel platinum or its combination.
In other embodiments of the invention, fill metal in the first groove 306 before, bottom and the sidewall of described first groove 306 are formed with workfunction layers, the material of described workfunction layers be Ti, Ta, TiN, TaN, TiAl, TaC, TaSiN wherein one or more.Described workfunction layers can also as diffusion impervious layer.
In the lump with reference to figure 9 and Figure 10, the alternative gate 305 of transistor seconds district II described in second dry etching, form the second groove 307, concrete technology step is: the mask layer (not shown) forming alternative gate 305 surface covering described dielectric layer 303, first metal gates 306a and transistor seconds district II, graphical described mask layer, exposes alternative gate 305 surface of transistor seconds district II; Adopt the alternative gate 305 of the second dry etching transistor seconds district II, form the second groove 307, adopt the method for wet etching, clean described second groove 307; Remove described mask layer.
Described second dry etching is plasma etching, and the gas that plasma etching adopts is hydrogen bromide (HBr) gas, and the second dry etching can not adopt containing other of chloride ion, prevents the corrosion to the first metal gates 306a in etching process.
During the alternative gate 305 of the second dry etching transistor seconds district II, be divided into main etching and over etching stage, because the sidewall of the second groove 307 side formed is the first metal gates 306a, the over etching stage need not consider the impact of dry etching on the first metal gates 306a, compare and the first dry etching, the amount of over etching is larger, the residual of polysilicon can not be formed in the second groove 307, without the need to adopting tetramethyl ammonium hydroxide solution (TMAH) wet-cleaned second groove 307, save processing step, cost-saving.
In the lump with reference to Figure 10 and Figure 11, full metal is filled in the second groove 307, the second metal gates 307a is formed at transistor seconds district II, described second metal gates 307a is the metal gates of nmos pass transistor 30, concrete processing step is: on dielectric layer 303, form metal level, and described metal level fills full second groove 307; Metal level described in cmp, with dielectric layer 303 for stop-layer, forms the second metal gates 307a at transistor seconds district II.
The material of described second metal gates 307a is one in aluminium, copper, nickel, chromium, titanium, titanium tungsten, tantalum and nickel platinum or its combination, specifically selects different workfunction metals according to technological requirement.
In other embodiments of the invention, fill metal in the first groove 307 before, bottom and the sidewall of described first groove 307 are formed with workfunction layers, the material of described workfunction layers be Ti, Ta, TiN, TaN, TiAl, TaC, TaSiN wherein one or more.Described workfunction layers can also as diffusion impervious layer.
To sum up, the formation method of the metal gates that the embodiment of the present invention provides, the alternative gate in the first dry etching first crystal area under control, after forming the first groove, wet-cleaned first groove, can remove alternative gate material remaining in the first groove, follow-uply forms the first metal gates at the first groove, improve the work function of the first metal gates, improve the stability of device;
Further, the alternative gate formed on the semiconductor substrate is the polysilicon of doping or unformed silicon, the speed of wet etching can be reduced after polysilicon or unformed silicon doping, when first groove in wet-cleaned first crystal area under control, the etch amount etching the molten alternative gate to transistor seconds district is ignored, the alternative gate width in transistor seconds district can not be reduced, ensure that the metal gates width that follow-up transistor seconds district is formed can not reduce, meet the requirement of technique, improve the stability of device;
Etching solution adopts tetramethyl ammonium hydroxide solution (TMAH), tetramethyl ammonium hydroxide solution (TMAH) is not containing metal ion, do not have the residual of metal ion after etching and pollute, can not cause damage to semiconductor device, and there is very high etching selection ratio.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; the Method and Technology content of above-mentioned announcement can be utilized to make possible variation and amendment to technical solution of the present invention; therefore; every content not departing from technical solution of the present invention; the any simple modification done above embodiment according to technical spirit of the present invention, equivalent variations and modification, all belong to the protection range of technical solution of the present invention.
Claims (13)
1. a formation method for metal gate, is characterized in that, comprising:
There is provided Semiconductor substrate, described Semiconductor substrate comprises the first transistor district and transistor seconds district;
Form the alternative gate of doping on the semiconductor substrate, described alternative gate is positioned at described first crystal area under control and transistor seconds district simultaneously;
The alternative gate in first crystal area under control described in first dry etching, forms the first groove, remains polysilicon in described first groove, and the alternative gate in described first groove and transistor seconds district has interface, the first groove described in wet-cleaned;
In the first groove, fill full metal, form the first metal gates;
The alternative gate in transistor seconds district described in second dry etching, forms the second groove, and forms the second metal gates in the second groove.
2. the formation method of metal gate as claimed in claim 1, is characterized in that, the solution that described wet-cleaned adopts is tetramethyl ammonium hydroxide solution.
3. the formation method of metal gate as claimed in claim 2, it is characterized in that, the concentration range of described tetramethyl ammonium hydroxide solution is 1% ~ 10%.
4. the formation method of metal gate as claimed in claim 1, it is characterized in that, the time of described wet-cleaned is 5 ~ 10 seconds.
5. the formation method of metal gate as claimed in claim 1, it is characterized in that, described Doped ions is boron ion, phosphonium ion, arsenic ion, carbon ion or Nitrogen ion.
6. the formation method of metal gate as claimed in claim 1, it is characterized in that, described alternative gate material is polysilicon or unformed silicon.
7. the formation method of metal gate as claimed in claim 1, is characterized in that, the gas that described first dry etching adopts is hydrogen bromide and chlorine.
8. the formation method of metal gate as claimed in claim 1, is characterized in that, the gas that described second dry etching adopts is hydrogen bromide.
9. the formation method of metal gate as claimed in claim 1, is characterized in that, be also formed with gate dielectric layer between described alternative gate and Semiconductor substrate.
10. the formation method of metal gate as claimed in claim 1, is characterized in that, described Semiconductor substrate is also formed with isolation structure.
The formation method of 11. metal gates as claimed in claim 1, is characterized in that, described Semiconductor substrate is also formed with dielectric layer, and described dielectric layer surface is with to be formed with isolation structure concordant with alternative gate surface.
The formation method of 12. metal gates as claimed in claim 1, it is characterized in that, described first crystal area under control is PMOS transistor district, and described transistor seconds district is nmos pass transistor district.
The formation method of 13. metal gates as claimed in claim 1, it is characterized in that, described first crystal area under control is nmos pass transistor district, and described transistor seconds district is PMOS transistor district.
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