Nothing Special   »   [go: up one dir, main page]

CN103098207A - 具有热管理的堆叠半导体芯片设备 - Google Patents

具有热管理的堆叠半导体芯片设备 Download PDF

Info

Publication number
CN103098207A
CN103098207A CN2011800435900A CN201180043590A CN103098207A CN 103098207 A CN103098207 A CN 103098207A CN 2011800435900 A CN2011800435900 A CN 2011800435900A CN 201180043590 A CN201180043590 A CN 201180043590A CN 103098207 A CN103098207 A CN 103098207A
Authority
CN
China
Prior art keywords
semiconductor chip
circuit board
thermal management
aperture
management device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN2011800435900A
Other languages
English (en)
Inventor
贾迈尔·里法伊-艾哈迈德
布莱恩·布莱克
迈克尔·Z·苏
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ATI Technologies ULC
Advanced Micro Devices Inc
Original Assignee
ATI Technologies ULC
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ATI Technologies ULC, Advanced Micro Devices Inc filed Critical ATI Technologies ULC
Publication of CN103098207A publication Critical patent/CN103098207A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
    • H01L25/0652—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/40—Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs
    • H01L23/4006—Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs with bolts or screws
    • H01L2023/4037—Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs with bolts or screws characterised by thermal path or place of attachment of heatsink
    • H01L2023/4062—Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs with bolts or screws characterised by thermal path or place of attachment of heatsink heatsink to or through board or cabinet
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1401—Structure
    • H01L2224/1403—Bump connectors having different sizes, e.g. different diameters, heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1418—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/14181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/1701—Structure
    • H01L2224/1703—Bump connectors having different sizes, e.g. different diameters, heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81192—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92222—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92225—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0652—Bump or bump-like direct electrical connections from substrate to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06572—Auxiliary carrier between devices, the carrier having an electrical connection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06589—Thermal management, e.g. cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/15321—Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
    • H05K1/0203—Cooling of mounted components
    • H05K1/0204—Cooling of mounted components using means for thermal conduction connection in the thickness direction of the substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09072—Hole or recess under component or special relationship between hole and component
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227—Other objects, e.g. metallic pieces
    • H05K2201/10378—Interposers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227—Other objects, e.g. metallic pieces
    • H05K2201/10416—Metallic blocks or heatsinks completely inserted in a PCB
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431—Details of mounted components
    • H05K2201/10507—Involving several components
    • H05K2201/10515—Stacked components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431—Details of mounted components
    • H05K2201/1056—Metal over component, i.e. metal plate over component mounted on or embedded in PCB

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

提供一种包括将热管理设备（75）与半导体芯片设备（10）的第一半导体芯片（35）热接触放置的制造方法。所述半导体芯片设备包括耦接到所述第一半导体芯片的第一基板（60）。所述第一基板具有第一孔径（70）。所述第一半导体芯片和所述热管理设备中至少一个至少部分位于所述第一孔径中。

Description

具有热管理的堆叠半导体芯片设备
发明背景
1.技术领域
本发明一般涉及半导体加工，并且更具体涉及堆叠半导体芯片的热管理结构及其组装方法。
2.相关领域描述
堆叠半导体芯片设备向科学家和工程师提出大量设计和整合挑战。常见问题包括在堆叠半导体芯片之间和在个别芯片和某一类型的电路板之间提供适当的电接口，所述电路板例如半导体芯片安装到的母板或半导体芯片封装基板。与堆叠半导体芯片相关的另一关键设计问题是热管理。大多数电设备由于电阻损耗而散热，且半导体芯片和装载半导体芯片的电路板都不例外。仍对与堆叠半导体芯片相关的另一技术挑战进行测试。
将裸半导体薄片转变成芯片集，然后将所述芯片安装在封装上或其它板上涉及大量个别步骤。因为半导体芯片的加工和安装通常以线性方式进行，即，各个步骤通常按特定顺序执行，所以最好能够在流程中尽早识别瑕疵部分。这样，可识别瑕疵部分，使得它们不经受不必要的另外处理。在处理阶段尽早识别瑕疵部分的经济刺激在堆叠半导体芯片设备的设计和制造中充分展现。这是从制造堆叠半导体芯片设备的特定工艺流程包括许多涉及将多个单一半导体芯片连续安装到电路板的制造步骤的事实中得出的。例如，如果安装到载台基板的第一半导体芯片在上面堆叠了几个其它半导体芯片后才被认出有瑕疵，那么所有与后来安装的芯片有关的材料加工步骤和材料可能都会浪费。
堆叠结构中半导体芯片的热管理在一个或多个半导体芯片的所需电测试期间仍然是技术挑战。堆叠结构中给定半导体芯片，不管是特定堆叠中第一个、中间的还是最后的半导体芯片，可能散热使得需要进行有效热管理来防止堆叠中的一个或所有半导体芯片热散逸，或使得可能以接近或真实操作功率级和频率来电测试堆叠中的一个或多个半导体芯片。
本发明旨在克服或减小一个或多个前述劣势的效应。
发明概述
根据本发明的实施方案的一个方面，提供一种包括将第一半导体芯片耦接到第一基板的制造方法。第一基板包括第一孔径。热管理设备通过第一孔径与第一半导体芯片热接触放置。
根据本发明的实施方案的另一方面，提供一种包括将热管理设备与半导体芯片设备的第一半导体芯片热接触放置的制造方法。半导体芯片设备包括耦接到第一半导体芯片的第一基板。第一基板具有第一孔径。热接触是通过第一孔径。
根据本发明的实施方案的另一方面，提供一种包括半导体芯片设备的装置，所述半导体芯片设备具有耦接到第一基板的第一半导体芯片。第一基板包括第一孔径。热管理设备通过第一孔径与第一半导体芯片热接触放置。
附图简述
在阅读以下详细描述且参照附图后，本发明的前述优点和另外的优点将会变得显而易见，在附图中：
图1是包括连接到插入器对面的半导体芯片的半导体芯片设备的示例性实施方案的剖视图；
图2是以更大放大倍率示出的图1的部分；
图3类似于图1，但是是包括连接到插入器对面的半导体芯片且具有替代热管理设备的半导体芯片设备的另一示例性实施方案的剖视图；
图4是从安装有热管理设备的电路板分解的示例性半导体芯片设备的剖视图；
图5是示例性半导体芯片设备在装配初始阶段的剖视图；
图6是类似于图5的剖视图，但是描绘了另外的装配；
图7是类似于图6的剖视图，描绘了示例性热管理设备附接到半导体芯片设备；
图8是描绘将示例性半导体芯片设备安装到示例性电路板上的剖视图；
图9是包括连接到插入器对面的半导体芯片的半导体芯片设备的替代示例性实施方案的剖视图；和
图10是图9描绘的插入器的示图。
具体实施方式
公开了各种堆叠半导体芯片结构。所公开的实施方案将基板或电路板与孔径合并来容纳半导体芯片和/或热管理设备中的一个的至少部分。热管理设备可操作以从芯片堆叠中最低的半导体芯片散热。孔径减小堆叠的形状因数而同时仍然提供热管理。现将描述另外的细节。
在下文所描述的附图中，在相同元件出现在多于一个附图中的情况下，通常重复参考数字。现参看附图，并且具体参看图1，示出半导体芯片设备10的示例性实施方案的剖视图，半导体芯片设备10包括连接到插入器20的侧面17的半导体芯片15和连接到插入器20的对面37的多个半导体芯片25、30和35。半导体芯片设备10的示例性结构和本文公开的替代物和本文公开的相关半导体芯片15、25、30和35并不依赖于半导体芯片或插入器的特定电子功能或特定类型。因此，半导体芯片15、25、30和35可以是电子产品中使用的无数种不同类型的电路设备中的任何设备，所述电子产品例如微处理器、图形处理器、结合微处理器/图形处理器、专用集成电路、存储设备、例如激光的有源光学器件、无源光学器件等，且半导体芯片15、25、30和35可以是单核或多核或甚至是与另外的芯片横向堆叠。另外，半导体芯片15、25、30和35中任一个或全部可被配置成具有或不具有一些逻辑电路的插入器，且插入器20可以是半导体芯片。因此，术语“芯片”包括插入器，且反之亦然。半导体芯片15、25、30和35和插入器20可能由例如硅或锗的散装半导体或例如绝缘体上硅材料的绝缘体上半导体材料或其它芯片或甚至绝缘材料构成。如果构建为专用插入器，那么插入器20可能由适于用于堆叠半导体芯片结构中的各种材料组成。例如，一些理想的属性包括相对接近半导体芯片15、25、30和35的CTE的热膨胀系数、易制性和热导率。例如，示例性材料包括硅、锗、蓝宝石、金刚石、聚合物基体中的碳纳米管等。
半导体芯片15可通过多个互连结构45电连接到插入器20。互连结构45可以是导电柱、焊点或其它类型的互连件。半导体芯片25可类似地通过多个互连结构50连接到插入器20，互连结构50可以是导电柱、焊点或其它类型的互连件。
虚线椭圆55外接插入器20、半导体芯片25、30和35和其它结构的部分。虚线椭圆55外接的部分将在图2中以更大放大倍率示出。然而，在参看图2之前，现将描述图1的另外的细节。插入器20可安装到基板或电路板60，且通过多个互连结构65电连接到基板或电路板60。互连结构65可以是导电柱、焊点或其它类型的互连件。本文公开的半导体芯片设备10的示例性结构不依赖于特定电子电路板功能。因此，电路板60可以是半导体芯片封装基板、母板、电路板或几乎任何其它类型的印刷电路板。虽然单片结构可用于电路板60，但是更典型的配置将使用堆积设计。在这方面，电路板60可由中央核心组成，所述中央核心上方形成一个或多个堆积层且下方形成另外一个或多个堆积层。核心本身可由一个或多个层堆叠形成。如果实施成半导体芯片封装基板，那么电路板60中层的数目可从四到十六不等或更多，但是也可使用少于四个层。也可使用所谓的“无核”设计。电路板60的层可由绝缘材料组成，例如各种已知的穿插金属互连件的环氧树脂。可使用堆积以外的多层配置。可选地，电路板20可由已知陶瓷或适于封装基板或其它印刷电路板的其它材料组成。电路板60具有许多导线和孔和其它结构（不可见）来在半导体芯片15、25、30和35之间和插入器20和例如另一电路板的另一设备之间提供电源、接地和信号传输。
虽然最好能够将例如半导体芯片25、30和35的一个或多个半导体芯片安装到插入器20的侧面37，但是所述结构必定增大半导体芯片设备10的总高度。所述高度增大在一些其它电子设备中半导体芯片设备10可用的空间有限的情况下可体现设计的复杂性。为了补偿与具有连接到插入器20的侧面35和40的半导体芯片相关的潜在高度增大，电路板60可能具有孔径70，半导体芯片25、30和35中的一个或多个可伸入孔径70。孔径70有利地完全穿过电路板60的厚度，来使可选热管理设备75能够至少与半导体芯片30热接触放置。可改变半导体芯片25、30和35和热管理设备75相对于孔径70的位置，来向半导体芯片设备10提供某一理想高度。例如，半导体芯片25、30和35中至少一个可部分或完全位于孔径70中，和/或可类似设置热管理设备75的部分。在任一情况下，热管理设备75通过孔径70与半导体芯片35热接触。
热管理设备75可采用无数种配置，例如，如示出的热翅片散热器布置或几乎任何其它类型的传热设备设计。若需要，热管理设备75可包括均热板和/或固态热电冷却器。可使用适用于传热设备的各种类型的材料，例如，铜、镍、铝、钢、它们的组合等。例如金刚石或蓝宝石的更特殊的材料也可用于极端热环境。
可选散热器80可安装在半导体芯片15上，来向半导体芯片设备10的上游提供热管理。散热器80可采用无数种配置，例如，如示出的翅片设计、更传统的半导体芯片封装盖、以上两种配置的组合或几乎任何其它类型的热输送设备。此外，示例性材料包括铜、镍、铝、钢、它们的组合等。例如金刚石或蓝宝石的更特殊的材料也可用于极端热环境。
半导体芯片设备10可安装到各种不同类型的电子结构。在该示意性实施方案中，半导体芯片设备10安装到电路板85，且通过多个将电路板60连接到电路板85的互连结构90连接到电路板85，所述电路板85可以是电路板、母板或几乎任何类型的电路板。在所述示意性实施方案中，互连结构90可以是一些锡球。然而，技术人员将理解到也可使用其它类型的互连结构，例如，针栅阵列、焊盘网格阵列或其它互连结构。在所述示意性实施方案中，至少与半导体芯片35热接触的热管理设备75的厚度可足以要求伸入电路板85或穿过电路板85。为了将热管理设备75容纳在所述电路板85中，可提供适当孔径95来容纳热管理设备75。如果热管理设备75沿z轴具有足够尺寸，那么在x-y平面中有空气或其它气流的情况下可实现对流冷却。
为了促进热管理设备75和至少半导体芯片35之间的热接触，热界面材料100可位于孔径70中，且与热管理设备75和至少半导体芯片35热接触。若需要，热界面材料100可足够广泛来根据需要完全填充孔径70。热界面材料100可由适于热管理的各种不同类型的热界面材料组成，例如，硅橡胶、硅润滑脂、丙烯酸类聚合物等。甚至可使用例如铟、镓、各种焊料等的金属材料。当然，如果使用金属材料，那么半导体芯片35可能必须具有适当的润湿膜或甚至堆叠。所述堆叠可包括形成在半导体芯片35上的铝膜、形成在铝膜上的钛膜、形成在钛膜上的镍钒膜和形成在镍钒膜上的金膜。铝膜提供与硅的有利的附着。钛膜提供阻挡层，来防止金和铟迁入半导体芯片35，并促进与镍钒膜的附着，且镍钒膜提供与金的理想附着和阻障来阻止扩散到钛层中。金膜为铟提供理想的润湿表面。
现在请参看图2，如上所述图2是以更大放大倍率示出的虚线椭圆55外接的图1的部分。这里，可看见插入器20、半导体芯片25、30和35、电路板60和热界面材料100的小部分。另外，也可看见热管理设备75的小部分。插入器20可具有多个内部布线结构，例如，黑线105示意性地表示的布线结构。半导体芯片25、30和35可类似地具有分别由黑线110、115和120示意性地表示的多个内部布线结构。技术人员将理解到布线结构105、110、115和120可以是单线线路或由导电孔互连的多个导线层或按要求地其它类型的结构。插入器20可如上文所述通过多个互连结构50电连接到半导体芯片25。互连结构50可以是微焊点、导电柱等。互连结构50可电连接到插入器20和半导体芯片25的各自的导体结构或焊垫125和130。半导体芯片25和30可被导体结构135电连接，且半导体芯片30和35可被导体结构140电连接。导体结构135和140可以是微焊点、导电柱等。导体结构135可电连接到半导体芯片25和30的各自的导体结构或焊垫145和146，且导体结构可电连接到半导体芯片30和35的各自的导体结构或焊垫147和148。
本文公开为尽可能由焊料组成的任何导体结构可由各种类型的焊料组成，例如，无铅或含铅焊料。适当的无铅焊料的例子包括锡-银（约97.3%的Sn、2.7%的Ag）、锡-铜（约99%的Sn、1%的Cu）、锡-银-铜（约96.5%的Sn、3%的Ag、0.5%的Cu）等。含铅焊料的例子包括共晶比例或接近共晶比例的锡铅焊料。
各种焊垫125、130、145、146、147和148或上文所述的导电柱可由铜、铝、银、金、铂、钛、难熔金属、难熔金属化合物、它们的合金等制成。若需要，那么焊垫125、130、145、146、147和148可由下部金属结构构成，所述下部金属结构提供阻障功能来阻止焊料浸渍。例如，多个金属层的层压例如钛层，然后是镍-钒层，然后是铜层。在另一个实施方案中，钛层可被铜层覆盖，然后是顶部镍涂层。然而，技术人员将理解到各种导电材料可用于导体。可使用各种已知技术来涂覆金属材料，例如，电镀、物理气相沉积、化学气相沉积等。
如上所述，热界面材料100可如图2中描绘部分地与孔径170同延或甚至完全同延。的确，所提供的热界面材料100的量使得半导体芯片25、30和35中所有半导体芯片都与热界面材料100接触。
现在可参看图3来理解半导体芯片设备10＇的另一示例性实施方案，图3是类似于图1的剖视图。这里，半导体芯片设备10＇可实质与半导体芯片设备10类似地配置，除了几处显著的例外。因此，半导体芯片15、25、30和35可连接到插入器20的对面。散热器75＇可至少与半导体芯片35热接触放置，且芯片25、30和35可部分或完全位于电路板60中孔径70中。然而，在所述示意性实施方案中，热管理设备75＇比图1中描绘的热管理设备75高度低。因此，不需要提供具有孔径的电路板85＇来容纳热管理设备75＇。只需要提供足够的间隙Z1来容纳替代性热管理设备75＇。
在前述示意性实施方案中，热管理设备75或75＇主要由热界面材料100的固有粘性固定到半导体芯片设备10。然而，技术人员将理解到可使用各种机制来相对于半导体芯片设备的任何公开的实施方案的半导体芯片设置热管理设备。在这方面，现在参看图2，其是描绘从电路板85〞的替代示例性实施方案分解的半导体芯片设备10的剖视图。这里，热管理设备75〞可固定到电路板85〞，且通过一个或多个支架150和155向下延伸穿过其中的孔径95。支架150和155可通过任何无数已知紧固技术固定到电路板85〞，例如，螺丝、焊料、粘合剂等。热管理设备75〞可通过所描绘的螺丝160和165或通过粘合剂、夹子、甚至焊料或任何各种已知紧固技术来固定到支架150和155。因此，热管理设备75〞可首先固定到电路板85〞，然后半导体芯片设备10可安装到电路板85〞，使得在热界面材料100和半导体芯片设备10的至少半导体芯片35之间建立热接触。此后，必要时可执行适当的回流焊接工艺来建立与互连结构90和电路板85〞相关的冶金结合。
现可通过参看图5、6和7且首先参看图5来理解装配图1和2描绘的半导体芯片设备10的示例性工艺流程。图5是半导体芯片设备10在安装图1和2描绘的半导体芯片25、30和35之前的剖视图。这里，如果半导体芯片15被大批生产为半导体薄片或其它工件的部分，那么半导体芯片15可首先是单一的，然后被安装到插入器20并通过互连结构45电连接到插入器20。插入器20可类似地大批生产且在安装半导体芯片15之前或之后是单一的。在任一情况下，互连结构45可取决于它们的成分而必要时经受焊料回流焊接工艺。另外，在将插入器20安装到电路板60之前或在互连结构65在例如两个焊接凸点或柱和凸点等的两个结构之间构成活接头的情况下，可制造互连结构65并将互连结构65连接到插入器20，然后互连结构65可分别在插入器20和电路板60上它们各自壳中形成，随后以安装/回流焊接工艺结合。在任一情况下，被设计来与图1和2中描绘的半导体芯片25电连接和结合的互连结构50这时或若需要就在下一阶段可位于插入器20上。
可用各种方式在电路板60中建立孔径70。在一个示意性实施方案中，电路板60可整体形成，随后可执行适当材料去除过程来建立孔径。例如，这可包括适当蚀刻工艺、激光烧蚀或一些其它材料去除过程。可选地，可用连续堆积工艺来形成电路板60，其中孔径70被简单地图案化，因此作为堆积工艺的部分而形成。另外，在这个阶段，互连结构90可附着到电路板60，或者，例如，所述结构可实际位于电路板85上且随后连接到电路板60。此外，建立互连结构90的实际过程将取决于它们的成分，在互连结构90包括通过匹配例如凸点的两个焊接结构形成的焊结点的情况下也是这样。
在这个阶段，半导体芯片15和插入器20都与电路板60电接触。因此，由芯片15、插入器20和电路板60组成的整个半导体芯片设备可经受电测试，来证实这三个主要元件的完整性。这是有利的，因为在这个阶段可检测到这些主要元件中任何元件的故障，而不需要经受与在安装图1和2描绘的所述半导体芯片25、30和35以后执行所述测试相关的时间、费用和可能的材料成本。
如图6示出，半导体芯片25、30和35可通过建立各自的互连结构（图2示出的135和140）来安装到插入器20。例如，这可能需要适当的回流焊接工艺。在半导体芯片25、30和35处于适当位置的情况下，半导体芯片设备10可再次经受电测试来不仅证实半导体芯片25、30和35的功能也证实整个半导体芯片设备10的各种组合电功能。
接下来，如图7示出，可向热管理设备75提供一些热界面材料100，然后热管理设备75与半导体芯片设备10的至少半导体芯片35接触。应注意，孔径70使得可容易地移动半导体芯片25、30和35来在插入器20安装到电路板60之后与插入器20啮合。可选地，部分或全部的热界面材料100可按需要涂覆到半导体芯片35和其它半导体芯片30和25，此后热管理设备75可与所述半导体芯片接触来建立必要的热接触。
接下来，如图8所描绘，包括热管理设备75的半导体芯片设备10可位于电路板85上，使得热管理设备75至少部分或可能延伸穿过孔径95，且如果需要就执行回流来通过互连结构90连接电路板85。
在上述示意性实施方案中，一个或多个半导体芯片可堆叠在插入器的下面，并向下延伸到电路板的单个孔径中或穿过所述单个孔径。然而，技术人员将理解到其它结构也是可能的。在这方面，现参看图9，其是类似于图1的剖视图，但是是半导体芯片设备10〞的替代示例性实施方案，半导体芯片设备10〞分享其它示意性实施方案的许多特点，例如，安装到插入器20的半导体芯片15。这里，然而，半导体芯片的多个堆叠170和175可安装到插入器20，且向下延伸穿过或完全穿过电路板190中各自的孔径180和185，在其中提供多个孔径180和185的条件下，电路板190可类似于图1和2描绘的电路板60而配置。为了提供热管理，热管理设备75可与位于孔径180和185中的各自的热界面材料部分200和205热接触。可选地，多个热管理设备75可按需要与堆叠170和175热接触放置，其中堆叠170和175中每一个堆叠一个热管理设备75。此外，电路板85可具有孔径95来容纳热管理设备75。当然，图3中描绘的热管理设备75＇也可用于所述示意性实施方案中。技术人员将理解到，孔径180和185的数目和空间定位具有设计自由裁量权。
技术人员将理解到，电路板中的一个或多个孔径的规定将带来导体路由的挑战。例如，如图10示出，图10是图9描绘的电路板195的示图，例如导线和导电孔的各种电布线结构将必须在孔径180和185周围路由。应注意，示出了被设计来在图9描绘的插入器20和图10描绘的电路板195之间建立电互连的互连结构中的几个互连结构，且所述几个互连结构被标注为210、215和220。另外，被设计来将电路板195电连接到图9中描绘的电路板85的互连结构中的几个互连结构是可见的且被标注为225和230。为了说明的目的，假设互连结构210是通过虚线示出的表面线路235和导电孔240来直接电连接到互连结构225。因此，互连结构210和互连结构225之间的电路径必须在孔径180周围路由，且必要时也在孔径185周围路由。对于互连结构213和互连结构230之间的虚线245示意性地表示的电路径也是这样。对于连接互连结构215和互连结构220的表面线路250也是这样。此外，图10中各种电路由结构的示意描绘的点只是为了说明提供孔径180和185来容纳图9示出的堆叠170和175将需要在所述孔径180和185周围路由任何内部或外部电布线结构。
本文公开的任何示例性实施方案可用计算机可读介质中放置的指令来实施或作为计算机数据信号来实施，所述计算机可读介质例如半导体、磁盘、光盘或其他存储介质。指令或软件可能能够合成和/或模拟本文公开的电路结构。在示例性实施方案中，例如CadenceAPD、Encore等的电子设计自动化方案可用以合成所公开的电路结构。所生成的代码可用以制造所公开的电路结构。
虽然本发明可能具有各种修改和替代形式，但是具体的实施方案已通过附图中的例子被示出并在本文中详细描述。然而，应理解，本发明并不旨在限于所公开的特定形式。相反，本发明将涵盖落入本发明的精神和范围内的所有修改、等同物和替代物，且本发明的精神和范围由以上权利要求限定。

Claims (25)

1.一种制造方法，其包括：
将第一半导体芯片（35）耦接到第一基板（60），所述第一基板包括第一孔径（70）；和
通过所述第一孔径将热管理设备（75、75＇、75〞）与第一半导体芯片热接触放置。
2.如权利要求1所述的方法，其中所述热管理设备包括散热器、均热板或热电冷却器中的一个。
3.如权利要求1所述的方法，其中所述第一半导体芯片和所述热管理设备中的至少一个至少部分位于所述第一孔径中。
4.如权利要求1所述的方法，其包括将多个半导体芯片（25、30、35）耦接到所述第一基板。
5.如权利要求4所述的方法，其中所述多个半导体芯片中的一个包括插入器（20）。
6.如权利要求1所述的方法，其中所述第一基板包括电路板，所述方法包括将所述第一电路板耦接到第二电路板（85）。
7.如权利要求6所述的方法，其中所述第二电路板包括第二孔径（95），且所述热管理设备至少部分位于所述第二孔径中。
8.如权利要求7所述的方法，其中将所述热管理设备耦接到所述第二电路板。
9.一种制造方法，其包括：
将热管理设备与半导体芯片设备（10）的第一半导体芯片热接触放置；且
其中所述半导体芯片设备包括耦接到所述第一半导体芯片（60）的第一基板，所述第一基板包括第一孔径（70），且所述热接触是通过所述第一孔径。
10.如权利要求9所述的方法，其中所述热管理设备包括散热器、均热板或热电冷却器中的一个。
11.如权利要求9所述的方法，其中所述第一半导体芯片和所述热管理设备中的至少一个至少部分位于所述第一孔径中。
12.如权利要求9所述的方法，其中所述半导体芯片设备包括耦接到所述第一基板的多个半导体芯片（25、30、35）。
13.如权利要求12所述的方法，其中所述多个半导体芯片中的一个包括插入器（20）。
14.如权利要求9所述的方法，其中所述第一基板包括电路板，所述方法包括将所述第一电路板耦接到第二电路板（85）。
15.如权利要求14所述的方法，其中所述第二电路板包括第二孔径（95），且所述热管理设备至少部分位于所述第二孔径中。
16.如权利要求15所述的方法，其中将所述热管理设备（75〞）耦接到所述第二电路板。
17.一种装置，其包括：
半导体芯片设备（10），其包括耦接到第一基板的第一半导体芯片（35），所述第一基板包括第一孔径（70）；和
热管理设备（70），其通过所述第一孔径与所述第一半导体芯片热接触。
18.如权利要求17所述的装置，其中所述热管理设备包括散热器、均热板或热电冷却器中的一个。
19.如权利要求17所述的装置，其中所述第一半导体芯片和所述热管理设备中的至少一个至少部分位于所述第一孔径中。
20.如权利要求17所述的装置，其中所述第一半导体芯片和所述热管理设备都至少部分位于所述第一孔径中。
21.如权利要求17所述的装置，其包括耦接到所述第一基板的多个半导体芯片。
22.如权利要求21所述的装置，其中多个半导体芯片中的一个包括插入器（20）。
23.如权利要求17所述的装置，其中所述第一基板包括耦接到第二电路板的电路板（85）。
24.如权利要求23所述的装置，其中所述第二电路板包括第二孔径（95），且所述热管理设备至少部分位于所述第二孔径中。
25.如权利要求24所述的装置，其中将所述热管理设备耦接到所述第二电路板。
CN2011800435900A 2010-09-24 2011-09-21 具有热管理的堆叠半导体芯片设备 Pending CN103098207A (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/889,590 2010-09-24
US12/889,590 US8472190B2 (en) 2010-09-24 2010-09-24 Stacked semiconductor chip device with thermal management
PCT/US2011/052466 WO2012040271A1 (en) 2010-09-24 2011-09-21 Stacked semiconductor chip device with thermal management

Publications (1)

Publication Number Publication Date
CN103098207A true CN103098207A (zh) 2013-05-08

Family

ID=44741715

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2011800435900A Pending CN103098207A (zh) 2010-09-24 2011-09-21 具有热管理的堆叠半导体芯片设备

Country Status (6)

Country Link
US (1) US8472190B2 (zh)
EP (1) EP2619795A1 (zh)
JP (1) JP2013538012A (zh)
KR (1) KR20130102052A (zh)
CN (1) CN103098207A (zh)
WO (1) WO2012040271A1 (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109075158A (zh) * 2016-04-12 2018-12-21 Mbda法国公司 设有多个互连的电子功能件的电子系统
CN110214373A (zh) * 2017-02-28 2019-09-06 华为技术有限公司 光电混合封装组件

Families Citing this family (48)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI339737B (en) 2005-04-27 2011-04-01 Aehr Test Systems Contactor assembly, cartridge, and apparatus and method for testing integrated circuit of device
US7800382B2 (en) 2007-12-19 2010-09-21 AEHR Test Ststems System for testing an integrated circuit of a device and its method of use
US8030957B2 (en) 2009-03-25 2011-10-04 Aehr Test Systems System for testing an integrated circuit of a device and its method of use
CN202276549U (zh) * 2011-09-26 2012-06-13 番禺得意精密电子工业有限公司 电连接组件
JP5167516B1 (ja) * 2011-11-30 2013-03-21 株式会社フジクラ 部品内蔵基板及びその製造方法並びに部品内蔵基板実装体
US20130181359A1 (en) 2012-01-13 2013-07-18 TW Semiconductor Manufacturing Company, Ltd. Methods and Apparatus for Thinner Package on Package Structures
TWI508249B (zh) 2012-04-02 2015-11-11 矽品精密工業股份有限公司 封裝件、半導體封裝結構及其製法
US20130308274A1 (en) * 2012-05-21 2013-11-21 Triquint Semiconductor, Inc. Thermal spreader having graduated thermal expansion parameters
US9209106B2 (en) * 2012-06-21 2015-12-08 Ati Technologies Ulc Thermal management circuit board for stacked semiconductor chip device
US9006908B2 (en) * 2012-08-01 2015-04-14 Marvell Israel (M.I.S.L) Ltd. Integrated circuit interposer and method of manufacturing the same
US9196575B1 (en) * 2013-02-04 2015-11-24 Altera Corporation Integrated circuit package with cavity in substrate
US9318464B2 (en) * 2013-05-21 2016-04-19 Advanced Micro Devices, Inc. Variable temperature solders for multi-chip module packaging and repackaging
US9653443B2 (en) * 2014-02-14 2017-05-16 Taiwan Semiconductor Manufacturing Company, Ltd. Thermal performance structure for semiconductor packages and method of forming same
US9269700B2 (en) * 2014-03-31 2016-02-23 Micron Technology, Inc. Stacked semiconductor die assemblies with improved thermal performance and associated systems and methods
US9391029B2 (en) * 2014-06-12 2016-07-12 Kabushiki Kaisha Toshiba Electronic device
US10553557B2 (en) 2014-11-05 2020-02-04 Infineon Technologies Austria Ag Electronic component, system and method
US10064287B2 (en) * 2014-11-05 2018-08-28 Infineon Technologies Austria Ag System and method of providing a semiconductor carrier and redistribution structure
US10192846B2 (en) 2014-11-05 2019-01-29 Infineon Technologies Austria Ag Method of inserting an electronic component into a slot in a circuit board
KR101640341B1 (ko) * 2015-02-04 2016-07-15 앰코 테크놀로지 코리아 주식회사 반도체 패키지
US9996120B1 (en) * 2015-05-22 2018-06-12 EMC IP Holding Company LLC PCB module for increased connectivity
US9779940B2 (en) * 2015-07-01 2017-10-03 Zhuahai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd. Chip package
US9589920B2 (en) * 2015-07-01 2017-03-07 Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd. Chip package
DE102015220676A1 (de) * 2015-10-22 2017-04-27 Zf Friedrichshafen Ag Leiterplatte und Anordnung mit einer Leiterplatte
WO2017108121A1 (en) * 2015-12-23 2017-06-29 Intel IP Corporation Semiconductor die package with more than one hanging die
US10466292B2 (en) 2016-01-08 2019-11-05 Aehr Test Systems Method and system for thermal control of devices in an electronics tester
US10121766B2 (en) * 2016-06-30 2018-11-06 Micron Technology, Inc. Package-on-package semiconductor device assemblies including one or more windows and related methods and packages
CN210692526U (zh) * 2016-08-31 2020-06-05 株式会社村田制作所 电路模块
US10797039B2 (en) * 2016-12-07 2020-10-06 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming a 3D interposer system-in-package module
US10062634B2 (en) * 2016-12-21 2018-08-28 Micron Technology, Inc. Semiconductor die assembly having heat spreader that extends through underlying interposer and related technology
CN110383092B (zh) * 2017-03-03 2022-04-01 雅赫测试系统公司 电子测试器
US9899305B1 (en) * 2017-04-28 2018-02-20 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package structure
US10269678B1 (en) 2017-12-05 2019-04-23 Nxp Usa, Inc. Microelectronic components having integrated heat dissipation posts, systems including the same, and methods for the fabrication thereof
US11101145B2 (en) * 2018-08-14 2021-08-24 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device with dummy micro bumps between stacking dies to improve flowability of underfill material
US11152333B2 (en) * 2018-10-19 2021-10-19 Micron Technology, Inc. Semiconductor device packages with enhanced heat management and related systems
US10973114B2 (en) * 2018-10-29 2021-04-06 L3 Technologies, Inc. Indium-based interface structures, apparatus, and methods for forming the same
US11553616B2 (en) * 2018-12-07 2023-01-10 Delta Electronics, Inc. Module with power device
CN116634659A (zh) * 2018-12-07 2023-08-22 台达电子工业股份有限公司 电源模块
US10943880B2 (en) 2019-05-16 2021-03-09 Advanced Micro Devices, Inc. Semiconductor chip with reduced pitch conductive pillars
KR102377811B1 (ko) 2019-08-09 2022-03-22 삼성전기주식회사 전자 소자 모듈 및 그 제조 방법
CN114009153A (zh) * 2020-04-23 2022-02-01 鸿富锦精密工业(武汉)有限公司 堆叠式电路板
US20210391301A1 (en) * 2020-06-10 2021-12-16 Intel Corporation High speed memory system integration
US11769752B2 (en) * 2020-07-24 2023-09-26 Micron Technology, Inc. Stacked semiconductor die assemblies with substrate heat sinks and associated systems and methods
JP7510817B2 (ja) 2020-08-25 2024-07-04 新光電気工業株式会社 半導体装置及びその製造方法
US11625079B2 (en) * 2020-12-23 2023-04-11 Quanta Computer Inc. Staggered arrangement graphite heat sink for liquid cooling cold plate
JP7447785B2 (ja) * 2020-12-25 2024-03-12 株式会社デンソー 電子装置
US20220330414A1 (en) * 2021-04-08 2022-10-13 International Business Machines Corporation Heat sinks with beyond-board fins
CN116053232A (zh) * 2022-12-20 2023-05-02 成都海光集成电路设计有限公司 一种电子封装、电子封装的制作方法及电子设备
US20240353634A1 (en) * 2023-04-20 2024-10-24 Ciena Corporation Managing relative thermal drift of carrier-mounted integrated circuits

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5567654A (en) * 1994-09-28 1996-10-22 International Business Machines Corporation Method and workpiece for connecting a thin layer to a monolithic electronic module's surface and associated module packaging
US5821762A (en) * 1994-02-28 1998-10-13 Mitsubishi Denki Kabushiki Kaisha Semiconductor device, production method therefor, method for testing semiconductor elements, test substrate for the method and method for producing the test substrate
US6501164B1 (en) * 2001-06-26 2002-12-31 Siliconware Precision Industries Co., Ltd. Multi-chip semiconductor package with heat dissipating structure
JP2004207566A (ja) * 2002-12-26 2004-07-22 Seiko Instruments Inc 半導体装置、表示装置、及び、その製造方法
US20040217485A1 (en) * 2003-05-02 2004-11-04 Advanced Semiconductor Engineering Inc. Stacked flip chip package
CN1734756A (zh) * 2004-08-11 2006-02-15 索尼株式会社 电子回路装置

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5856911A (en) * 1996-11-12 1999-01-05 National Semiconductor Corporation Attachment assembly for integrated circuits
US6060777A (en) * 1998-07-21 2000-05-09 Intel Corporation Underside heat slug for ball grid array packages
US6853070B2 (en) * 2001-02-15 2005-02-08 Broadcom Corporation Die-down ball grid array package with die-attached heat spreader and method for making the same
TW502406B (en) * 2001-08-01 2002-09-11 Siliconware Precision Industries Co Ltd Ultra-thin package having stacked die
US6580611B1 (en) * 2001-12-21 2003-06-17 Intel Corporation Dual-sided heat removal system
US6712621B2 (en) * 2002-01-23 2004-03-30 High Connection Density, Inc. Thermally enhanced interposer and method
US6861750B2 (en) * 2002-02-01 2005-03-01 Broadcom Corporation Ball grid array package with multiple interposers
US6858932B2 (en) * 2002-02-07 2005-02-22 Freescale Semiconductor, Inc. Packaged semiconductor device and method of formation
US6906415B2 (en) 2002-06-27 2005-06-14 Micron Technology, Inc. Semiconductor device assemblies and packages including multiple semiconductor devices and methods
US7122906B2 (en) 2004-01-29 2006-10-17 Micron Technology, Inc. Die-wafer package and method of fabricating same
JP2007123457A (ja) * 2005-10-27 2007-05-17 Nec Electronics Corp 半導体モジュール
US7903425B2 (en) * 2006-06-27 2011-03-08 Lenovo (Singapore) Pte. Ltd. Integrated circuit chip thermal solution
US7646093B2 (en) * 2006-12-20 2010-01-12 Intel Corporation Thermal management of dies on a secondary side of a package
US20100181594A1 (en) * 2008-03-25 2010-07-22 Lin Charles W C Semiconductor chip assembly with post/base heat spreader and cavity over post

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5821762A (en) * 1994-02-28 1998-10-13 Mitsubishi Denki Kabushiki Kaisha Semiconductor device, production method therefor, method for testing semiconductor elements, test substrate for the method and method for producing the test substrate
US5567654A (en) * 1994-09-28 1996-10-22 International Business Machines Corporation Method and workpiece for connecting a thin layer to a monolithic electronic module's surface and associated module packaging
US6501164B1 (en) * 2001-06-26 2002-12-31 Siliconware Precision Industries Co., Ltd. Multi-chip semiconductor package with heat dissipating structure
JP2004207566A (ja) * 2002-12-26 2004-07-22 Seiko Instruments Inc 半導体装置、表示装置、及び、その製造方法
US20040217485A1 (en) * 2003-05-02 2004-11-04 Advanced Semiconductor Engineering Inc. Stacked flip chip package
CN1734756A (zh) * 2004-08-11 2006-02-15 索尼株式会社 电子回路装置

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109075158A (zh) * 2016-04-12 2018-12-21 Mbda法国公司 设有多个互连的电子功能件的电子系统
CN109075158B (zh) * 2016-04-12 2023-05-23 Mbda法国公司 设有多个互连的电子功能件的电子系统
CN110214373A (zh) * 2017-02-28 2019-09-06 华为技术有限公司 光电混合封装组件

Also Published As

Publication number Publication date
WO2012040271A1 (en) 2012-03-29
US20120075807A1 (en) 2012-03-29
US8472190B2 (en) 2013-06-25
KR20130102052A (ko) 2013-09-16
JP2013538012A (ja) 2013-10-07
EP2619795A1 (en) 2013-07-31

Similar Documents

Publication Publication Date Title
CN103098207A (zh) 具有热管理的堆叠半导体芯片设备
US7714452B2 (en) Structure and method for producing multiple size interconnections
US8466543B2 (en) Three dimensional stacked package structure
US6884653B2 (en) Folded interposer
CN104064551B (zh) 一种芯片堆叠封装结构和电子设备
US5854507A (en) Multiple chip assembly
US7888185B2 (en) Semiconductor device assemblies and systems including at least one conductive pathway extending around a side of at least one semiconductor device
US6906417B2 (en) Ball grid array utilizing solder balls having a core material covered by a metal layer
CN103219299A (zh) 集成电路封装组件及其形成方法
US7786571B2 (en) Heat-conductive package structure
US8217403B1 (en) Electronic device
US7576434B2 (en) Wafer-level solder bumps
KR20140127156A (ko) 전기 시스템 및 그 코어 모듈
US20120161312A1 (en) Non-solder metal bumps to reduce package height
US20150208506A1 (en) A printed circuit board arrangement and a method for forming electrical connection at a printed circuit board
US20090200362A1 (en) Method of manufacturing a semiconductor package
US20090032946A1 (en) Integrated circuit
JPH04290258A (ja) マルチチップモジュール
US20220208624A1 (en) Semiconductor package including dual stiffener
US20210167038A1 (en) Dual in-line memory module
US8941236B2 (en) Using collapse limiter structures between elements to reduce solder bump bridging
JPH04144160A (ja) 集積回路チップのための低外形、高密度のパッケージとする装置
JPS63501995A (ja) マイクロミニチュア装置の圧接接続端子の製造方法
CN111883513A (zh) 芯片封装结构及电子设备
US20230197595A1 (en) Multi-chip high memory bandwidth configuration

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C02 Deemed withdrawal of patent application after publication (patent law 2001)
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20130508