CN103094191B - Method of reducing dielectric constant of inter-lamination dielectric layer - Google Patents
Method of reducing dielectric constant of inter-lamination dielectric layer Download PDFInfo
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- CN103094191B CN103094191B CN201110340496.3A CN201110340496A CN103094191B CN 103094191 B CN103094191 B CN 103094191B CN 201110340496 A CN201110340496 A CN 201110340496A CN 103094191 B CN103094191 B CN 103094191B
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Abstract
The invention provides a method of reducing the dielectric constant of an inter-lamination dielectric layer. The method of reducing the dielectric constant of the inter-lamination dielectric layer is applied to a back-end process of a semiconductor device and comprises that the inter-lamination dielectric layer is etched before hand, metal interconnecting wires are filled inside the inter-lamination dielectric layer to form a metal interconnecting layer of the inter-lamination dielectric layer; and holes are formed on the surface of the inter-lamination dielectric layer of the inter-lamination dielectric layer metal interconnecting layer. The method of reducing the dielectric constant of the inter-lamination dielectric layer can effectively reduce resistance-capacitance (RC) delays of an integrated circuit.
Description
Technical field
The present invention relates to semiconductor device processing technology, particularly a kind of method of dielectric layer dielectric constant between lower layer.
Background technology
At present, at the back segment (back-end-of-line of semiconductor device, BEOL) in technique, when making semiconductor integrated circuit, after semiconductor device layer is formed, need to form metal interconnecting layer on semiconductor device layer, every layer of metal interconnecting layer comprises metal interconnecting wires and interlayer dielectric layer (Inter-layer dielectric, ILD), this just needs to manufacture groove (trench) and connecting hole to above-mentioned interlayer dielectric layer, then plated metal in above-mentioned groove and connecting hole, the metal of deposition is metal interconnecting wires, generally select copper as metal interconnected wire material.Fig. 1 is the structural representation of metal interconnecting layer, and it comprises interlayer dielectric layer 101 and metal interconnecting wires 102.Interlayer dielectric layer generally adopts low-k (Low-K) insulation material layer, black diamond (the black diamond of the similar oxide (Oxide) such as containing silicon, oxygen, carbon, protium, BD) material, unadulterated silicate glass (USG), fluoride glass (FSG) etc.Wherein, the dielectric constant of FSG and USG is greater than the dielectric constant of 3, BD is 2.7 ~ 3.
Along with the development of integrated circuit, the number of plies of back segment metal interconnecting layer is more and more intensive, in order to the resistance capacitance (RC) reducing whole integrated circuit (IC) postpones, improve the electric property of device, develop Novel super-low k (ULK) inter-level dielectric layer material, be generally porous material, than above-mentioned BD, FSG, USG, there is lower dielectric constant, can be such as the silicon dioxide of porous carbon dope, be referred to as black diamond two generation (BDII).But the problem of this porous material is also obvious: one, bad mechanical strength, deposited metallic copper in groove and connecting hole after, need to carry out cmp (CMP) to metallic copper, interlayer dielectric layer can be ground to simultaneously, now, the interlayer dielectric layer with inferior mechanical intensity is easy to form distortion or crack; Two, because porous material easily absorbs, be easy to absorb chemical substance when dry etching or wet etching, change the character of material; Three, in prior art in order to prevent copper from diffusing into interlayer dielectric layer, be limited in groove and connecting hole better, generally deposition of barrier film between interlayer dielectric layer and metal interconnecting wires, and barrier film is easy to be diffused in the inter-level dielectric layer material of porous in forming process, reduce the electric property of device, as puncture voltage (VBD) etc.
Therefore, the RC how reducing integrated circuit postpones to become the problem needing in the industry to solve.
Summary of the invention
In view of this, the technical problem that the present invention solves is: the RC how reducing integrated circuit postpones.
For solving the problems of the technologies described above, technical scheme of the present invention is specifically achieved in that
The invention discloses the method for dielectric layer dielectric constant between a kind of lower layer, be applied in the last part technology of semiconductor device, the method comprises: etch interlayer dielectric layer in advance, and fills metal interconnecting wires formation within it when layer metal interconnecting layer; In the punching of the formed interlayer dielectric layer when layer metal interconnecting layer surface.
Described punching on the formed interlayer dielectric layer when layer metal interconnecting layer surface is:
Interlayer dielectric layer adopt direct self assembly DSA method form porous design;
With described porous design for mask, interlayer dielectric layer is etched, form the hole of multiple desired depth and width on interlayer dielectric layer surface.
Describedly on interlayer dielectric layer, direct self assembly is adopted to be: at interlayer dielectric layer surface coating copolymer copolymer, described copolymer forms porous design automatically.
Described copolymer is the PS-PMMA mixed by two kinds of polymers polystyrene PS and polyethylene methacrylic acid methyl esters PMMA.
With described porous design for mask, carry out in etching reaction chamber the step that interlayer dielectric layer etches, etching gas comprises octafluoroization four carbon C
4f
8, difluoromethane CH
2f
2, N
2and Ar;
Wherein, C
4f
8flow be 5 ~ 100 sccm sccm, CH
2f
2flow be 5 ~ 100sccm, N
2flow be the flow of 100 ~ 500sccm, Ar be 100 ~ 1000sccm.
Etch interlayer dielectric layer, after forming multiple hole, the method comprises the step removing copolymer further.
Described removal copolymer adopts dry etching etching gas to comprise carbon dioxide and methane.
Before interlayer dielectric layer surface coating copolymer, the method comprises further carries out back carving, to the metal interconnecting wires manifesting predetermined altitude to interlayer dielectric layer.
The diameter in described hole is not more than 20 nanometers.
Described interlayer dielectric layer comprises: carbonado BD, unadulterated silicate glass USG or fluoride glass FSG.
As seen from the above technical solutions, the present invention is in the interlayer dielectric layer surface punching when layer metal interconnecting layer, interlayer dielectric layer is made to have multiple and have the hole of certain depth, because this some holes stamps in the later stage, in the density in hole, the degree of depth and quantitatively, compared to the hole of black diamond two those porous materials of generation, all obviously much lower, the problem existing for above-mentioned said porous material would not be there is like this, but owing to being filled with air in this some holes, the dielectric constant of air is 1, the overall dielectric constant of interlayer dielectric layer is declined, thus achieve object of the present invention.
Accompanying drawing explanation
Fig. 1 is the structural representation of metal interconnecting layer.
Fig. 2 is the schematic flow sheet of the method for dielectric layer dielectric constant between embodiment of the present invention lower layer.
Fig. 2 a to Fig. 2 d is the concrete generalized section of the method for dielectric layer dielectric constant between embodiment of the present invention lower layer.
Embodiment
For making object of the present invention, technical scheme and advantage clearly understand, to develop simultaneously embodiment referring to accompanying drawing, the present invention is described in more detail.
The present invention utilizes schematic diagram to be described in detail, when describing the embodiment of the present invention in detail, for convenience of explanation, represent that the schematic diagram of structure can be disobeyed general ratio and be made partial enlargement, should in this, as limitation of the invention, in addition, in the making of reality, the three-dimensional space of length, width and the degree of depth should be comprised.
The method of dielectric layer dielectric constant between embodiment of the present invention lower layer, its schematic flow sheet as shown in Figure 2, comprises the following steps, and below in conjunction with Fig. 2 a to Fig. 2 d, is described in detail.
Step 21, refer to Fig. 2 a, the interlayer dielectric layer when layer metal interconnecting layer and metal interconnecting wires are provided;
Particularly, on the interlayer dielectric layer 101 when layer metal interconnecting layer, etching forms groove and connecting hole, plated metal copper in described groove and connecting hole, then carry out CMP to the metallic copper wherein higher than interlayer dielectric layer surface, the groove and the connecting hole that deposit metallic copper are called metal interconnecting wires 102.
Step 22, refer to Fig. 2 b, adopt direct self assembly (Directedself-assembly, DSA) method to form porous design 201 on interlayer dielectric layer 101 surface;
Particularly, at interlayer dielectric layer surface coating copolymer (copolymer).It should be noted that, copolymer only can grow on interlayer dielectric layer surface, and copper surface can not be attached to, and copolymer is made up of multiple polymers, its characteristic is exactly that this several polymer can be separated automatically on interlayer dielectric layer surface, the porous design of formation rule arrangement, those skilled in the art are referred to as DSA method.Wherein, require that the diameter in each hole is less than 20 nanometers, object be avoid follow-up when interlayer dielectric layer surface deposition material, because the diameter in hole is too large, and enter in this some holes, and if the diameter in hole too large, it will be caused to have the problems such as poor mechanical strength.
The copolymer that the embodiment of the present invention adopts is PS-PMMA, namely by two kinds of polymers polystyrene (polystyrene, and polyethylene methacrylic acid methyl esters (Poly methyl methacrylate PS), PMMA) mix, this copolymer forms porous design automatically on interlayer dielectric layer surface.The bore dia of its porous design is 18 nanometers, and has the spacing of 42 nanometers between Kong Yukong, arrangement comparison rule.
Step 23, refer to Fig. 2 c, with described porous design 201 for mask, interlayer dielectric layer is etched, form the hole 202 of multiple desired depth and width on interlayer dielectric layer surface;
Owing to being take porous design as mask, so the hole that etching interlayer dielectric layer is formed is consistent with the hole of described porous design.The step that interlayer dielectric layer etches is carried out in etching reaction chamber, certain control is carried out to etching gas and flow parameter, just can form required hole.Particularly, can adopt fluoro-gas, in the embodiment of the present invention, etching gas comprises octafluoroization four carbon (C
4f
8), difluoromethane (CH
2f
2), N
2and Ar, wherein, C
4f
8flow be 5 ~ 100 sccm (sccm), CH
2f
2flow be 5 ~ 100sccm, N
2flow be the flow of 100 ~ 500sccm, Ar be 100 ~ 1000sccm.
Further, the embodiment of the present invention also comprises step 24, refers to Fig. 2 d, removes described mask.
Wherein, the removal as the copolymer of mask can adopt wet etching or dry etching.For dry etching, can pass into the gas such as carbon dioxide and methane in etching reaction chamber, this is the method known by those skilled in the art, does not repeat them here.
The preferred embodiment of the present invention is between step 21 and 22, add back the step of carving interlayer dielectric layer.The height passing through back the interlayer dielectric layer carved is starkly lower than the height of metal interconnecting wires, interlayer dielectric layer obviously can be divided into multiple region by the metal interconnecting wires like this owing to protruding, in limited little regional extent, more be conducive to the performance of copolymer characteristic, namely can more effectively form above-mentioned porous design.
It should be noted that, the embodiment of the present invention is the characteristic that make use of copolymer, and the mask formed with copolymer, punches to interlayer dielectric layer, and other can realize the mode in the punching of interlayer dielectric layer surface, all in protection scope of the present invention.And copolymer is also not limited to the PS-PMMA in the embodiment of the present invention, it can also be the copolymer of other two kinds or the formation of two or more polymer mixed.
By method of the present invention, the K value of interlayer dielectric layer can reduce by 20% ~ 30% than original, on the basis overcoming the problem existing for porous material, achieves object of the present invention, greatly reduce the dielectric constant of interlayer dielectric layer, thus the RC reducing integrated circuit postpones.
The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, within the spirit and principles in the present invention all, any amendment made, equivalent replacement, improvement etc., all should be included within the scope of protection of the invention.
Claims (7)
1. the method for dielectric layer dielectric constant between lower layer, be applied in the last part technology of semiconductor device, it is characterized in that, the method comprises:
In advance interlayer dielectric layer is etched, and fill metal interconnecting wires formation within it when layer metal interconnecting layer;
On the formed interlayer dielectric layer of working as layer metal interconnecting layer, be that border adopts direct self assembly DSA method to form porous design with metal interconnecting wires;
With described porous design for mask, interlayer dielectric layer is etched, form the hole of multiple desired depth and width on interlayer dielectric layer surface;
Described on the formed interlayer dielectric layer of working as layer metal interconnecting layer, be that border adopts the method for direct self assembly to be with metal interconnecting wires: as layer metal interconnecting layer surface coating copolymer copolymer, make copolymer take metal interconnecting wires as border, only automatically form porous design on interlayer dielectric layer surface;
Described copolymer is the PS-PMMA mixed by two kinds of polymers polystyrene PS and polyethylene methacrylic acid methyl esters PMMA.
2. the method for claim 1, is characterized in that, with described porous design for mask, carries out in etching reaction chamber the step that interlayer dielectric layer etches, and etching gas comprises octafluoroization four carbon C
4f
8, difluoromethane CH
2f
2, N
2and Ar;
Wherein, C
4f
8flow be 5 ~ 100 sccm sccm, CH
2f
2flow be 5 ~ 100sccm, N
2flow be the flow of 100 ~ 500sccm, Ar be 100 ~ 1000sccm.
3. method as claimed in claim 2, is characterized in that, etch interlayer dielectric layer, and after forming multiple hole, the method comprises the step removing copolymer further.
4. method as claimed in claim 3, is characterized in that, described removal copolymer adopts dry etching etching gas to comprise carbon dioxide and methane.
5. the method for claim 1, is characterized in that, before interlayer dielectric layer surface coating copolymer, the method comprises further carries out back carving, to the metal interconnecting wires manifesting predetermined altitude to interlayer dielectric layer.
6. the method for claim 1, is characterized in that, the diameter in described hole is not more than 20 nanometers.
7. the method for claim 1, is characterized in that, described interlayer dielectric layer comprises: carbonado BD, unadulterated silicate glass USG or fluoride glass FSG.
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| CN201110340496.3A CN103094191B (en) | 2011-11-01 | 2011-11-01 | Method of reducing dielectric constant of inter-lamination dielectric layer |
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| CN103094191B true CN103094191B (en) | 2015-04-15 |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1649107A (en) * | 2004-01-30 | 2005-08-03 | 国际商业机器公司 | Device and methodology for reducing effective dielectric constant in semiconductor devices |
| CN101335190A (en) * | 2007-06-27 | 2008-12-31 | 国际商业机器公司 | Methods of patterning self-assembly nano-structure and forming porous dielectric |
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| US7767099B2 (en) * | 2007-01-26 | 2010-08-03 | International Business Machines Corporaiton | Sub-lithographic interconnect patterning using self-assembling polymers |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1649107A (en) * | 2004-01-30 | 2005-08-03 | 国际商业机器公司 | Device and methodology for reducing effective dielectric constant in semiconductor devices |
| CN101335190A (en) * | 2007-06-27 | 2008-12-31 | 国际商业机器公司 | Methods of patterning self-assembly nano-structure and forming porous dielectric |
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