CN103066102A - Groove type power semiconductor element for raising breakdown voltage and its manufacturing method - Google Patents
Groove type power semiconductor element for raising breakdown voltage and its manufacturing method Download PDFInfo
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Abstract
The invention provides a groove type power semiconductor element for improving breakdown voltage and a manufacturing method thereof, wherein a first groove is formed between adjacent grid grooves of the groove type power semiconductor element for improving breakdown voltage and penetrates through a body area; the bottom of the first groove is provided with a polysilicon structure, the conductivity type of the polysilicon structure is the same as that of the body region of the power semiconductor element, and the polysilicon structure is separated from the body region by a preset distance; forming a dielectric structure above the polysilicon structure and at least extending upwards to the body region; a source region is formed at the upper part of the body region; a heavily doped region in the body region; the conductive structure is electrically connected with the heavily doped region and the source region. The invention can improve the dynamic characteristic of the trench type power semiconductor element, improve the breakdown voltage and keep the reliability of the structure.
Description
Technical field
The present invention relates to a kind of groove power semiconductor element and manufacture method thereof, particularly a kind of groove power semiconductor element and manufacture method thereof that promotes breakdown voltage.
Background technology
Emphasizing under the energy-conservation trend, for the application of power semiconductor, also more and more paying attention to the performance of its conducting resistance.In general, the improvement of conducting resistance helps to reduce the conducting loss (conduction loss) of circuit operation, and still, the reduction of conducting resistance can be accompanied by the reduction of breakdown voltage (breakdown voltage) inevitably.Downgrade conducting resistance by adjustment doping content or the mode that changes built crystal layer thickness arbitrarily, all may cause harmful effect for the reliability of structure.
Therefore, seeking a kind of groove power semiconductor element that can promote breakdown voltage, guarantee simultaneously the reliability of its structure, is important problem of the art.
Summary of the invention
In view of this, main purpose of the present invention is to propose a kind of groove power semiconductor element and manufacture method thereof that promotes breakdown voltage, keeps simultaneously the reliability of its structure.
For achieving the above object, the invention provides a kind of groove power semiconductor element that promotes breakdown voltage.With regard to a preferred embodiment, this groove power semiconductor element that promotes breakdown voltage comprises a base material, at least two gate trenchs, one first dielectric layer, one first polysilicon structure, at least one first groove, one second polysilicon structure, this tagma of one first conductivity type, the source area of one second conductivity type, heavily doped region and the one source pole metal level of one first conductivity type.Wherein, gate trench is positioned at base material.The inner surface of the first dielectric layer cover gate groove.The first polysilicon structure is positioned at gate trench.The first groove is between adjacent two gate trenchs.The body district of the first conductivity type is positioned between these gate trenchs.The first groove runs through this tagma and extends to this below, tagma.The second polysilicon structure system of the first conductivity type inserts the lower part of the first groove.The second polysilicon structure is positioned at below, this tagma, and with the body interval every a preset distance.The source area of the second conductivity type is positioned at the upper part in this tagma.The second conductivity type is electrical opposite with the first conductivity type.The heavily doped region of the first conductivity type is positioned at this tagma.Source metal is electrically connected heavily doped region and source area.
In other words, the invention provides a kind of groove power semiconductor element that promotes breakdown voltage, comprise base material; At least two gate trenchs are positioned at this base material; The first dielectric layer covers the inner surface of this gate trench; The first polysilicon structure is positioned at this at least two gate trenchs; At least one first groove is between these two gate trenchs; This tagma of the first conductivity type is positioned between these two gate trenchs at least, and this first groove runs through this this tagma and extends to this this below, tagma; The second polysilicon structure of the first conductivity type is inserted the lower part of this first groove, and this second polysilicon structure is positioned at this this below, tagma, and with this body interval every preset distance; The source area of the second conductivity type is positioned at the upper part in this this tagma, and this second conductivity type is electrical opposite with this first conductivity type; The heavily doped region of the first conductivity type is positioned at this this tagma; And source metal, be electrically connected this heavily doped region and this source area.
The present invention also provides the manufacture method of this groove power semiconductor element.With regard to a preferred embodiment, this manufacture method comprises the following steps: that at least (a) provides a base material; (b) form at least two gate trenchs in base material; (c) inner surface of formation one first dielectric layer cover gate groove; (d) form one first polysilicon structure in gate trench; (e) form at least one first groove between adjacent two gate trenchs; (f) form the second polysilicon structure of one first conductivity type in the part once of the first groove; (g) form in the base material of this tagma between gate trench of one first conductivity type, the first groove extends downward this below, tagma, and the second polysilicon structure is positioned at this below, tagma, and with the body interval every a preset distance; (h) source area that forms one second conductivity type in this tagma one on part; (i) form an interlayer dielectric layer and cover the first polysilicon structure, and utilize interlayer dielectric layer defining the one source pole contact hole corresponding to the first groove place; (j) form the heavily doped region of one first conductivity type in this tagma; And (k) insert the one source pole metal level in the source electrode contact hole, to be electrically connected heavily doped region and source area.
That is to say that the present invention also provides a kind of manufacture method that promotes the groove power semiconductor element of breakdown voltage, this manufacture method comprises the following steps: to provide base material at least; Form at least two gate trenchs in this base material; Form the inner surface that dielectric layer covers this gate trench; Form the first polysilicon structure in these at least two gate trenchs; Form at least one first groove between these two gate trenchs; Form the second polysilicon structure of the first conductivity type in the lower part of this first groove; Form this tagma of the first conductivity type between these at least two gate trenchs, this first groove extends downward this this below, tagma, and this second polysilicon structure is positioned at this this below, tagma, and with this body interval every preset distance; Form the source area of the second conductivity type in the upper part in this this tagma; Form interlayer dielectric layer and cover this first polysilicon structure, and utilize this interlayer dielectric layer corresponding to this first groove place, define the source electrode contact hole; Form the heavily doped region of the first conductivity type in this this tagma; And insert source metal in this source electrode contact hole, to be electrically connected this heavily doped region and this source area.
The present invention can improve the dynamic characteristic and lifting breakdown voltage of groove power semiconductor element, and keeps reliability of structure.
Can be further understood by means of following detailed Description Of The Invention and appended accompanying drawing about advantage of the present invention.
Description of drawings
Figure 1A to Fig. 1 H is the first embodiment of the manufacture method of the present invention's groove power semiconductor element of improving breakdown voltage;
Fig. 2 is the second embodiment of the manufacture method of the present invention's groove power semiconductor element of improving breakdown voltage;
Fig. 3 A and Fig. 3 B are the 3rd embodiment of the manufacture method of the present invention's groove power semiconductor element of improving breakdown voltage;
Fig. 3 C is the 4th embodiment of the manufacture method of the present invention's groove power semiconductor element of improving breakdown voltage;
Fig. 4 A to Fig. 4 C is the 5th embodiment of the manufacture method of the present invention's groove power semiconductor element of improving breakdown voltage;
Fig. 5 A and Fig. 5 B are the 6th embodiment of the manufacture method of the present invention's groove power semiconductor element of improving breakdown voltage;
Fig. 6 is the 7th embodiment of the manufacture method of the present invention's groove power semiconductor element of improving breakdown voltage;
Fig. 7 A and Fig. 7 B are the 8th embodiment of the manufacture method of the present invention's groove power semiconductor element of improving breakdown voltage;
Fig. 8 A to Fig. 8 E is the 9th embodiment of the manufacture method of the present invention's groove power semiconductor element of improving breakdown voltage;
Fig. 9 A to Fig. 9 F is the tenth embodiment of the manufacture method of the present invention's groove power semiconductor element of improving breakdown voltage;
Figure 10 A to Figure 10 C is other three kinds of different embodiment of manufacture method of the p-type heavily doped region of Fig. 9 E;
Figure 11 is the 11 embodiment of the manufacture method of the present invention's groove power semiconductor element of improving breakdown voltage;
Figure 12 A to Figure 12 C is the 12 embodiment of the manufacture method of the present invention's groove power semiconductor element of improving breakdown voltage;
Figure 13 is the 13 embodiment of the manufacture method of the present invention's groove power semiconductor element of improving breakdown voltage.
[main element description of reference numerals]
Gate trench 120,720,820a, 882
The first dielectric layer 130,730,830
The first polysilicon structure 140,740,840a, 840b
This tagma 150,750
Source area 160,760,1060
Patterned layer 165,465,465 ', 665,865
Heavily doped region 180,380,480,580,780,880,880 ', 980,1080
The first groove 170,770,820b
The second polysilicon structure 172,772,872
Dielectric structure 174,274,374,774,835,935
The 3rd polysilicon structure 175
Source metal 190,190 '
Heavily doped polysilicon structure 276,876
Dielectric layer 375,965
Source electrode contact hole 377,477,677,777,877,977
Dielectric pattern layer 765
Interlayer dielectric layer 775,875
Conductive structure 890,990
Embodiment
The first embodiment
Figure 1A to Fig. 1 H is the first embodiment of the manufacture method of the present invention's groove power semiconductor element of improving breakdown voltage.Describe as an example of a N-shaped groove power semiconductor element example among Figure 1A to Fig. 1 H.But the present invention is not limited to this.The present invention is certainly also applicable to the power semiconductor of p-type.
Shown in Figure 1A, at first, form N-shaped epitaxial layer 110 on a N-shaped substrate 100, to form the base material of making the groove power semiconductor element.Subsequently, form at least two gate trenchs 120 in epitaxial layer 110.Next, as shown in Figure 1B, along the surface undulation of epitaxial layer 110, form the inner surface of one first dielectric layer, 130 cover gate grooves 120.Then, form one first polysilicon structure 140 in gate trench 120, as the grid polycrystalline silicon structure of the groove power semiconductor element of present embodiment.
Then, shown in Fig. 1 C, in the implanted ions mode, form this tagma 150 of p-type in epitaxial layer 110, around each gate trench 120.Next, in the implanted ions mode, form N-shaped source area 160 in this tagma 150 one on part.This source area 160 is adjacent to gate trench 120.Subsequently, shown in Fig. 1 D, form a patterned layer 165 on epitaxial layer 110, this patterned layer 165 defines first groove in the epitaxial layer 110 of 120 of adjacent two gate trenchs.Then, shown in Fig. 1 E, in the implanted ions mode, by the opening of patterned layer 165, below source area 160, form p-type heavily doped region 180.The scope of this p-type heavily doped region 180 can be slightly larger than A/F.
Next, shown in Fig. 1 F, utilize patterned layer 165 to be etch shield, in epitaxial layer 110, form the first groove 170 with etching mode.This first groove 170 runs through this tagma 150, and source area 160 and p-type heavily doped region 180 are divided into respectively two parts.Subsequently, form lightly doped the second polysilicon structure 172 of p-type in the lower part of the first groove 170.A predeterminable range is left in the upper surface of this second polysilicon structure 172 and this tagma 150, is connected with this tagma 150 to avoid this second polysilicon structure 172.
Subsequently, shown in Fig. 1 G, form a dielectric structure 174 in the first groove 170.This dielectric structure 174 is positioned at the second polysilicon structure 172 tops, and dielectric structure 174 extends upwardly to this tagma 150, and its position extends downward this 150 belows, tagma by this tagma 150.Next, shown in Fig. 1 H, form one source pole metal level 190 in patterned layer 165 tops, and insert in the first groove 170, to connect heavily doped region 180 and source area 160.Above-mentioned patterned layer 165 is separated source metal 190 and the first polysilicon structure 140 as an interlayer dielectric layer.
The making of present embodiment by p-type the second polysilicon structure 172 forms the p-type doped region of floating below this tagma 150, with releive gate trench 120 bottoms with drain between Electric Field Distribution, thereby help to promote breakdown voltage.Therefore, present embodiment can increase the implantation depth of p-type heavily doped region 180, even allows p-type heavily doped region 180 extend downward the bottom surface in this tagma 150, and does not worry that this structure causes the excessively low problem of breakdown voltage to produce.
The second embodiment
Fig. 2 is the second embodiment of the manufacture method of the present invention's groove power semiconductor element of improving breakdown voltage.The Main Differences of present embodiment and above-mentioned first embodiment of the invention is the manufacture of p-type heavily doped region 180.In the present embodiment, p-type heavily doped region 180 is not to be formed at source area 160 belows in the implanted ions mode, but form first p-type heavily doped polysilicon structure 276 in dielectric structure 274 tops, and then form p-type heavily doped region 180 in the side of p-type heavily doped polysilicon structure 276 with thermal diffusion step.
The 3rd embodiment
Fig. 3 A and Fig. 3 B are the 3rd embodiment of the manufacture method of the present invention's groove power semiconductor element of improving breakdown voltage.The Main Differences of present embodiment and the first embodiment of the present invention is that present embodiment does not form dielectric structure 174 above the second polysilicon structure 172, but forms N-shaped the 3rd polysilicon structure 175 in the first groove 170.Fig. 3 A is the manufacturing step of accepting Fig. 1 F, as shown in Fig. 3 A, forming the second polysilicon structure 172 after the step of the lower part of the first groove 170, form a N-shaped the 3rd polysilicon structure 175 in the second polysilicon structure 172 tops, and extend upwardly at least this tagma 150.Subsequently, shown in Fig. 3 B, form one source pole metal level 190 in patterned layer 165 tops, and insert in the first groove 170, to connect heavily doped region 180 and source area 160.With regard to the structure of the groove power semiconductor element of present embodiment, interface at source metal 190 and N-shaped the 3rd polysilicon structure 175 can form Schottky diode (schottky diode), and helps to improve the switch speed of power semiconductor.
The 4th embodiment
Fig. 3 C is the 4th embodiment of the manufacture method of the present invention's groove power semiconductor element of improving breakdown voltage.The Main Differences of present embodiment and the first embodiment of the present invention is that present embodiment does not form dielectric structure 174 above the second polysilicon structure 172, but forms a metal plug in the first groove 170.This metal plug is positioned at the second polysilicon structure 172 tops, and extends upwardly at least this tagma 150.As shown in Fig. 3 C, with regard to a preferred embodiment, can be formed directly in source metal 190 ' and insert in the first groove 170, to form this metal plug.Similar in appearance to the third embodiment of the present invention, with regard to the structure of the groove power semiconductor element of present embodiment, on the interface of source metal 190 ' and the N-shaped epitaxial layer 110 of these 150 belows, tagma of p-type, also can form Schottky diode, and help to improve the switch speed of power semiconductor.
The 5th embodiment
Fig. 4 A to Fig. 4 C is the 5th embodiment of the manufacture method of the present invention's groove power semiconductor element of improving breakdown voltage.Fig. 4 A accepts the step of Fig. 1 D.After forming the first groove 170 and p-type the second polysilicon structure 172, remove first the patterned layer 165 that is covered on the epitaxial layer 110.Then, deposit a dielectric layer 375 on epitaxial layer 110 comprehensively, fill up simultaneously the first groove 170.
Next, shown in Fig. 4 B, in the lithography mode, form an opening to define source electrode contact hole 377 at dielectric layer 375.This opening is aimed at the first groove 170, and its width is greater than the A/F of the first groove 170.It should be noted that this etching step can remove the first groove 170 interior unnecessary dielectric materials simultaneously, to form dielectric structure 374.Next, shown in Fig. 4 C, utilize the dielectric layer 375 that is covered on the first polysilicon structure 140 to be shielding, push away the basal surface position of deep source contact hole 377 with etching mode downwards.Then, form p-type heavily doped region 380 in the bottom of source electrode contact hole 377 in the implanted ions mode.This p-type heavily doped region 380 is positioned at the both sides of dielectric structure 374, and the bottom of p-type heavily doped region 380 extends downward the bottom surface in this tagma 150.The subsequent step of present embodiment, roughly the same in the various embodiments described above, do not repeat them here.
The 6th embodiment
Fig. 5 A and Fig. 5 B are the 6th embodiment of the manufacture method of the present invention's groove power semiconductor element of improving breakdown voltage.The step of Fig. 5 A is to accept the step of Fig. 1 G haply, but the p-type heavily doped region 480 of present embodiment is after the making of finishing the first groove 170, just is formed at the both sides of the first groove 170.Shown in Fig. 5 A, present embodiment is covered in patterned layer 465 on the first polysilicon structure 140 with the etching of isotropic etching technology, to enlarge the A/F of patterned layer 465 after forming dielectric structure 174.Opening after this enlarges namely can be used as source electrode contact hole 477.Then, shown in Fig. 5 B, the patterned layer 465 ' after the etching is shielding, pushes away the basal surface position of deep source contact hole 477 downwards.Next, form p-type heavily doped region 480 in the implanted ions mode in the bottom surface of source electrode contact hole 477.
The 7th embodiment
Fig. 6 is the 7th embodiment of the manufacture method of the present invention's groove power semiconductor element of improving breakdown voltage.With respect to the embodiment of Fig. 5 A behind the A/F of etching mode expansion patterned layer 465, form heavily doped region 480 in source electrode contact hole bottom in the implanted ions mode again, as shown in Figure 6, present embodiment then is to utilize patterned layer 165 and dielectric structure 174 to be shielding, and directly forms p-type heavily doped region 580 in the both sides of the first groove 170 in oblique implanted ions mode.
The 8th embodiment
Fig. 7 A and Fig. 7 B are the 8th embodiment of the manufacture method of the present invention's groove power semiconductor element of improving breakdown voltage.After defining the position of the first groove 170 with patterned layer 465 first with respect to the embodiment of Fig. 5 A, expand the A/F of patterned layer 465 to form the source electrode contact hole with etching mode again, shown in Fig. 7 A and Fig. 7 B, present embodiment is the opening sidewalls formation wall structure 667 in patterned layer 665, to define the first groove 170.After the making of finishing the first groove 170, present embodiment directly divests the wall structure 667 of the opening sidewalls that is covered in patterned layer 665, and utilizes the opening of patterned layer 665 to define the position of source electrode contact hole 677.
The 9th embodiment
Fig. 8 A and Fig. 8 E are the 9th embodiment of the manufacture method of the present invention's groove power semiconductor element of improving breakdown voltage.With respect to the manufacture method of above-mentioned each embodiment, all be to finish first gate trench 120, form again the first groove 170 between adjacent two gate trenchs 120, present embodiment then is after the making of finishing the first groove, forms gate trench in its both sides again.
Shown in Fig. 8 A, at first, form one first groove 770 in epitaxial layer 110.Subsequently, form the second polysilicon structure 772 in the lower part of the first groove 770.Next, shown in Fig. 8 B, deposit a dielectric pattern layer 765 comprehensively.This dielectric pattern layer 765 fills up the first groove 770, and defines respectively a gate trench 720 in the first groove 770 both sides.Subsequently, by these dielectric pattern layer 765 etching epitaxial layers 110, to form gate trench 720.
Next, shown in Fig. 8 C, remove unnecessary dielectric material with etching mode, stay the dielectric structure 774 that is positioned at the first groove 770.Then, shown in Fig. 8 D, sequentially form the first dielectric layer 730 and the first polysilicon structure 740 in gate trench 720.Next, again in the implanted ions mode, sequentially form p-type body 750 and N-shaped source area 760 between neighboring gates groove 720, the first grooves 770.
Subsequently, shown in Fig. 8 E, form an interlayer dielectric layer 775 on epitaxial layer 110, and in this interlayer dielectric layer 775, make an opening and aim at the first groove 770, to define one source pole contact hole 777.The width of this opening is greater than the A/F of the first groove 770.Then, by the opening etching epitaxial layer 110 of this interlayer dielectric layer 775, to form source electrode contact hole 777 in dielectric structure 774 tops.Next, in the implanted ions mode, implant the bottom that p-type is doped in source electrode contact hole 777, to form p-type heavily doped region 780 in the both sides of dielectric structure 774.
In above-mentioned part embodiment, the p-type heavily doped region extends downward the bottom surface in this tagma 150 to promote the dynamic characteristic of groove power semiconductor element.But the present invention is not limited to this.Should be by actual demand, this p-type heavily doped region also further extends to this 150 belows, tagma, also or maintain the bottom surface top certain distance in this tagma 150.With regard to a preferred embodiment, the bottom surface of this p-type heavily doped region need be positioned at the top of the lower edge of dielectric structure 174, to keep suitable breakdown voltage value.
Secondly, in the various embodiments described above of the present invention, the lower part of the first groove 170 all is formed with the second polysilicon structure.But the present invention is not limited to this.With regard to a preferred embodiment, the present invention also can omit the making of the second polysilicon structure, and directly at the first groove 170 interior making dielectric structures.This dielectric structure that protrudes from this bottom surface, tagma downwards also helps to improve the Electric Field Distribution between gate trench and drain electrode, to promote breakdown voltage.
The tenth embodiment
Fig. 9 A to Fig. 9 E is the tenth embodiment of the manufacture method of the present invention's groove power semiconductor element of improving breakdown voltage.With respect to above-mentioned each embodiment, the first groove 170 is to utilize different etching steps from gate trench 120, is formed at respectively in the epitaxial layer 110, and present embodiment then is to make gate trench 820a and the first groove 820b with etching step.And in the present embodiment, gate trench 820a and the first groove 820b have the roughly the same degree of depth.
Shown in Fig. 9 A, at first, form gate trench 820a and the first groove 820b in epitaxial layer 110 in the lithography mode.Next, shown in Fig. 9 B, form one first dielectric layer 830 and cover each gate trench 820a, the inner surface of the first groove 820b.Then, at each gate trench 820a, form respectively one first polysilicon structure 840a, 840b in the first groove 820b.Then, shown in Fig. 9 C, in the implanted ions mode, sequentially form this tagma 150 of p-type in epitaxial layer 110 with the upper part of N-shaped source area 160 in this tagma 150.Subsequently, form a patterned layer 865 and cover the first polysilicon structure 840a that is positioned at gate trench 820a, and by an etching step, remove the first polysilicon structure 840b that is positioned at the first groove 820b.Then, insert a dielectric structure 835 in the first groove 820b.
Next, shown in Fig. 9 D, after first patterned layer 865 being removed, form an interlayer dielectric layer 875 and cover the first polysilicon structure 840a that is positioned at gate trench 820a.Then, in this interlayer dielectric layer 875, form an opening to define the scope of source electrode contact hole 877 in the lithography mode.This opening rough alignment the first groove 820b, and its width is greater than the A/F of the first groove 820b.Then, by the opening etching epitaxial layer 110 of this interlayer dielectric layer 875, to form one source pole contact hole 877.Next, shown in Fig. 9 E, form heavily doped region 880 in the implanted ions mode in the bottom of source electrode contact hole 877.Then, in source electrode contact hole 877, insert a conductive structure 890 to finish this manufacturing process.
Present embodiment only is manufactured with a dielectric structure 835 in the first groove 820b, and not such as the second polysilicon structure in the various embodiments described above.The existence of this dielectric structure 835 also helps to improve Electric Field Distribution, to promote breakdown voltage.Secondly, shown in Fig. 9 F, present embodiment also can be made the second extra polysilicon structure 872 below dielectric structure 835.But, need to have dielectric structure 835 to think between this second polysilicon structure and this tagma 150 and separate.
Figure 10 A, Figure 10 B and Figure 10 C are other three kinds of different embodiment of manufacture method of the p-type heavily doped region 880 of Fig. 9 E.Shown in Figure 10 A, present embodiment is that a p-type heavily doped polysilicon structure 876 is formed on the bottom prior to source electrode contact hole 877, and then forms p-type heavily doped region 880 around p-type heavily doped polysilicon structure 876 with the thermal diffusion processing procedure.Shown in Figure 10 B, present embodiment pushes deep to the bottom surface of source electrode contact hole downwards the side of dielectric structure 835.That is to say that dielectric structure 835 projects upwards in the bottom surface of source electrode contact hole.Subsequently, form p-type heavily doped region 880 in this tagma 150 of dielectric structure 835 both sides in the implanted ions mode again.It should be noted that therefore, the implantation depth of above-mentioned implanted ions step does not need too dark, can make heavily doped region 880 extend downward the bottom surface in this tagma 150 because the source electrode contact hole 877 of present embodiment is to go deep in this tagma 150.Shown in Figure 10 C, the source electrode contact hole 877 of present embodiment gos deep into the below in this tagma 150, and the bottom of source electrode contact hole 877 is exposed the N-shaped epitaxial layer 110 of these 150 belows, tagma to the open air.P-type heavily doped region 880 ' then is in oblique implanted ions mode, is formed at the both sides of source electrode contact hole 877.It should be noted that because dielectric structure 835 protrudes from the bottom surface of source electrode contact hole 877 this dielectric structure 835 can avoid oblique implanted ions step the p-type alloy to be implanted the bottom of source electrode contact hole 877.Whereby, through follow-up source metal deposition step, can form structure of Schottky diode in the bottom surface of source electrode contact hole 877, with the switch speed of bring to power semiconductor element.Secondly, present embodiment also can additionally apply a forward implanted ions step outside oblique implanted ions step, implant the N-shaped alloy in source electrode contact hole 877 bottoms, form N-shaped heavily doped region 882 in the below of source electrode contact hole 877, with the conducting voltage of further reduction structure of Schottky diode.
The 11 embodiment
Figure 11 is the 11 embodiment of the manufacture method of the present invention's groove power semiconductor element of improving breakdown voltage.With respect to the embodiment of Figure 10 C, present embodiment further adds deep source contact hole 877, makes the side of source electrode contact hole 877 extend to the below in this tagma 150.In addition, present embodiment is to form p-type doped region 873 in source electrode contact hole 877 bottoms in the implanted ions mode.Through follow-up source metal deposition step, present embodiment can form structure of Schottky diode in the side of the lower part of source electrode contact hole 877, with the switch speed of bring to power semiconductor element.In addition, the p-type doped region (p-type polysilicon structure) 873 that is formed at source electrode contact hole 877 belows helps the Electric Field Distribution of releiving, to improve breakdown voltage.
The 12 embodiment
Figure 12 A to Figure 12 C is the 12 embodiment of the manufacture method of the present invention's groove power semiconductor element of improving breakdown voltage.The embodiment that is different from Fig. 9 B and Fig. 9 C, after utilizing the removal of patterned layer 865 selective etch to be positioned at the first polysilicon structure 840b of the first groove 820b, remove immediately this patterned layer 865, shown in Figure 12 A, present embodiment selects general dielectric material to make this patterned layer 865, and after removing the first polysilicon structure 840b, keep this patterned layer 865, cover this patterned layer 865 and fill up the first groove 820b and directly form a dielectric layer 965.
Subsequently, shown in Figure 12 B, remove unnecessary dielectric material, to form dielectric structure 935 in the first groove 170.It should be noted that this etching step can remove the dielectric layer 965 that is covered on the patterned layer 865 simultaneously.Yet if select the material that has similar etching characteristic with dielectric layer 965 as patterned layer 865, this etching step can be removed the patterned layer 865 of part simultaneously, and forms outward appearance as shown in Figure 12B.Subsequently, shown in Figure 12 C, by the opening etching epitaxial layer 110 of patterned layer 865, to form source electrode contact hole 977.Then, form heavily doped region 980 in source electrode contact hole 977 bottoms in the implanted ions mode.Next, form a conductive structure (not shown) in source electrode contact hole 977, be electrically connected heavily doped region 980 and source area 160, to finish the manufacture process of present embodiment.
The 13 embodiment
In above-mentioned each embodiment, the p-type heavily doped region is positioned at the bottom of source electrode contact hole, and roughly is the below that is positioned at source area.But, the present invention is not limited to this.As shown in figure 13, this p-type heavily doped region 1080 also can be that alternative arrangement is in the superficial layer in this tagma 150 with source area 1060.As for the manufacture method of the p-type heavily doped region 1080 among this embodiment with source area 1060, except can utilize the little shadow step of twice respectively the superficial layer in this tagma 150 define the position of heavily doped region and source area, and impose respectively outside the implanted ions step, also can only utilize little shadow step together to define the position of heavily doped region or source area.For instance, can implant the N-shaped alloy at the superficial layer in this tagma 150 first comprehensively, and then define the scope of heavily doped region with little shadow step, and be implanted into the p-type alloy of high concentration in the scope that defines out, make the conductivity type of implanting the zone change p-type into by N-shaped.Whereby, can form heavily doped region and the source area of alternative arrangement.Above-described embodiment utilizes the scope of little shadow step definition heavily doped region, and before the step of definition heavily doped region, implants the N-shaped alloy prior to the superficial layer of body comprehensively.But, the present invention is not limited to this.This little shadow step also can be in order to defining the scope of source area, and above-mentioned comprehensive implantation step also can be and implants the p-type alloy.
As mentioned above, the manufacture method of groove power semiconductor element of the present invention can make the first groove auto-alignment in P type heavily doped region, to avoid the generation of alignment error.Next, the second polysilicon structure and dielectric structure that present embodiment is formed at part under the first groove help to improve Electric Field Distribution between gate trench and drain electrode.Simultaneously, collocation is formed at the dielectric structure both sides, and extends to the heavily doped region of body bottom surface, can between the keeping of the improvement of the dynamic characteristic of groove power semiconductor element and breakdown voltage, obtain good balance.
The present invention can improve the dynamic characteristic and lifting breakdown voltage of groove power semiconductor element, and keeps reliability of structure.
But the above; it only is preferred embodiment of the present invention; can not limit protection scope of the present invention with this, i.e. all simple equivalences of doing according to claim of the present invention and description change and revise, and all still belong in the scope that claim of the present invention contains.Arbitrary embodiment of the present invention or claim scope do not need to reach the disclosed whole purposes of the present invention or advantage or characteristics in addition.In addition, summary part and title only are the usefulness of the auxiliary Searches of Patent Literature, are not to limit protection scope of the present invention.
Claims (15)
1. a groove power semiconductor element that promotes breakdown voltage is characterized in that, the groove power semiconductor element of this lifting breakdown voltage comprises:
Base material;
At least two gate trenchs are positioned at this base material;
The first dielectric layer covers the inner surface of this gate trench;
The first polysilicon structure is positioned at this at least two gate trenchs;
At least one first groove is between these two gate trenchs;
This tagma of the first conductivity type is positioned between these two gate trenchs at least, and this first groove runs through this this tagma and extends to this this below, tagma;
The second polysilicon structure of the first conductivity type is inserted the lower part of this first groove, and this second polysilicon structure is positioned at this this below, tagma, and with this body interval every preset distance;
The source area of the second conductivity type is positioned at the upper part in this this tagma, and this second conductivity type is electrical opposite with this first conductivity type;
The heavily doped region of the first conductivity type is positioned at this this tagma; And
Source metal is electrically connected this heavily doped region and this source area.
2. the groove power semiconductor element of lifting breakdown voltage as claimed in claim 1 is characterized in that, this heavily doped region and this source area alternative arrangement should upper parts in this this tagma.
3. the groove power semiconductor element of lifting breakdown voltage as claimed in claim 1, it is characterized in that this groove power semiconductor element also comprises dielectric structure, insert in this first groove, this dielectric structure is positioned at this second polysilicon structure top, and extends upwardly to this this tagma.
4. the groove power semiconductor element of lifting breakdown voltage as claimed in claim 3, it is characterized in that, this groove power semiconductor element also comprises interlayer dielectric layer, be positioned on this first polysilicon structure, this interlayer dielectric layer is corresponding to this first groove place, definition has width greater than the source electrode contact hole of this first groove, and this heavily doped region is positioned at the bottom of this source electrode contact hole.
5. the groove power semiconductor element of lifting breakdown voltage as claimed in claim 4 is characterized in that, this dielectric structure protrudes from the bottom of this source electrode contact hole, and this heavily doped region is positioned at the both sides of this dielectric structure.
6. the groove power semiconductor element of lifting breakdown voltage as claimed in claim 3 is characterized in that, this heavily doped region is adjacent to this dielectric structure, and the bottom of this heavily doped region extends to this this below, tagma.
7. such as the groove power semiconductor element of each described lifting breakdown voltage of claim 1 to 6, also comprise plug structure, insert in this first groove, this plug structure is positioned at this second polysilicon structure top, and extend upwardly at least this this tagma, and this plug structure is the 3rd polysilicon structure or the metal plug of the second conductivity type.
8. a manufacture method that promotes the groove power semiconductor element of breakdown voltage is characterized in that the manufacture method of this groove power semiconductor element comprises the following steps: at least
Base material is provided;
Form at least two gate trenchs in this base material;
Form the inner surface that the first dielectric layer covers this gate trench;
Form the first polysilicon structure in these at least two gate trenchs;
Form at least one first groove between these two gate trenchs;
Form the second polysilicon structure of the first conductivity type in the lower part of this first groove;
Form this tagma of the first conductivity type between these at least two gate trenchs, this first groove extends downward this this below, tagma, and this second polysilicon structure is positioned at this this below, tagma, and with this body interval every preset distance;
Form the source area of the second conductivity type in the upper part in this this tagma;
Form interlayer dielectric layer and cover this first polysilicon structure, and utilize this interlayer dielectric layer corresponding to this first groove place, define the source electrode contact hole;
Form the heavily doped region of the first conductivity type in this this tagma; And
Insert source metal in this source electrode contact hole, to be electrically connected this heavily doped region and this source area.
9. the manufacture method of the groove power semiconductor element of lifting breakdown voltage as claimed in claim 8, it is characterized in that, after the step of the second polysilicon structure that forms this first conductivity type, also comprise and insert dielectric structure in this first groove, this dielectric structure is positioned at this second polysilicon structure top, and extend upwardly to this this tagma, the step that forms this dielectric structure comprises:
Form dielectric layer and cover this interlayer dielectric layer, and fill up this first groove; And
Remove this dielectric layer in this first groove outside with etching mode, and expand the width of this source electrode contact hole.
10. the manufacture method of the groove power semiconductor element of lifting breakdown voltage as claimed in claim 8, it is characterized in that, the step that forms this heavily doped region and this source area comprises two road implanted ions steps, implant respectively the alloy of the alloy of this first conductivity type and this second conductivity type in this this tagma, and, the implantation zone of this two roads implanted ions step has part to overlap, to form this heavily doped region and this source area alternative arrangement in the upward part in this this tagma.
11. the manufacture method of the groove power semiconductor element of lifting breakdown voltage as claimed in claim 8, it is characterized in that, form the step of this heavily doped region for to implant the alloy of this first conductivity type in this this tagma by this source electrode contact hole, to form this heavily doped region, and the bottom of this heavily doped region extends to this this below, tagma.
12. the manufacture method of the groove power semiconductor element of lifting breakdown voltage as claimed in claim 8 is characterized in that, the step that forms this heavily doped region comprises:
Form the heavily doped polysilicon structure in this dielectric structure top; And
Make the interior alloy thermal diffusion of this heavily doped polysilicon structure to this this tagma, to form this heavily doped region.
13. the manufacture method of the groove power semiconductor element of lifting breakdown voltage as claimed in claim 8, it is characterized in that, the step that forms this first groove is later than and forms this source area in the upward step of part in this this tagma, and this first groove runs through this this tagma.
14. the manufacture method of the groove power semiconductor element of lifting breakdown voltage as claimed in claim 8, it is characterized in that, form the step of this first groove early than the step that forms this this tagma, the degree of depth of this first groove is greater than the degree of depth of this gate trench, and, form the step of this second polysilicon structure early than the step that forms this first polysilicon structure.
15. the manufacture method of the groove power semiconductor element of lifting breakdown voltage as claimed in claim 8, it is characterized in that, after forming the step of the second polysilicon structure of this first conductivity type, also comprise and insert plug structure in this first groove, this plug structure is positioned at this second polysilicon structure top, and extend upwardly at least this this tagma, the 3rd polysilicon structure or the metal plug of plug structure the second conductivity type.
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| Application Number | Priority Date | Filing Date | Title |
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| TW100137607 | 2011-10-18 | ||
| TW100137607A TWI419334B (en) | 2011-10-18 | 2011-10-18 | Trenched power mosfet with enhanced breakdown voltage and fabrication method thereof |
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| CN103066102B CN103066102B (en) | 2016-05-04 |
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| CN107154425A (en) * | 2016-03-03 | 2017-09-12 | 瑞萨电子株式会社 | Semiconductor device |
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| WO2015033181A1 (en) * | 2013-09-05 | 2015-03-12 | Freescale Semiconductor, Inc. | A power field effect transistor, a power field effect transistor device and a method of manufacturing a power field effect transistor |
| DE102015221054A1 (en) * | 2015-10-28 | 2017-05-04 | Robert Bosch Gmbh | Power MOSFET and method of making a power MOSFET |
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| CN101385147A (en) * | 2006-04-29 | 2009-03-11 | 万国半导体股份有限公司 | Enhancing schottky breakdown voltage (bv) without affecting an integrated mosfet-schottky device layout |
| CN102201366A (en) * | 2010-03-23 | 2011-09-28 | 科轩微电子股份有限公司 | Trench type power semiconductor structure with Schottky diode and manufacturing method thereof |
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| US5877528A (en) * | 1997-03-03 | 1999-03-02 | Megamos Corporation | Structure to provide effective channel-stop in termination areas for trenched power transistors |
| TW456049B (en) * | 2000-09-05 | 2001-09-21 | Ind Tech Res Inst | Trench-type metal oxide semiconductor stop structure |
| TW588460B (en) * | 2003-01-24 | 2004-05-21 | Ind Tech Res Inst | Trench power MOSFET and method of making the same |
| TW200908321A (en) * | 2007-08-01 | 2009-02-16 | Ptek Technology Co Ltd | Trench power MOSFET and its manufacturing method |
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| US20020115257A1 (en) * | 2001-02-19 | 2002-08-22 | Hitachi, Ltd. | Insulated gate type semiconductor device and method for fabricating the same |
| CN101385147A (en) * | 2006-04-29 | 2009-03-11 | 万国半导体股份有限公司 | Enhancing schottky breakdown voltage (bv) without affecting an integrated mosfet-schottky device layout |
| CN102201366A (en) * | 2010-03-23 | 2011-09-28 | 科轩微电子股份有限公司 | Trench type power semiconductor structure with Schottky diode and manufacturing method thereof |
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| CN107154425A (en) * | 2016-03-03 | 2017-09-12 | 瑞萨电子株式会社 | Semiconductor device |
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| TWI419334B (en) | 2013-12-11 |
| CN103066102B (en) | 2016-05-04 |
| TW201318166A (en) | 2013-05-01 |
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Effective date of registration: 20170421 Address after: Hsinchu County, Taiwan, China Patentee after: Shuaiqun Microelectronic Co., Ltd. Address before: Chinese Taiwan New Taipei City Patentee before: Kexuan Microelectronic Co.,Ltd. |