CN103050495B - OTP memory cell and making method thereof - Google Patents
OTP memory cell and making method thereof Download PDFInfo
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- CN103050495B CN103050495B CN201110310896.XA CN201110310896A CN103050495B CN 103050495 B CN103050495 B CN 103050495B CN 201110310896 A CN201110310896 A CN 201110310896A CN 103050495 B CN103050495 B CN 103050495B
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- 238000000034 method Methods 0.000 title claims abstract description 41
- 238000003860 storage Methods 0.000 claims abstract description 53
- 239000000758 substrate Substances 0.000 claims abstract description 35
- 238000002955 isolation Methods 0.000 claims abstract description 15
- 239000000463 material Substances 0.000 claims description 26
- 238000009413 insulation Methods 0.000 claims description 18
- 238000000151 deposition Methods 0.000 claims description 12
- 230000008021 deposition Effects 0.000 claims description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 7
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 7
- 230000015572 biosynthetic process Effects 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 6
- 238000005516 engineering process Methods 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 3
- 238000005468 ion implantation Methods 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 claims description 3
- 239000010410 layer Substances 0.000 abstract description 47
- 238000004519 manufacturing process Methods 0.000 abstract description 10
- 239000011241 protective layer Substances 0.000 abstract description 9
- 238000007667 floating Methods 0.000 abstract description 7
- 238000010276 construction Methods 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 5
- 230000015556 catabolic process Effects 0.000 description 4
- 230000008878 coupling Effects 0.000 description 3
- 238000010168 coupling process Methods 0.000 description 3
- 238000005859 coupling reaction Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910002370 SrTiO3 Inorganic materials 0.000 description 2
- MCMNRKCIXSYSNV-UHFFFAOYSA-N ZrO2 Inorganic materials O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 2
- 239000012774 insulation material Substances 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 206010021703 Indifference Diseases 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
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Abstract
The present invention discloses a kind of OTP memory cell and making method thereof. This OTP memory cell, comprising: semiconducter substrate; Gate dielectric layer; Store grid and control grid; The side wall that described storage grid and control grid the are separated isolation structure being positioned at around described storage grid; It is wrapped in the insulating protective layer on described storage grid and control grid surface; It is positioned at the gating electrode that described control grid side contacts with described semiconducter substrate; And it is positioned at the doped well region below the described gating electrode of described semiconducter substrate. This OTP memory cell, for traditional floating grid OTP, make use of the impact on device electrology characteristic that punctures of thin gate dielectric layer and realizes storing. Its compact construction, principle is simple, stores programming easy to operate, and the making method of this structure is mutually compatible with standard logic processing procedure, and technique is simple, it is possible to save manufacturing cost greatly.
Description
Technical field
The present invention relates to the device architecture of storer and relative production technique, particularly relate to memory cell structure and the making method thereof of a kind of disposable programmable (OTP, onetimeprogrammable) storer, belong to field of manufacturing semiconductor devices.
Background technology
System integrated chip popular at present or micro-chip processor, a storer is all needed to carry out stocking system code, owing to the Making programme of logic and conventional memory is widely different, comparing traditional mode is introduce read-only storage (ROM) in logic processing procedure. But the process being produced on wafer flow of read-only storage just needs definition, constrains the handiness of system coding to a certain extent. For this shortcoming of read-only storage, it is possible to by circuit card respectively logic chip together with memory chip package, like this system code can be changed by the change of memory chip content. But such mode is because needing two pieces or above chip, the height that manufacturing cost can be suitable, and the cost of encapsulation also can be very high, and the area of chip is also very big, meanwhile, owing to signal demand is transmitted by circuit card, is easy to be subject to assorted news interference.
Disposable programmable (OTP) storer, owing to its cost is lower and mutually compatible with logic processing procedure, is widely used in recent years. Traditional ROM read-only storage is substituted, it is possible to greatly improve the handiness of chip system code by adding otp memory in integrated circuit (IC) chip. That is, after wafer flow terminates, it is possible to by the form of coding, code is write otp memory, for different clients and Realization of Product indifference, namely different code can be provided to realize different functions for different clients like this. Otp memory is made up of with the peripheral circuit mated mutually with it OTP memory cell array usually, existing OTP memory cell generally adds one by a coupling capacity (or NMOS gating pipe), and a floating gate transistor (nmos pass transistor) is formed, (HCI can be injected by thermoelectron, etc. hotcarrierinjection) it is programmed by method, make electron storage on multi-crystal silicon floating bar, then utilize the size of threshold voltage to judge on floating grid with or without injection electronics, thus symbolize 0 or 1 at a unit.
But, this kind of existing OTP memory cell each floating gate transistor corresponding needs a coupling capacity, and the usual area of condenser coupling part is relatively big, occupies the area of storer greatly, and its manufacturing process is also more complicated.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of OTP memory cell of puncturing based on gate dielectric layer and making method thereof.
In order to solve the problems of the technologies described above, the present invention adopts following technical scheme:
A kind of OTP memory cell, comprising:
Semiconducter substrate;
The gate dielectric layer being positioned in described semiconducter substrate;
The storage grid being positioned on described gate dielectric layer and control grid;
The side wall isolation structure being positioned at around described storage grid, described storage grid and control grid are separated by described side wall isolation structure;
It is wrapped in the insulating protective layer on described storage grid and control grid surface;
It is positioned at the gating electrode that described control grid side contacts with described semiconducter substrate, separates by insulating protective layer between described gating electrode and described control grid;
It is positioned at the doped well region below the described gating electrode of described semiconducter substrate.
As the preferred version of the present invention, described semiconducter substrate is monocrystalline substrate.
As the preferred version of the present invention, the material of described gate dielectric layer is silicon oxide or other high dielectric constant materials.
As the preferred version of the present invention, the material of described storage grid and control grid is polysilicon.
As the preferred version of the present invention, the material of described insulating protective layer is silicon oxide.
A making method for OTP memory cell, comprises the following steps:
Step one, on a semiconductor substrate formation one layer of gate dielectric layer, then on described gate dielectric layer, form storage grid; And around described storage grid, form side wall isolation structure;
Step 2, described storage grid and side wall isolation structure surface deposition first insulation layer;
Step 3, depositing grid material in the semiconducter substrate being formed with described storage grid and side wall isolation structure, then remove the side formation control grid of unnecessary grid material at described storage grid, described storage grid and control grid are isolated structure by side wall and are separated;
Step 4, in described semiconducter substrate, form doped well region, make described doped well region be positioned at another side relative with described storage grid of described control grid;
Step 5, at described control grid surface deposition the 2nd insulation layer;
Step 6, making gating electrode make it to contact with the described doped well region in semiconducter substrate, separate by the 2nd insulation layer between described gating electrode and described control grid. Wherein, the 2nd insulation layer can be used as the insulating protective layer of device unit.
As the preferred version of the present invention, in step one, described semiconducter substrate is monocrystalline substrate; The material of described gate dielectric layer is silicon oxide or other high dielectric constant materials; The material of described storage grid is polysilicon.
As the preferred version of the present invention, in step 2, described deposition first insulation layer is deposition thermal oxide layer.
As the preferred version of the present invention, in step 2, described first insulation layer is also covered in the surface that described gate dielectric layer exposes; Can be used to increase the grid medium thickness below subsequent control grid.
As the preferred version of the present invention, in step 3, described grid material is polysilicon.
As the preferred version of the present invention, in step 3, remove unnecessary grid material by chemically machinery polished and etching technics, thus form described control grid.
As the preferred version of the present invention, in step 3, form described doped well region by ion implantation technology.
As the preferred version of the present invention, the making method of this OTP memory cell also comprises the step making contact hole and draw control grid electrode and memory gate electrode respectively, described control grid electrode contacts with described control grid, and described memory gate electrode contacts with described storage grid.
The useful effect of the present invention is:
The OTP memory cell of the present invention is different from traditional floating grid OTP, and the method not adopting floating grid thermoelectron to inject carries out storing data, but the impact on device electrology characteristic that punctures that make use of gate dielectric layer realizes storing. Its compact construction, principle is simple, stores programming easy to operate, and the making method of this structure is mutually compatible with standard logic processing procedure, and technique is simple, it is possible to save manufacturing cost greatly.
Accompanying drawing explanation
Fig. 1 is the structural representation of OTP memory cell in the embodiment of the present invention one;
Fig. 2 a punctures the principle schematic of gate dielectric layer when being OTP memory cell write data in the embodiment of the present invention one;
Fig. 2 b punctures the circuit diagram of gate dielectric layer when being OTP memory cell write data in the embodiment of the present invention one;
The circuit diagram that when Fig. 3 is that in the embodiment of the present invention one, OTP memory cell reads data, gate dielectric layer is breakdown;
Fig. 4 a-4g is the Making programme schematic diagram of OTP memory cell in the embodiment of the present invention two.
Embodiment
The preferred embodiments of the present invention and concrete implementation step are described further below in conjunction with accompanying drawing, and in order to the convenience illustrated, accompanying drawing is not proportionally drawn.
The present inventor, in order to simplify otp memory preparation technology, reduces production cost, and structure and principle to otp memory conduct in-depth research, and have devised and a kind of punctures based on gate dielectric layer, the OTP memory cell that cost of manufacture is lower.
Embodiment one
As shown in Figure 1, this OTP memory cell comprises: semiconducter substrate 100; The gate dielectric layer 101 being positioned in described semiconducter substrate 100; The storage grid 102 being positioned on described gate dielectric layer 101 and control grid 103; The side wall isolation structure 104 being positioned at around described storage grid 102; It is wrapped in described storage grid 102 and the insulating protective layer 105 on control grid 103 surface; It is positioned at the gating electrode 106 that described control grid 103 side contacts with described semiconducter substrate 100, it is positioned at the doped well region 1001 below the described gating electrode 106 of described semiconducter substrate 100. Wherein, described storage grid 102 and control grid 103 are separated by described side wall isolation structure 104, separate by insulating protective layer 105 between described gating electrode 106 and described control grid 103.
In the present embodiment, the monocrystalline substrate that semiconducter substrate 100 can be preferably common; Described gate dielectric layer 101 can select conventional dielectric materials, and such as silicon oxide, gate dielectric layer 101 described in other embodiments can also be SrTiO3、HfO2Or ZrO2Deng high dielectric constant material; The material of described storage grid 102 and control grid 103 can be preferably polysilicon; The material of described side wall isolation structure 104 can be preferably the customary insulation materials such as silicon oxide; Described insulating protective layer 105 can also be preferably the customary insulation materials such as silicon oxide; Described doped well region 1001 can be P type trap zone can also be N-type well region, the drain region in similar standard CMOS. It should be noted that, the preferred material mentioned in the present embodiment is exemplarily property explanation only, in actual applications, device size and selecting of material should be not limited only to this.
As shown in Figure 2 a, when this OTP memory cell is write data: control grid G1 is by this unit gating, and voltage is added to by concentrating and stores grid G2 place so that it is the thinner gate dielectric layer of lower section is breakdown, thus completes programming." 0 " or " 1 " two states can be defined according to whether gate dielectric layer is breakdown, thus realize the storage of information. Now, circuit diagram as shown in Figure 2 b, in the present embodiment, write data time, the substrate ground connection (not shown) of storage unit; Gating electrode meets high-voltage+Vcc by bit line BL, such as 1.8-3.3V; Control grid G1 meets high-voltage+Vcc; Store grid G2 and meet low voltage-Vcc, such as-3.3 to-1.8V.
When to this OTP memory cell read data time, control grid G1 by this unit gating, by judging now whether storage unit has outflow of bus current to determine the data that this storage unit stores. When storage unit is read data information, if it is breakdown to store gate dielectric layer below grid G2, then as shown in Figure 3, storage unit has current flowing to its circuit diagram; If storing gate dielectric layer below grid G2 not punctured by voltage, even if then there being voltage difference to exist, electric current is not still had to pass through. In the present embodiment, when reading data, the substrate ground connection of this storage unit; Gating electrode meets high-voltage+Vcc by bit line BL, such as 1.8-3.3V; Control grid G1 meets high-voltage+Vcc; Store grid G2 ground connection.
It should be noted that, the present embodiment writes data and reads high-voltage or the ground connection only exemplarily property explanation that data are mentioned, in actual applications, the scope of operating voltage should be not limited only to this.
Embodiment two
Consulting Fig. 4 a-4g, this kind of OTP memory cell can adopt following method to make:
Step one, as shown in fig. 4 a, there is provided the monocrystalline substrate commonly used as semiconducter substrate 200, then one layer of gate dielectric layer 201 is formed on this monocrystalline substrate surface, thermal oxidation method such as can be adopted to form grid oxide layer, the methods such as deposition can certainly be adopted to form other dielectric materialss as gate dielectric layer 201, such as SrTiO3、HfO2Or ZrO2Deng high dielectric constant material; Then formed on described gate dielectric layer 201 and store grid 202, such as, store grid 202 by deposit spathic silicon to be formed; And then formation side wall isolates structure 204 around described storage grid 202. Wherein, make gate dielectric layer 201, storage grid 202 and side wall isolation structure 204 thereof and can adopt conventional logic processing procedure, do not repeat them here.
Step 2, as shown in Figure 4 b, in step one resulting structures surface, namely forms the first insulation layer 2051 at described storage grid 202 and side wall isolation structure 204 surface thereof, such as, deposits one layer of high temperature oxide layer (HTO). This first insulation layer 2051 is for the protection of storage grid 202; subsequent technique is avoided it to be impacted; in addition; owing to the first insulation layer 2051 during actual fabrication is also covered on the gate dielectric layer 201 stored around grid 202, the first insulation layer 2051 is also used as increasing the grid medium thickness below subsequent control grid 203 simultaneously.
Step 3, as illustrated in fig. 4 c, on step 2 resulting structures surface, namely in the semiconducter substrate 200 being formed with described storage grid 202 and side wall isolation structure 204, grid material 2031 is deposited, then, as shown in figure 4d, removing the side formation control grid 203 of unnecessary grid material 2031 at described storage grid 202 by chemically machinery polished (CMP) and etching technics, described storage grid 202 and control grid 203 are isolated structure 204 by side wall and are separated.
Step 4, as shown in fig 4e, on step 3 resulting structures basis, by methods such as ion implantations, in described semiconducter substrate 200, form doped well region 2001, make described doped well region 2001 be positioned at another side relative with described storage grid 202 of described control grid 203.
Step 5, as shown in fig. 4f, on step 4 resulting structures surface, is namely included in described control grid 203 surface, and deposition the 2nd insulation layer the 2052, two insulation layer 2052 can be used as the insulating protective layer of whole device unit.
Step 6, as shown in figure 4g, by making contact hole, makes gating electrode 206 and makes it to contact with the described doped well region 2001 in semiconducter substrate 200. Separate by the 2nd insulation layer 2052 between described gating electrode 206 and described control grid 203.
In addition, in order to conducting control grid and storage grid, in addition it is also necessary to making contact hole and also draw control grid electrode and memory gate electrode respectively, described control grid electrode contacts with described control grid 203, and described memory gate electrode contacts with described storage grid 202.
Those skilled in the art are according to aforesaid method, it is possible to produce the memory cell array being made up of this OTP memory cell, and the peripheral circuit mated mutually with it, thus can form complete otp memory. This otp memory is applied to the handiness that can improve system coding in system integrated chip or micro-chip processor, and manufacturing cost can be saved greatly.
It should be noted that, herein, term " comprises ", " comprising " or its any other variant are intended to contain comprising of nonexcludability, so that comprise the process of a series of key element, method, article or equipment not only comprise those key elements, but also comprise other key elements clearly do not listed, or also comprise the key element intrinsic for this kind of process, method, article or equipment. When not more restrictions, the key element limited by statement " comprising ... ", and be not precluded within process, method, article or the equipment comprising described key element and also there is other identical element.
Above-described embodiment only listing property principle and effect of the present invention is described, but not for limiting the present invention. Above-described embodiment all can without departing from the spirit and scope of the present invention, be modified by any person skilled in the art person. Therefore, the scope of the present invention, should as listed by claim book.
Claims (8)
1. the making method of an OTP memory cell, it is characterised in that, comprise the following steps:
Step one, on a semiconductor substrate formation one layer of gate dielectric layer, then on described gate dielectric layer, form storage grid; And around described storage grid, form side wall isolation structure;
Step 2, described storage grid and side wall isolation structure surface deposition first insulation layer;
Step 3, depositing grid material in the semiconducter substrate being formed with described storage grid and side wall isolation structure, then remove the side formation control grid of unnecessary grid material at described storage grid, described storage grid and control grid are isolated structure by side wall and are separated;
Step 4, in described semiconducter substrate, form doped well region, make described doped well region be positioned at another side relative with described storage grid of described control grid;
Step 5, at described control grid surface deposition the 2nd insulation layer;
Step 6, making gating electrode make it to contact with the described doped well region in semiconducter substrate, separate by the 2nd insulation layer between described gating electrode and described control grid.
2. the making method of OTP memory cell according to claim 1, it is characterised in that: in step one, described semiconducter substrate is monocrystalline substrate; The material of described gate dielectric layer is silicon oxide or high dielectric constant material; The material of described storage grid is polysilicon.
3. the making method of OTP memory cell according to claim 1, it is characterised in that: in step 2, described deposition first insulation layer is deposition thermal oxide layer.
4. the making method of OTP memory cell according to claim 1, it is characterised in that: in step 2, described first insulation layer is also covered in the surface that described gate dielectric layer exposes.
5. the making method of OTP memory cell according to claim 1, it is characterised in that: in step 3, described grid material is polysilicon.
6. the making method of OTP memory cell according to claim 1, it is characterised in that: in step 3, remove unnecessary grid material by chemically machinery polished and etching technics, thus form described control grid.
7. the making method of OTP memory cell according to claim 1, it is characterised in that: in step 3, form described doped well region by ion implantation technology.
8. the making method of OTP memory cell according to claim 1, it is characterized in that: the making method of this OTP memory cell also comprises the step making contact hole and draw control grid electrode and memory gate electrode respectively, described control grid electrode contacts with described control grid, and described memory gate electrode contacts with described storage grid.
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| US6667902B2 (en) * | 2001-09-18 | 2003-12-23 | Kilopass Technologies, Inc. | Semiconductor memory cell and memory array using a breakdown phenomena in an ultra-thin dielectric |
| CN101315906A (en) * | 2007-05-31 | 2008-12-03 | 和舰科技(苏州)有限公司 | Once programmable memory structure and manufacturing method thereof |
| CN101373773A (en) * | 2007-08-20 | 2009-02-25 | 和舰科技(苏州)有限公司 | Disposable programmable memory, memory capacitor and manufacturing method thereof |
| CN101752382A (en) * | 2008-12-15 | 2010-06-23 | 北京芯技佳易微电子科技有限公司 | One-time programmable memory and manufacture and programming reading method |
| CN102057441A (en) * | 2008-04-04 | 2011-05-11 | 赛鼎矽公司 | Low threshold voltage anti-fuse device |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6667902B2 (en) * | 2001-09-18 | 2003-12-23 | Kilopass Technologies, Inc. | Semiconductor memory cell and memory array using a breakdown phenomena in an ultra-thin dielectric |
| CN101315906A (en) * | 2007-05-31 | 2008-12-03 | 和舰科技(苏州)有限公司 | Once programmable memory structure and manufacturing method thereof |
| CN101373773A (en) * | 2007-08-20 | 2009-02-25 | 和舰科技(苏州)有限公司 | Disposable programmable memory, memory capacitor and manufacturing method thereof |
| CN102057441A (en) * | 2008-04-04 | 2011-05-11 | 赛鼎矽公司 | Low threshold voltage anti-fuse device |
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