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CN103000537B - Encapsulating structure of a kind of wafer scale and preparation method thereof - Google Patents

Encapsulating structure of a kind of wafer scale and preparation method thereof Download PDF

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Publication number
CN103000537B
CN103000537B CN201110290446.9A CN201110290446A CN103000537B CN 103000537 B CN103000537 B CN 103000537B CN 201110290446 A CN201110290446 A CN 201110290446A CN 103000537 B CN103000537 B CN 103000537B
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Prior art keywords
wafer
chip
plastic packaging
layer
thinning
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CN201110290446.9A
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CN103000537A (en
Inventor
薛彦迅
黄平
何约瑟
哈姆扎·耶尔马兹
鲁军
鲁明联
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Alpha and Omega Semiconductor Cayman Ltd
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Alpha and Omega Semiconductor Inc
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Priority to CN201110290446.9A priority Critical patent/CN103000537B/en
Publication of CN103000537A publication Critical patent/CN103000537A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H01L2224/05558—Shape in side view conformal layer on a patterned surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The present invention relates generally to packaging body of a kind of semiconductor device and preparation method thereof, more precisely, the present invention relates to a kind of in Wafer level packaging, chip is carried out overall package and makes it there is no exposed encapsulating structure outside plastic packaging material and preparation method thereof.In wafer level packaging structure provided by the present invention, distribution again technology is utilized to become to be arranged in cover the arrangement solder joint of the top insulating medium layer of chip by the weld pad being distributed in chip end face again layout designs, and by forming the metal material of filling in through hole in a silicon substrate and through hole, some electrodes of chip end face or signal terminal being connected to and being positioned on the bottom-side electrodes metal level of die bottom surface.And the top plastic-sealed body comprised in wafer level packaging structure and bottom plastic packaging physical efficiency, preferably by sealing seamless for chip, form good mechanical protection and electic protection.

Description

Encapsulating structure of a kind of wafer scale and preparation method thereof
Technical field
The present invention relates generally to packaging body of a kind of semiconductor device and preparation method thereof, more precisely, the present invention relates to a kind of in Wafer level packaging, chip is carried out overall package and makes it there is no exposed encapsulating structure outside plastic packaging material and preparation method thereof.
Background technology
In advanced chip package mode, wafer-level packaging WLCSP (WaferLevelChipScalePackaging) carries out packaging and testing in advance on full wafer wafer, and plastic packaging is carried out to it, then IC packaging body particle one by one is just cut to, namely the volume of the packaging body therefore after encapsulation is almost equal to the life size of bare chip, and this packaging body possesses good heat radiation and electric property.
Usually, in the complicated technology flow process of wafer-level packaging, no matter be based on considering the reduction of resistance substrate or reducing the size of chip, finally need thinned die to certain thickness.And chip is thinner cracked, this just requires the damage doing one's utmost to be avoided chip being caused to any form, but actual process preparation flow is exactly unsatisfactory, the cutting of such as wafer easily causes the edge of chip or corner to burst apart to some extent, and the chip that one of its consequence obtains is frangible or unfilled corner.On the other hand; in the chip scale package body of Most current wafer scale; chip part in device is exposed outside plastic packaging material; its harmful effect causes chip humidity-proof ability difference and plastic-sealed body cannot provide omnibearing mechanical protection, and electric property is also suppressed to a certain extent.Publication number is a kind of method that the United States Patent (USP) of US2009/0032871 discloses wafer-level packaging, its chips completes plastic packaging and by from after wafer point is cut off, a part of electrode of chip front side is connected by the electrode of the conductive structure with chip back that are positioned at chip sides, but the electrode of chip back remains exposed outside plastic packaging material.The patent No. be 6107164 United States Patent (USP) equally also disclose a kind of method of wafer-level packaging, by first carrying out cutting in the front of wafer and carrying out plastic packaging, again from the thinning back side wafer of wafer, cut off from wafer point by chip afterwards, the back side completing the chip of plastic packaging obtained is still still exposed outside plastic packaging material.Similar, also have the patent No. to be respectively the United States Patent (USP) case of US6420244 and 6852607, these patent applications all do not solve the problem how chip can also being carried out complete seal protection while thinned wafer.
Summary of the invention
In view of the above problems, the present invention proposes a kind of method of wafer-level packaging, include on the wafer of multiple chip one, distribution again technology RDL is utilized to become to be arranged in cover the arrangement solder joint of the insulating medium layer of chip by the weld pad being distributed in chip end face again layout designs, arrangement solder joint comprises first kind arrangement solder joint, comprises the following steps: on described arrangement solder joint, settle solder projection; The front of wafer described in plastic packaging, with coated insulating medium layer and the solder projection being positioned at wafer frontside of the first plastic packaging layer; Grind in the back side of wafer; The back side of the wafer after coating one deck barrier layer is extremely thinning, and form the opening being arranged in barrier layer; By be opened on thinning after the back side of wafer etch, form the through hole of contact first kind arrangement solder joint in the substrate comprised in wafer and insulating medium layer, and remove barrier layer; Fill in metal material to described through hole; The back side of the wafer after thinning covers layer of metal layer; The back side being coated with metal level of the wafer after thinning is cut wafer, form the cutting groove of isolating chip, and cutting groove stops in the first plastic packaging layer; Plastic packaging is carried out to wafer in the back side being coated with metal level of the wafer after thinning, forms the second plastic packaging layer of covered with metal layer, and plastic packaging material is also filled in cutting groove simultaneously; Grind the first plastic packaging layer to be exposed in the first plastic packaging layer of solder projection after thinning; Cut in described cutting groove, chip is separated.
Above-mentioned method, formation described through hole after, also on the inwall of described through hole, deposit isolation liner bed course, and fill metal material by isolation liner bed course and be looped around around through hole substrate region insulation.Above-mentioned method, forming the mode of through hole is dry etching or wet etching or laser ablation.Above-mentioned method, the described first kind contacted with through hole arranges the position of solder joint, is arranged in the insulating medium layer on the substrate non-active device cell region that covers.Above-mentioned method, described chip is rectilinear MOSFET.Above-mentioned method, formed in the process of the through hole of contact first kind arrangement solder joint, the described first kind contacted with through hole arranges the drain electrode that solder joint forms described MOSFET; And in the arrangement solder joint of all non-first kind arrangement solder joints, do not form gate electrode and source electrode that the arrangement solder joint contacted with through hole forms described MOSFET at least partially.
The method of another kind of wafer-level packaging provided by the invention, include on the wafer of multiple chip one, distribution again technology RDL is utilized to become to be arranged in cover the arrangement solder joint of the insulating medium layer of chip by the weld pad being distributed in chip end face again layout designs, arrangement solder joint comprises first kind arrangement solder joint, comprise the following steps: coating one deck covers the barrier layer of insulating medium layer and the arrangement solder joint being positioned at wafer frontside, and formation is arranged in the opening that barrier layer contacts first kind arrangement solder joint; Arrange to the first kind substrate that solder joint, insulating medium layer and wafer comprise by described opening to etch, until form the through hole running through first kind arrangement solder joint in insulating medium layer, substrate, remove barrier layer afterwards; On described arrangement solder joint, settle solder projection, some solder is filled in described through hole simultaneously; The front of wafer described in plastic packaging, with coated insulating medium layer and the solder projection being positioned at wafer frontside of the first plastic packaging layer; Carry out grinding until the back side of wafer after thinning exposes outside the solder be filled in described through hole in the back side of wafer; The back side of the wafer after thinning covers layer of metal layer; The back side being coated with metal level of the wafer after thinning is cut wafer, form the cutting groove of isolating chip, and cutting groove stops in the first plastic packaging layer; Plastic packaging is carried out to wafer in the back side being coated with metal level of the wafer after thinning, forms the second plastic packaging layer of covered with metal layer, and plastic packaging material is also filled in cutting groove simultaneously; Grind the first plastic packaging layer to be exposed in thinning rear first plastic packaging layer by solder projection; Cut in described cutting groove, chip is separated.
Above-mentioned method, formation described through hole after, also on the inwall of described through hole, deposit isolation liner bed course, and fill metal material by isolation liner bed course and be looped around around through hole substrate region insulation.Above-mentioned method, forming the mode of through hole is dry etching or wet etching or laser ablation.Above-mentioned method, the planar cross-sectional size of the through hole formed is less than the planar dimension of arrangement solder joint.Above-mentioned method, the described first kind contacted with through hole arranges the position of solder joint, is arranged in the insulating medium layer on the substrate non-active device cell region that covers.Above-mentioned method, described chip is rectilinear MOSFET.Above-mentioned method, formed in the process of the through hole of contact first kind arrangement solder joint, the described first kind contacted with through hole arranges the drain electrode that solder joint forms described MOSFET; And in the arrangement solder joint of all non-first kind arrangement solder joints, do not form the arrangement solder joint contacted with through hole at least partially and form the gate electrode of described MOSFET and the arrangement solder joint of source electrode.
The encapsulating structure of a kind of wafer scale provided by the invention, in this encapsulating structure, distribution again technology is utilized to become to be arranged in cover the arrangement solder joint of the top insulating medium layer of chip by the weld pad being distributed in chip end face again layout designs, arrangement solder joint comprises first kind arrangement solder joint, also comprise: the top plastic-sealed body of coated top insulating medium layer and solder projection, wherein said solder projection is placed on arrangement solder joint, and solder projection is exposed in the plastic-sealed body of top; Cover one deck bottom electrode metal layer of chip back; Be formed in the through hole contacting first kind arrangement solder joint in the substrate unit and top insulating medium layer that chip comprises, and the first kind contacted with through hole is arranged solder joint by the metal material of filling in through hole is electrically connected on described bottom electrode metal layer; The bottom plastic-sealed body of coated described chip, the lateral extension portions of bottom plastic-sealed body covers described bottom electrode metal layer, and the sidewall of the sidewall of the sidewall of chip, insulating medium layer, top plastic-sealed body is also covered by the side extensions of the bottom plastic-sealed body vertical with lateral extension portions simultaneously.
The encapsulating structure of above-mentioned wafer scale, the inwall of described through hole is also provided with isolation liner bed course, and the metal material of filling is by isolation liner bed course and the substrate region insulation that is looped around around through hole.The encapsulating structure of above-mentioned wafer scale, in covering in the insulating medium layer in the substrate unit that chip comprises on non-active device cell region, arranging by described distribution again technology the described first kind contacted with through hole and arranging solder joint.The encapsulating structure of above-mentioned wafer scale, described through hole runs through this first kind contacted with through hole further and arranges solder joint; And the planar cross-sectional size of through hole is less than the planar dimension of arrangement solder joint, and the metal material of filling in through hole is the extension of the solder projection be placed on first kind arrangement solder joint.The encapsulating structure of above-mentioned wafer scale, described chip is rectilinear MOSFET.The encapsulating structure of above-mentioned wafer scale, the described first kind contacted with through hole arranges the drain electrode that solder joint forms described MOSFET; And in the arrangement solder joint of all non-first kind arrangement solder joints, do not form gate electrode and source electrode that the arrangement solder joint contacted with through hole forms described MOSFET at least partially.
The method of a kind of wafer-level packaging provided by the invention, include on the wafer of multiple chip one, be formed in the front of wafer protrude from wafer frontside and be electrically connected to the solder projection of chip pad, comprise the following steps: the front of wafer described in plastic packaging, with the front of the first plastic packaging layer coated silicon wafer and solder projection; Grind in the back side of wafer; The back side of the wafer after thinning is cut wafer, form the cutting groove of isolating chip, and cutting groove stops in the first plastic packaging layer; Plastic packaging is carried out to wafer in the back side of the wafer after thinning, formed coated thinning after the second plastic packaging layer at the back side of wafer, plastic packaging material is also filled in cutting groove simultaneously; Grind the first plastic packaging layer to be exposed in the first plastic packaging layer of solder projection after thinning; Cut in described cutting groove, chip is separated.
Above-mentioned method, after completing the grinding back surface of wafer, be also included in thinning after the back side of wafer cover the step of layer of metal layer; And in the process of cutting groove forming isolating chip, the back side being coated with metal level of the wafer after thinning is cut wafer; And formed coated thinning after wafer the back side the second plastic packaging layer process in, described second plastic packaging layer also simultaneously covered with metal layer.Above-mentioned method, described chip is the IC of planar structure, and its all signal input output ends is all arranged on the side of chip end face.Above-mentioned method, described chip is two MOSFET of rectilinear common drain; And the drain electrode of a MOSFET and the drain electrode of another MOSFET are electrically connected by described metal level in two MOSFET, and arrange source electrode and the gate electrode that solder joint forms any one MOSFET in two MOSFET respectively at least partially.Above-mentioned method, at least comprises multiple diode in described chip, and described diode electrode terminal is electrically connected on described metal level jointly; And arrange another electrode terminal that solder joint forms described diode at least partially.
The method of a kind of wafer-level packaging provided by the invention, include on the wafer of multiple chip one, utilize distribution again technology RDL to become to be arranged in cover the arrangement solder joint of the insulating medium layer of chip by the weld pad being distributed in chip end face again layout designs, comprise the following steps: on described arrangement solder joint, settle solder projection; The front of wafer described in plastic packaging, with coated insulating medium layer and the solder projection being positioned at wafer frontside of the first plastic packaging layer; Grind in the back side of wafer; The back side of the wafer after thinning is cut wafer, form the cutting groove of isolating chip, and cutting groove stops in the first plastic packaging layer; Plastic packaging is carried out to wafer in the back side of the wafer after thinning, formed coated thinning after the second plastic packaging layer at the back side of wafer, plastic packaging material is also filled in cutting groove simultaneously; Grind the first plastic packaging layer to be exposed in the first plastic packaging layer by solder projection; Cut in described cutting groove, chip is separated.
Above-mentioned method, after completing the grinding back surface of wafer, be also included in thinning after the back side of wafer cover the step of layer of metal layer; And in the process of cutting groove forming isolating chip, the back side being coated with metal level of the wafer after thinning is cut wafer; And formed coated thinning after wafer the back side the second plastic packaging layer process in, described second plastic packaging layer also simultaneously covered with metal layer.
The encapsulating structure of a kind of wafer scale provided by the invention, in this encapsulating structure, the end face of chip be formed protrude from chip end face and be electrically connected to the solder projection of chip pad, also comprise: the top plastic-sealed body being coated on chip end face, and solder projection is exposed in the plastic-sealed body of top; The bottom plastic-sealed body of coated described chip, the lateral extension portions of bottom plastic-sealed body covers the bottom surface of chip, and the sidewall of the sidewall of chip, top plastic-sealed body is also covered by the side extensions of the bottom plastic-sealed body vertical with lateral extension portions simultaneously.
The encapsulating structure of above-mentioned wafer scale, also comprises one deck bottom electrode metal layer covering die bottom surface, also covers bottom electrode metal layer while the back side of the lateral extension portions covering chip of described second plastic packaging layer.The encapsulating structure of above-mentioned wafer scale, described chip is the IC of planar structure, and its all signal input output ends is all arranged on the side of chip end face.The encapsulating structure of above-mentioned wafer scale, described chip is two MOSFET of rectilinear common drain; And the drain electrode of a MOSFET and the drain electrode of another MOSFET are electrically connected by described metal level in two MOSFET, and arrange source electrode and the gate electrode that solder joint forms any one MOSFET in two MOSFET respectively at least partially.The encapsulating structure of above-mentioned wafer scale, at least comprises multiple diode in described chip, and described diode electrode terminal is electrically connected on described metal level jointly; And arrange another electrode terminal that solder joint forms described diode at least partially.
The encapsulating structure of a kind of wafer scale provided by the invention, in this encapsulating structure, distribution again technology is utilized to become to be arranged in cover the arrangement solder joint of the top insulating medium layer of chip by the weld pad being distributed in chip end face again layout designs, also comprise: the top plastic-sealed body of coated top insulating medium layer and solder projection, wherein said solder projection is placed on arrangement solder joint, and solder projection is exposed in the plastic-sealed body of top; The bottom plastic-sealed body of coated described chip, the lateral extension portions of bottom plastic-sealed body covers the bottom surface of chip, and the sidewall of the sidewall of chip, top insulating medium layer, the sidewall of top plastic-sealed body are also covered by the side extensions of the bottom plastic-sealed body vertical with lateral extension portions simultaneously.
The encapsulating structure of above-mentioned wafer scale, also comprises one deck bottom electrode metal layer covering die bottom surface, also covers bottom electrode metal layer while the bottom surface of the lateral extension portions covering chip of described bottom plastic-sealed body.
The method of a kind of wafer-level packaging provided by the invention, include on the wafer of multiple chip one, be formed in the front of wafer protrude from wafer frontside and be electrically connected to the solder projection of chip pad, comprise the following steps: cut in the front of wafer, formed and be positioned at the cutting groove for isolating chip of wafer frontside side, and this cutting groove stops in the substrate that wafer comprises; Carry out plastic packaging in the front of wafer, form the first plastic packaging layer in the front of coated silicon wafer, plastic packaging material is also filled in the cutting groove being arranged in wafer frontside side simultaneously; Grind in the back side of wafer; The back side of the wafer after thinning is cut wafer, formed be positioned at thinning after the cutting groove for isolating chip of side, the back side of wafer, and be arranged in thinning after the cutting groove of wafer rear side stop in the substrate and contact with the plastic packaging material being filled in the cutting groove being positioned at wafer frontside side further; Plastic packaging is carried out to wafer in the back side of the wafer after thinning, formed coated thinning after the second plastic packaging layer at the back side of wafer, simultaneously plastic packaging material be also filled in be arranged in thinning after the cutting groove of wafer rear side; Grind the first plastic packaging layer to be exposed in the first plastic packaging layer of solder projection after thinning; Simultaneously in be arranged in wafer frontside side cutting groove, be arranged in thinning after the cutting groove of wafer rear side cut, chip is separated.
Above-mentioned method, is characterized in that, after the back side of wafer completes grinding, be also included in thinning after the back side of wafer etch, and cover the step of layer of metal layer to the back side of the wafer after thinning; And formed be arranged in thinning after the process of the cutting groove for isolating chip of wafer rear side, the back side being coated with metal level of the wafer after thinning is cut wafer; And formed coated thinning after wafer the back side the second plastic packaging layer process in, described second plastic packaging layer also simultaneously coated described metal level.
The method of a kind of wafer-level packaging provided by the invention, include on the wafer of multiple chip one, distribution again technology RDL is utilized to become to be arranged in cover the arrangement solder joint of the insulating medium layer of chip by the weld pad being distributed in chip end face again layout designs, arrangement solder joint comprises first kind arrangement solder joint, comprises the following steps: on described arrangement solder joint, settle solder projection; Cut in the front of wafer, formed and be positioned at the cutting groove for isolating chip of wafer frontside side, and this cutting groove stops in the substrate that wafer comprises; The front of wafer described in plastic packaging, with coated insulating medium layer and the solder projection being positioned at wafer frontside of the first plastic packaging layer, plastic packaging material is also filled in the cutting groove being formed and be arranged in wafer frontside side simultaneously; Grind in the back side of wafer; The back side of the wafer after thinning is cut wafer, formed be positioned at thinning after the cutting groove for isolating chip of wafer rear side, and be arranged in thinning after the cutting groove of wafer rear side stop in the substrate and contact with the plastic packaging material being filled in the cutting groove being positioned at wafer frontside side further; Plastic packaging is carried out to wafer in the back side of the wafer after thinning, formed coated thinning after the second plastic packaging layer at the back side of wafer, simultaneously plastic packaging material be also filled in be arranged in thinning after the cutting groove of wafer rear side; Grind the first plastic packaging layer to be exposed in the first plastic packaging layer of solder projection after thinning; Simultaneously in be arranged in wafer frontside side cutting groove, be arranged in thinning after the cutting groove of wafer rear side cut, chip is separated.
Above-mentioned method, after the back side of wafer completes grinding, be also included in thinning after the back side of wafer etch, and cover the step of layer of metal layer to the back side of the wafer after thinning; And formed be arranged in thinning after the process of the cutting groove for isolating chip of wafer rear side, the back side being coated with metal level of the wafer after thinning is cut wafer; And formed coated thinning after wafer the back side the second plastic packaging layer process in, described second plastic packaging layer also simultaneously coated described metal level.Above-mentioned method, before the back side of the wafer after covering layer of metal layer is extremely thinning, further comprising the steps of:
Backside coating one deck barrier layer of the wafer after thinning, and form the opening being arranged in barrier layer; By be opened on thinning after the back side of wafer etch, form the through hole of contact first kind arrangement solder joint in the substrate comprised in wafer and insulating medium layer, and remove barrier layer; Fill metal material in described through hole, and the layer of metal layer that the back side of wafer after thinning covers is electrically connected to by the metal material be filled in described through hole the first kind contacted with through hole arranges on solder joint.Above-mentioned method, the described first kind contacted with through hole arranges the position of solder joint, is arranged in the insulating medium layer on the substrate non-active device cell region that covers.
Said method, settle solder projection on arrangement solder joint before, further comprising the steps of: coating one deck is coated is positioned at the insulating medium layer of wafer frontside and the barrier layer of arrangement solder joint, and formation is arranged in the opening that barrier layer contacts first kind arrangement solder joint; By described opening, described first kind arrangement solder joint and insulating medium layer, substrate are etched, in substrate and insulating medium layer, form the through hole running through this first kind arrangement solder joint, and remove barrier layer; While settling solder projection afterwards on arrangement solder joint, some solder is also filled in described through hole in the lump.Said method, carry out in the back side of wafer in process of lapping, the back side of the wafer after thinning exposes outside filling solder in through-holes, and the layer of metal layer that the back side of wafer afterwards after thinning covers is electrically connected at by the solder of filling in through-holes the first kind contacted with through hole arranges on solder joint.
The encapsulating structure of a kind of wafer scale provided by the invention, in the structure shown here, the end face of chip be formed protrude from chip end face and be electrically connected to the solder projection of chip pad, comprise: the top plastic-sealed body of coating chip, the lateral extension portions of top plastic-sealed body covers the front of chip, the partial sidewall of chip is also covered by the side extensions of the top plastic-sealed body vertical with the lateral extension portions of top plastic-sealed body simultaneously, and solder projection is exposed in the plastic-sealed body of top; The bottom plastic-sealed body of coating chip, the lateral extension portions of bottom plastic-sealed body covers the bottom surface of chip, other a part of sidewall of chip is also covered by the side extensions of the bottom plastic-sealed body vertical with the lateral extension portions of bottom plastic-sealed body simultaneously, and the side extensions of top plastic-sealed body and the side extensions of bottom plastic-sealed body contact with each other with by sealing seamless for chip.
The encapsulating structure of above-mentioned wafer scale, also comprises one deck bottom electrode metal layer covering die bottom surface, also covers bottom electrode metal layer while the bottom surface of the lateral extension portions covering chip of described bottom plastic-sealed body.The encapsulating structure of above-mentioned wafer scale, described chip is the IC of planar structure, and its all signal input output ends is all arranged on the side of chip end face.The encapsulating structure of above-mentioned wafer scale, described chip is two MOSFET of rectilinear common drain; And the drain electrode of a MOSFET and the drain electrode of another MOSFET are electrically connected by described bottom electrode metal layer in two MOSFET, and arrange source electrode and the gate electrode that solder joint forms any one MOSFET in two MOSFET respectively at least partially.The encapsulating structure of above-mentioned wafer scale, at least comprises multiple diode in described chip, and described diode electrode terminal is electrically connected on described bottom electrode metal layer jointly; And arrange another electrode terminal that solder joint forms described diode at least partially.
The invention provides a kind of encapsulating structure of wafer scale, in this encapsulating structure, distribution again technology is utilized to become to be arranged in cover the arrangement solder joint of the top insulating medium layer of chip by the weld pad being distributed in chip end face again layout designs, arrangement solder joint comprises first kind arrangement solder joint, it is characterized in that, comprise: the top plastic-sealed body of coating chip, the lateral extension portions of top plastic-sealed body covers on the insulating medium layer of top, the side extensions of the top plastic-sealed body vertical with the lateral extension portions of top plastic-sealed body is simultaneously also by the sidewall of top insulating medium layer, the partial sidewall of chip is covered, and solder projection is exposed in the plastic-sealed body of top, the bottom plastic-sealed body of coating chip, the lateral extension portions of bottom plastic-sealed body covers the bottom surface of chip, other a part of sidewall of chip is also covered by the side extensions of the bottom plastic-sealed body vertical with the lateral extension portions of bottom plastic-sealed body simultaneously, and the side extensions of top plastic-sealed body and the side extensions of bottom plastic-sealed body contact with each other with by sealing seamless for chip.
The encapsulating structure of above-mentioned wafer scale, is also included in one deck bottom electrode metal layer that die bottom surface covers, and also covers bottom electrode metal layer while the bottom surface of the lateral extension portions covering chip of described bottom plastic-sealed body.The encapsulating structure of above-mentioned wafer scale, also comprise: be formed in the through hole contacting first kind arrangement solder joint in the substrate unit and top insulating medium layer that chip comprises, and the first kind contacted with through hole is arranged solder joint by the metal material of filling in through hole is electrically connected on described bottom electrode metal layer.The encapsulating structure of above-mentioned wafer scale, described through hole runs through this first kind contacted with through hole further and arranges solder joint; And the planar cross-sectional size of through hole is less than the planar dimension of arrangement solder joint, and the metal material of filling in through hole is the extension of the solder projection be placed on first kind arrangement solder joint.The encapsulating structure of above-mentioned wafer scale, wherein, described chip is rectilinear MOSFET.
Those skilled in the art reads the detailed description of following preferred embodiment, and with reference to after accompanying drawing, the advantage of these and other aspects of the present invention undoubtedly will be apparent.
With reference to appended accompanying drawing, to describe embodiments of the invention more fully.But, appended accompanying drawing only for illustration of and elaboration, do not form limitation of the scope of the invention.
Figure 1A-1B is original design diagram of the weld pad of chip end face.
Fig. 1 C-1D is the schematic diagram carrying out original for chip end face weld pad to become from new layout designs arrangement solder joint.
Fig. 1 E, 1F are at original weld pad with at the schematic diagram carrying out planting ball from the arrangement solder joint of new layout respectively.
Fig. 2 A-2M is in a kind of execution mode, a part for chip arrangement solder joint is connected to the preparation flow of the electrode of chip back by the filling metal material in through hole.
Fig. 3 A-3J is in another kind of execution mode, a part for chip arrangement solder joint is connected to the preparation flow of the electrode of chip back by the filling metal material in through hole.
Fig. 4 A-4E is in a kind of execution mode, at the back of the body surface forming electrode of chip and by the preparation flow of chip package after RDL technical finesse.
Fig. 5 A-5F is in a kind of execution mode, the chip without RDL technical finesse back of the body surface forming electrode and by the preparation flow of chip package.
Fig. 6 A-6E is in a kind of execution mode, does not form electrode and by the preparation flow of chip package after RDL technical finesse at the back side of chip.
Fig. 7 A-7E is in a kind of execution mode, does not form electrode and by the preparation flow of chip package at the back side of the chip without RDL technical finesse.
Fig. 8 A-8I is in a kind of execution mode, carries out cutting plastic packaging in the front of the wafer without RDL technical finesse, then the back side of wafer after thinning is carried out plastic packaging and cuts, by the preparation flow that chip is separated from wafer.
Fig. 9 A-9E is in a kind of execution mode, carries out cutting plastic packaging, the plastic packaging material in thinned wafer front in the front of the wafer without RDL technical finesse, and the back side plastic packaging of the wafer after thinning also cuts, by chip from the preparation flow be separated.
Figure 10 A-10I is in a kind of execution mode, carries out cutting and the back side of the wafer of plastic packaging again after thinning is carried out plastic packaging and cuts, by the preparation flow that chip is separated from wafer after RDL technical finesse in the front of wafer.
Embodiment
Shown in Figure 1A, in the schematic top plan view of chip 100 end face, originally the edge designs along chip 100 end face surrounding has the multiple weld pads (BondPad) 101 connecting chip 100 internal circuit, weld pad 101 is generally aluminium pad (Peripheralpads) for being formed in electrical contact with the external world, such as directly carry out the bottom metal layers UBM of wire bonding or first depositing Ti/Cu/Ni etc. thereon thereon, carry out again planting ball, it can be the signal I/O contact terminal (I/OPad) of chip 100 internal circuit, or the interface etc. of Power or Ground.Figure 1B describes the schematic cross-section of weld pad 101 set on the end face of the chip 100 of segment thickness.
Shown in Fig. 1 C, utilize distribution again technology RDL (RedistributionLayer), existing for the chip 100 end face weld pad 101 being arranged in surrounding is redesigned into the arrangement solder joint 104 of any rational position, arrangement solder joint 104 can be redistributed into the periphery of chip 100 end face, both sides or any side, or even forms matrix arrangement.For the ease of understanding, Fig. 1 C illustrates weld pad 101 and completes distribution again and form the schematic top plan view after arranging solder joint 104, Fig. 1 D is then weld pad 101 through RDL process from the schematic cross-section being arranged in insulating medium layer 102 after new layout, insulating medium layer 102 covers on the end face of chip 100, insulating medium layer 102 is generally polyimide material (Polyimide), arrangement solder joint 104 can by be created on interconnection line (Trace) 103 in insulating medium layer 102 and corresponding being electrically connected with weld pad 101 simultaneously, simultaneously arrange solder joint 104 also can select not to be connected with any weld pad 101 after RDL and individualism for future use.Interconnection line 103 is usually with bending path, so the interconnection line 103 concrete annexation with arrangement solder joint 104, weld pad 101 is not depicted by Fig. 1 D, but now the weld pad 101 that is connected with arrangement solder joint 104 of a part and the external world carry out Signal transmissions and then depend on the arrangement solder joint 104 be attached thereto.
Shown in Figure 1B and 1E, solder projection (Solderbump) 105 is directly welded on the original weld pad 101 of chip 100 end face; And in Fig. 1 D and 1F, solder projection 105 is but be welded on arrangement solder joint 104.
See the method for a kind of wafer-level packaging of Fig. 2 A-2M, on the wafer 200 including multiple chip 200 ' shown in Fig. 2 A, multiple chips 200 ' mutually each other casting link together and be jointly formed in silicon substrate (or silicon substrate) 200A that wafer 200 comprises, adjacent chip is by the scribe line (ScribeLine of wafer frontside, not shown) mutually define border to each other, the weld pad 201 of chip 200 ' is positioned at the side in wafer 200 front.Distribution again technology is utilized to become to be arranged in cover the arrangement solder joint 204 of the insulating medium layer 202 of wafer 200 (simultaneously covering chip 200 ') by the weld pad 201 being distributed in chip 200 ' end face again layout designs, as shown in Figure 2 B.And carry out planting ball arrangement solder projection 205 on arrangement solder joint 204, as shown in Figure 2 C.Plastic package process is carried out afterwards, with the first plastic packaging layer 206 coated solder projection 205 and the insulating medium layer 202 covering wafer 200 front, as shown in Figure 2 D in the front of wafer 200.Carry out grinding the thickness with thinned wafer 200 at the back side of wafer 200 afterwards, such as, carry out cmp CMP, as shown in Figure 2 E, the segment thickness (as D1) at wafer 200 back side is polished, and namely the thickness of substrate 200A obtains thinning.Apply the back side of one deck barrier layer 207 to the wafer 200 after thinning again, as shown in Figure 2 F, and form the opening 207 ' being arranged in barrier layer 207 patterning, there are multiple choices on barrier layer 207, as photoresistance or SiN or SiO2, mainly in order to form the opening 207 ' aiming at part arrangement solder joint 204 (first kind arrangement solder joint 204a as in Fig. 2 G) in vertical direction in barrier layer 207, to utilize silicon through hole technology (TSV, ThroughSiliconVia), substrate 200A and insulating medium layer 202 to be etched by the back side of the wafer 200 of opening 207 ' after thinning using barrier layer 207 as hard mask, make to be etched away in the silicon substrate 200A region of the middle exposure of opening 207 ', and etching lasts till and to be also etched away at the insulating medium layer 202 of the middle exposure of opening 207 ', until etching stopping is on first kind arrangement solder joint 204a, the final through hole 208 forming contact first kind arrangement solder joint 204a in substrate 200A and insulating medium layer 202.First kind arrangement solder joint 204a is the part in all arrangement solder joints 204 in fact, just first kind arrangement solder joint 204a is initial is not connected and individualism with any weld pad 201 of chip 200 ', first kind arrangement solder joint 204a is used for being connected with some electrodes or signal terminal of being formed in chip 200 ' bottom surface in subsequent step, thus these electrodes are guided to the side in chip 200 ' front.Remove barrier layer 207 after completing the etching of through hole 208, wherein, through hole 208 be formed with various ways, such as dry etching or wet etching or laser ablation; Usually after formation through hole 208, also need the isolation liner bed course depositing layer oxide film on the inwall of through hole 208, be filled in so that follow-up metal material in through hole 208 can by isolation liner bed course be looped around around through hole 208 silicon substrate area, insulate in the substrate 200A region namely surrounding through hole 208.In order to prevent through hole 208, oversize to cause the first kind to arrange solder joint 204a unsettled and cannot obtain the physical support of insulating medium layer 202 in through hole 208, the opening size size of opening 207 ' can be controlled, and planar cross-sectional (cross section) size controlling through hole 208 further makes it be less than the planar dimension size of arrangement solder joint 204, thus the first kind is avoided to arrange coming off of solder joint 204a.
Shown in Fig. 2 H-2I, fill metal material 208 ' in through hole 208, and the back side of wafer 200 after thinning covers layer of metal layer 209, the metal material 208 ' now in metal level 209 contact through hole 208.Afterwards in being coated with metal level 209 and the back side of wafer 200 after being thinning, wafer 200 is cut, form the cutting groove 210 of isolation adjacent chips 200 ', now cutter touch certain thickness first plastic packaging layer 206, cutting groove 210 is caused to stop in the first plastic packaging layer 206, also namely multiple chips 200 ' now relies on the first plastic packaging layer 206 and interconnects, metal level 209 is cut into the bottom electrode metal layer 209 ' being positioned at every chips 200 ' bottom surface simultaneously, insulating medium layer 202 is also cut into the top insulating medium layer 202 ' being positioned at every chips 200 ' end face, as shown in fig. 2j.Be coated with metal level 209 and the back side of wafer 200 after being thinning again, plastic packaging is carried out to wafer 200, although now metal level 209 is cut into multiple bottom electrode metal layer 209 ' being positioned at every chips 200 ' bottom surface, but all bottom electrode metal layers 209 ' still form an overall metal level 209 jointly, thus after completing plastic packaging, form the second plastic packaging layer 211 of covered with metal layer 209, specifically, the coated bottom electrode metal layer 209 ' being positioned at every chips 200 ' bottom surface of second plastic packaging layer 211, meanwhile, the part plastic packaging material that second plastic packaging layer 211 comprises also is filled in cutting groove 210, as shown in figure 2k.
Shown in Fig. 2 L-2M, the first plastic packaging layer 206 with thinning certain thickness (as D2) is ground to the first plastic packaging layer 206, so that solder projection 205 is exposed in the first plastic packaging layer 206, as solder projection 205 expose to thinning after the first plastic packaging layer 206 '.Cut in cutting groove 210 afterwards, namely cutting mouth 212 shown in Fig. 2 M is cutting vestige, and form the width of the cutter that cutting mouth 212 utilizes, be less than to form the width of cutter that cutting groove 210 utilizes, thus chip 200 ' carries out from wafer 200 the encapsulating structure 200 " A that separates to obtain multiple wafer scale the most at last, the first plastic packaging layer 206 ' after thinning forms the top plastic-sealed body 206 covering top insulating medium layer 202 ' in this cutting process ", second plastic packaging layer 211 forms the bottom plastic-sealed body 211 ' covering bottom electrode metal layer 209 ' in this cutting process, and the lateral extension portions 211 ' a of bottom plastic-sealed body 211 ' covers bottom electrode metal layer 209 ', side extensions 211 ' the b vertical with lateral extension portions 211 ' a also covers the sidewall of chip 200 ', the sidewall of top insulating medium layer 202 ', top plastic-sealed body 206 " sidewall, wherein, side extensions 211 ' the b that bottom plastic-sealed body 211 ' comprises is that a part of plastic packaging material that the second plastic packaging layer 211 is filled in cutting groove 210 is formed through the cutting process shown in Fig. 2 M in fact.
Due in the preparation process shown in Fig. 2 J-2M, the substrate 200A that wafer 200 comprises is cut into the substrate unit 200 ' A that chip 200 ' comprises, so for the encapsulating structure 200 of the wafer scale shown in Fig. 2 M, " for A; in the silicon substrate unit 200 ' A that chip 200 ' comprises, the first kind contacted with through hole 208 is arranged solder joint 204a and is electrically connected on bottom electrode metal layer 209 ' by the metal material 208 ' of filling in the through hole 208 of contact first kind arrangement solder joint 204a.In an Alternate embodiments, chip 200 ' is the MOSFET of rectilinear (Verticalstructure), and also namely its principal current flow to bottom from top device, or vice versa.The drain region of chip 200 ' is formed in the side near chip 200 ' bottom surface in substrate unit 200 ' A usually, in order to strengthen the ohmic contact of bottom electrode metal layer 209 ' and chip 200 ' drain region, can depositing metal layers 209 to the wafer 200 after thinning the back side before, the ion that the back side heavy doping implantation of the wafer 200 after thinning is identical with drain region doping type.Because the drain region of bottom electrode metal layer 209 ' contact in the substrate unit 200 ' A of side, chip 200 ' bottom surface forms drain electrode, so the first kind contacted with through hole 208 arranges solder joint 204a owing to being electrically connected with the drain electrode of MOSFET thus forming the drain electrode of rectilinear MOSFET, and in all arrangement solder joints 204, except first kind arrangement solder joint 204a, do not form in the arrangement solder joint 204 contacted with through hole 208, have at least on part arrangement solder joint 204 grid that is connected to the MOSFET being positioned at chip 200 ' end face side and source electrode, and form gate electrode and the source electrode of rectilinear MOSFET respectively.As can be seen here, for the drain electrode of the chip 200 ' of rectilinear MOSFET is produced on the bottom electrode metal layer 209 ' of side, chip 200 ' bottom surface originally, but the first kind arranged solder joint 204a with bottom electrode metal layer 209 ' forms electrical contact by the metal material 208 ' of filling in through hole 208, thus the end, is leaked the vertical structure device in source, top source, draining all is arranged on the side of chip 200 ' end face.Equally, if need the source of the vertical structure device leaked on top, source, the end, drain electrode is all arranged on the side of chip 200 ' end face, as long as selecting first kind arrangement solder joint 204a that through hole 208 contacts when forming through hole 208 is source electrode bottom contact MOSFET.It is worth mentioning that, in RDL preparation flow, the first kind contacted with through hole 208 arranges the position that solder joint 204a is formed, be be arranged in the insulating medium layer 202 on the silicon substrate 200A non-active device cell region that covers, time such etched substrate 200A forms through hole 208, be just unlikely to the integrated circuit unit destroying chip 200 '.Specifically, the formation of any one through hole 208, must ensure that through hole 208 is formed in the silicon substrate area not participating in the circuit structure forming chip 200 '.
For the ease of understanding, make an explanation with Fig. 1 F, the first kind contacted with through hole 108 arranges the position that solder joint 104 is formed, be be arranged in the insulating medium layer 102 on the substrate unit 100 ' A non-active device cell region (as Zone R territory) that covers, substrate unit 100 ' A comes from the cutting and separating to the substrate that the wafer at chip 100 place comprises.In the substrate unit 100 ' A that a part of region 102 ' that in figure, insulating medium layer 102 comprises covers on non-active device cell region, first kind arrangement solder joint 104 is formed in this part region 102 '.Substrate unit 100 ' A comprise within the scope of the Zone R territory of receiving opening 108, in its transverse area (X-axis) and longitudinal region (Y-axis) and vertical area (Z axis), preparation does not comprise any efficient circuit unit of chip 100 in other words, meanwhile, the planar dimension of first kind arrangement solder joint 104 chooses the planar dimension (transverse area and longitudinal region) being not more than Zone R territory scope.
See Fig. 3 A-3J, the present invention is also provided in the method for the another kind of wafer-level packaging of Fig. 2 A-2M step being carried out localized variation, wafer 200 shown in Fig. 3 A is on the wafer 200 shown in Fig. 2 B, be coated with the barrier layer 213 that one deck covers the insulating medium layer 202 and arrangement solder joint 204 being positioned at side, wafer 200 front, form the opening 213 ' being arranged in barrier layer 213 afterwards, and opening 213 ' contacts the first kind arrangement solder joint 204a in arrangement solder joint 204, the formation of opening 213 ' can by carrying out photoetching to the barrier layer 213 of photoresistance and so on, thus selected opening 213 ' aims at first kind arrangement solder joint 204a in vertical direction.By opening 213 ', the silicon substrate 200A that this first kind arrangement solder joint 204a and insulating medium layer 202, wafer 200 comprise is etched afterwards.Wherein, must ensure that the planar dimension of opening 213 ' is less than the planar dimension of first kind arrangement solder joint 204a, to ensure that first kind arrangement solder joint 204a is only that the region be exposed in opening 213 ' is etched away, region that not first kind arrangement solder joint 204a is all is etched away completely, consequently, the first kind arrangement solder joint 204a region be exposed in opening 213 ' is first etched away thus exposes insulating medium layer 202 at opening 213 ', continue to etch the insulating medium layer 202 of the middle exposure of opening 213 ', until expose silicon substrate 200A at opening 213 ', and continue to etch the silicon substrate 200A of the middle exposure of opening 213 ', and etching stopping is in silicon substrate 200A, final at insulating medium layer 202, the through hole 214 running through this first kind arrangement solder joint 204a is formed in the silicon substrate 200A of segment thickness, as shown in Figure 3 B, remove barrier layer 213 afterwards.Usually after formation through hole 214, also to deposit the isolation liner bed course of layer oxide film on the inwall of through hole 214, so as follow-up be filled in metal material in through hole 214 by isolation liner bed course be looped around around through hole 214 silicon substrate area insulate.
Shown in Fig. 3 C, the arrangement solder joint 204 comprising first kind arrangement solder joint 204a settles solder projection 205, in this process, some solder 214 ' flows into simultaneously and is filled in through hole 214, this some solder 214 ' is cast with the first kind solder projection 205 arranged on solder joint 204a and is linked together, and visible solder 214 ' is placed in the extension that the first kind contacted with through hole 214 arranges the solder projection 205 on solder joint 204a.After completing above-mentioned steps, carry out plastic packaging in the front of wafer 200, with the first plastic packaging layer 206 coated solder projection 205 and the insulating medium layer 202 covering wafer 200 front, as shown in Figure 3 D.And carry out CMP grinding in the back side of wafer 200 until the back side of wafer 200 after thinning exposes outside the solder 214 ' be filled in through hole 214, as shown in FIGURE 3 E, the segment thickness (as D3) of wafer 200 is polished.The back side of the wafer 200 again after thinning covers layer of metal layer 209, and as chemical vapour deposition (CVD), shown in Fig. 3 F, now solder 214 ' and metal level 209 keep in electrical contact.Afterwards in being coated with metal level 209 and the back side of wafer 200 after being thinning, wafer 200 is cut, form the cutting groove 210 of isolation adjacent chips 200 ', cutter cut the first plastic packaging layer 206 in thickness upper part, now cutting groove 210 stops in the first plastic packaging layer 206, as shown in Figure 3 G.Multiple chips 200 ' now relies on the first plastic packaging layer 206 and interconnects, metal level 209 is cut into the bottom electrode metal layer 209 ' being positioned at every chips 200 ' bottom surface, and insulating medium layer 202 is also cut into the top insulating medium layer 202 ' being positioned at every chips 200 ' end face.Be coated with metal level 209 and the back side of wafer 200 after being thinning again, plastic packaging is carried out to wafer 200, now metal level 209 is cut into multiple bottom electrode metal layer 209 ' being positioned at every chips 200 ' bottom surface, but bottom electrode metal layer 209 ' still forms the metal level 209 of one deck globality jointly, thus the part plastic packaging material that the second plastic packaging layer 211, the second plastic packaging layer 211 forming covered with metal layer 209 after completing plastic packaging comprises also is filled in cutting groove 210 simultaneously.Afterwards as shown in fig. 31, grind the first plastic packaging layer 206 to be exposed in the first plastic packaging layer 206 ' of solder projection 205 after thinning, the segment thickness (as D4) of the first plastic packaging layer 206 is polished.See Fig. 3 J, finally cut in cutting groove 210, to be separated by chip 200 ', obtain the encapsulating structure 200 " B of the wafer scale shown in Fig. 3 J.In one embodiment, chip 200 ' with the device shown in Fig. 2 M and indistinction, is rectilinear MOSFET.The encapsulating structure 200 of wafer scale " in B; in the etching process that through hole 214 is formed; the result produced is that through hole 214 runs through the first kind contacted with through hole 214 and arrange solder joint 204a; and solder 214 ' with arrange in the first kind solder projection 205 that solder joint 204a settles and generate simultaneously, and the metal material of filling in through hole 214 is the extension arranging the solder projection 205 that solder joint 204a settles in the first kind.
See Fig. 4 A-4E, the wafer 200 of the present invention after to be also provided in shown in Fig. 2 E thinning carries out the method for the another kind of wafer-level packaging of other processing steps, it should be noted that, in this embodiment, with the arrangement solder joint 104 of RDL design exemplarily, but it is noted that, it is not necessary condition that the weld pad 101 of chip 100 end face of Figure 1A is redesigned into arrangement solder joint 104.
Shown in Fig. 4 A, carry out plastic packaging in the side in wafer 200 front, also cover insulating medium layer 202 with the front of the first plastic packaging layer 206 coated silicon wafer 200 and solder projection 205, first plastic packaging layer 206 simultaneously, carry out CMP grinding in the back side of wafer 200, and after the grinding back surface completing wafer 200, be also included in thinning after the back side of wafer 200 cover the step of layer of metal layer 209, afterwards in being coated with metal level 209 and the back side of wafer 200 after being thinning, wafer 200 is cut, form the cutting groove 210 of isolation adjacent chips 200 ', first plastic packaging layer 206 of segment thickness is cut to form the degree of depth that cutting groove 210 is arranged in the first plastic packaging layer 206, now cutting groove 210 stops in the first plastic packaging layer 206, namely also multiple chips 200 ' now relies on the first plastic packaging layer 206 and mutually casts and link together, metal level 209 is cut into the bottom electrode metal layer 209 ' covering every chips 200 ' bottom surface simultaneously, insulating medium layer 202 is also cut into the top insulating medium layer 202 ' covering every chips 200 ' end face, as shown in Figure 4 B.Be coated with metal level 209 and the back side of wafer 200 after being thinning again, plastic packaging is carried out to wafer 200, form the second plastic packaging layer 211 of covered with metal layer 209 after completing plastic packaging, the part plastic packaging material that the second plastic packaging layer 211 comprises simultaneously is also filled in cutting groove 210, as shown in Figure 4 C.Grind again the first plastic packaging layer 206 obtain thinning after the first plastic packaging layer 206 ', and to be exposed in the first plastic packaging layer 206 ' of solder projection 205 after thinning, as shown in Figure 4 D.Cut in cutting groove 210, chip 200 ' is separated, obtain the encapsulating structure 200 of the wafer scale shown in Fig. 4 E " C, the first plastic packaging layer 206 ' after thinning forms the top plastic-sealed body 206 covering top insulating medium layer 202 ' in this cutting process ".In this embodiment, the arrangement solder joint 204 of unnecessary more selected chip 200 ' end faces makes it be filled with the through hole of metal material by any and be connected to bottom electrode metal layer 209 ', so, in the type of this type of chip 200 ', carry out the arrangement solder joint 204 of Signal transmissions all in the side of its end face with the external world, the side of its bottom surface does not then need the signal terminal guiding to 200 ' end face side.In an embodiment, two MOSFET (CommonDrainMOSFET) that chip 200 ' is rectilinear common drain, in two MOSFET, the drain electrode of a MOSFET and the drain electrode of another MOSFET are electrically connected by bottom electrode metal layer 209 ', and arrange at least partially on source electrode and gate electrode that solder joint 204 is connected to any one MOSFET in two MOSFET, and form source electrode and the gate electrode of any one MOSFET in two MOSFET.In another embodiment, multiple diode be integrated in substrate 200A is at least comprised in chip 200 ', and diode electrode terminal is jointly electrically connected on bottom electrode metal layer 209 ' and forms parallel connection, arrange another electrode terminal that solder joint 204 just constitutes diode respectively so at least partially, and be all positioned at the side in chip 200 ' front.Encapsulating structure 200 " in C, top insulating medium layer 202 ' comes from the cutting of insulating medium layer 202, utilize distribution again technology to become to be arranged in cover the arrangement solder joint 204 of the top insulating medium layer 202 ' of chip by the weld pad 201 being distributed in chip 200 ' end face again layout designs, comprise thinning after the first plastic packaging layer 206 ' in cutting process, forms the top plastic-sealed body 206 of covering top insulating medium layer 202 ' ", second plastic packaging layer 211 forms the bottom plastic-sealed body 211 ' covering bottom electrode metal layer 209 ' in cutting process, and the lateral extension portions 211 ' a of bottom plastic-sealed body 211 ' covers bottom electrode metal layer 209 ', side extensions 211 ' the b vertical with lateral extension portions 211 ' a also covers the sidewall of chip 200 ', the sidewall of top insulating medium layer 202 ', top plastic-sealed body 206 " sidewall, wherein, the side extensions 211 ' b that bottom plastic-sealed body 211 ' comprises is that a part of plastic packaging material that the second plastic packaging layer 211 is filled in cutting groove 210 is formed through the cutting process shown in Fig. 4 E in fact, solder projection 205 is in top plastic-sealed body 206 " in exposed.
In fact, directly can also settle soldered ball on the weld pad 101 of chip 100 end face of Figure 1A and carry out the flow process of Fig. 4 A-4E, and the type of chip is identical, only weld pad 101 does not redistribute through RDL, also the process of deposition one deck insulation insulating medium layer 202 has been lacked therebetween, shown in Fig. 5 A-5F.Fig. 5 A first directly settles soldered ball 205 on the weld pad 201 of the wafer 200 shown in Fig. 2 A, thus be formed in the front of wafer 200 namely protrude from the wafer 200 front end face of chip 200 ' (also) and be electrically connected to the solder projection 205 of chip 200 ' weld pad 201, plastic packaging is carried out afterwards, with the front of the first plastic packaging layer 206 coated silicon wafer 200 and solder projection 205 in the front of wafer 200; And carry out CMP grinding at the back side of wafer 200, after completing grinding, be also included in thinning after the back side of wafer 200 cover the step of layer of metal layer 209, as indicated by figures 5 a-5b.Afterwards in being coated with metal level 209 and the back side of wafer 200 after being thinning, wafer 200 is cut, form the cutting groove 210 of isolation adjacent chips 200 ', now the first plastic packaging layer 206 of segment thickness is cut and forms the degree of depth that cutting groove 210 is arranged in the first plastic packaging layer 206, cutting groove 210 stops in the first plastic packaging layer 206, also namely multiple chips 200 ' now relies on the first plastic packaging layer 206 and interconnects, and metal level 209 is cut into the bottom electrode metal layer 209 ' being positioned at every chips 200 ' bottom surface simultaneously.Be coated with metal level 209 and the back side of wafer 200 after being thinning again, plastic packaging is carried out to wafer 200, form the second plastic packaging layer 211 of covered with metal layer 209 after completing plastic packaging, the part plastic packaging material that the second plastic packaging layer 211 comprises simultaneously is also filled in cutting groove 210, as shown in Figure 5 D.Grind the first plastic packaging layer 206 to be exposed in the first plastic packaging layer 206 ' of solder projection 205 after thinning, as shown in fig. 5e.Cut in cutting groove 210, chip 200 ' is separated, obtain the encapsulating structure 200 " D of the wafer scale shown in Fig. 5 F.It should be noted that in the step due to this embodiment and do not form silicon through hole TSV, so without the need to considering the position that silicon through hole TSV will be formed.Therefore whether the weld pad 101 of chip 100 end face of Figure 1A being redesigned into arrangement solder joint 104 neither necessary condition.Encapsulating structure 200 is " in D, the end face of chip 200 ' be formed protrude from chip 200 ' end face and be electrically connected to the solder projection 205 of chip 200 ' weld pad 201, comprise thinning after the first plastic packaging layer 206 ' in cutting process, form the top plastic-sealed body 206 covering chip 200 ' end face ", second plastic packaging layer 211 forms the bottom plastic-sealed body 211 ' covering bottom electrode metal layer 209 ' in cutting process, and the lateral extension portions 211 ' a of bottom plastic-sealed body 211 ' covers bottom electrode metal layer 209 ', side extensions 211 ' the b vertical with lateral extension portions 211 ' a covers the sidewall of chip 200 ', top plastic-sealed body 206 " sidewall, solder projection 205 is in top plastic-sealed body 206 " in exposed.
See Fig. 6 A-6E, the wafer 200 of the present invention after to be also provided in shown in Fig. 2 E thinning carries out the method for the another kind of wafer-level packaging of other processing steps, it should be noted that in this embodiment, be with the difference of 4A-4E, the backside deposition metal level of the wafer 200 not after thinning.
Shown in Fig. 6 A, carry out plastic packaging in the front of wafer 200, also cover insulating medium layer 202 with the front of the first plastic packaging layer 206 coated silicon wafer 200 and solder projection 205, first plastic packaging layer 206 simultaneously; CMP grinding is carried out in the back side of wafer 200, after completing grinding back surface, wafer 200 is cut, form the cutting groove 210 of isolation adjacent chips 200 ', now cutting groove 210 stops in the first plastic packaging layer 206, simultaneously insulating medium layer 202 be also cut into be positioned at every chips 200 ' end face top insulating medium layer 202 ', Fig. 6 B shown in.The back side of the wafer 200 again after thinning, carries out plastic packaging to wafer 200, forms the second plastic packaging layer 211 after completing plastic packaging, and the part plastic packaging material that the second plastic packaging layer 211 comprises simultaneously is also filled in cutting groove 210, as shown in Figure 6 C.Grind the first plastic packaging layer 206 to be exposed in the first plastic packaging layer 206 by solder projection 205, as shown in Figure 6 D, solder projection 205 be exposed to thinning after the first plastic packaging layer 206 ' outside.Cut in cutting groove 210 again, chip 200 ' is separated, obtain the encapsulating structure 200 of the wafer scale shown in Fig. 6 E " E, the first plastic packaging layer 206 ' after thinning forms the top plastic-sealed body 206 covering top insulating medium layer 202 ' in this cutting process ".In this embodiment, after wafer 200 is thinning, its back side does not deposit any metal level, the bottom surface of chip 200 ' is also without any bottom electrode metal layer, the type of chip 200 ' is the IC of planar structure (Lateralstructure), arrangement solder joint 204 forms the signal terminal of the IC of this planar structure, and its all signal input output ends is all arranged on the side of chip 200 ' end face.Encapsulating structure 200 is " in E, distribution again technology is utilized to become to be arranged in cover the arrangement solder joint 204 of the top insulating medium layer 202 ' of chip 200 ' by the weld pad 201 being distributed in chip 200 ' end face again layout designs, also comprise thinning after the top plastic-sealed body 206 of covering top insulating medium layer 202 ' that formed in cutting process of the first plastic packaging layer 206 ' ", second plastic packaging layer 211 forms the lateral extension portions 211 ' a covering chip 200 ' bottom surface in cutting process, and the side extensions 211 ' b vertical with lateral extension portions 211 ' a also covers the sidewall of chip 200 ', the sidewall of top insulating medium layer 202 ', top plastic-sealed body 206 " sidewall, solder projection 205 is in top plastic-sealed body 206 " in exposed.
Compared with the flow process in Fig. 6 A-6E, in another execution mode, directly can also settle soldered ball on the weld pad 101 of chip 100 end face of Figure 1A and carry out the flow process of Fig. 6 A-6E, only weld pad 101 does not redistribute through RDL, and lack the process of deposition one deck insulation insulating medium layer 202, shown in Fig. 7 A-7E.As shown in Figure 7 A, the weld pad 201 of the wafer 200 shown in Fig. 2 A directly plants soldered ball 205, and carries out plastic packaging in the front of wafer 200, with the front of the first plastic packaging layer 206 coated silicon wafer 200 and solder projection 205; CMP grinding is carried out, the thickness of organic semiconductor device 200A in the back side of wafer 200; The back side of the wafer 200 afterwards after thinning, wafer 200 is cut, form the cutting groove 210 of isolation adjacent chips 200 ', now cutting groove 210 stops in the first plastic packaging layer 206, and now substrate 200A is divided into the substrate unit 200 ' A that every chips 200 ' comprises.The back side of the wafer 200 again after thinning, carries out plastic packaging to wafer 200, forms the second plastic packaging layer 211, and the part plastic packaging material that the second plastic packaging layer 211 comprises simultaneously is also filled in cutting groove 210, as seen in figure 7 c.Grind the first plastic packaging layer 206 to be exposed in the first plastic packaging layer 206 ' of solder projection 205 after thinning, as illustrated in fig. 7d.Cut in cutting groove 210, chip 200 ' is separated, obtain the encapsulating structure 200 " F of the wafer scale shown in Fig. 7 E.Silicon through hole TSV is not formed, without the need to considering the position that silicon through hole TSV will be formed due to same in the step of this embodiment.Therefore the weld pad 101 of chip 100 end face of Figure 1A being redesigned into arrangement solder joint 104 is not necessary condition.Encapsulating structure 200 is " in F, the type of chip 200 ' is the IC of planar structure, the end face of chip 200 ' be formed protrude from chip 200 ' end face and be electrically connected to the solder projection 205 of chip 200 ' weld pad 201, comprise thinning after the first plastic packaging layer 206 ' in cutting process, form the top plastic-sealed body 206 covering chip 200 ' end face ", second plastic packaging layer 211 forms the bottom plastic-sealed body 211 ' covering chip 200 ' bottom surface in cutting process, lateral extension portions 211 ' a of bottom plastic-sealed body 211 ' covers chip 200 ' bottom surface, side extensions 211 ' the b vertical with lateral extension portions 211 ' a also covers the sidewall of chip 200 ', top plastic-sealed body 206 " sidewall, solder projection 205 is in top plastic-sealed body 206 " in exposed.
Above embodiment is all first implement to carry out cutting in the side at the back side of wafer to form cutting groove, then cuts the plastic packaging material in cutting groove thus be separated by chip.Following content is cut providing the side of first implementing in the front of wafer, then carries out cutting the execution mode with separating chips in the side, the back side of wafer.
See the method for a kind of wafer-level packaging of Fig. 8 A-8I, be formed in the front of wafer 200 protrude from wafer 200 front and be electrically connected to the solder projection 205 of chip 200 ' weld pad 201, as shown in figures 8 a-8b.And carry out planting ball arrangement solder projection 205 on weld pad 201, as shown in Figure 8 B, cut in the front of wafer 200 afterwards, form the cutting groove 215 for isolating chip 200 ' being positioned at side, wafer 200 front, and this cutting groove 215 stops in the substrate 200A of wafer 200, between adjacent chip 200 ', cutting groove 215 can carry out cutting formation at the scribe line of wafer frontside (ScribeLine) place.Carry out plastic packaging in the front of wafer 200 afterwards, with the front of the first plastic packaging layer 206 coated silicon wafer 200 and solder projection 205, as shown in Figure 8 C, the plastic packaging material that the first plastic packaging layer 206 comprises simultaneously is also filled in cutting groove 215.CMP grinding is carried out again with the thickness of thinned wafer 200 at the back side of wafer 200, the i.e. thickness of substrate 200A that comprises of thinned wafer 200, as in fig. 8d, the segment thickness (as D5) of wafer 200 is polished, namely the thickness of substrate 200A obtains thinning, the back side of the wafer 200 after thinning can be selected afterwards to etch, with repair its grind the lattice damage that causes or eliminate thinning after the remaining stressor layers in the back side of wafer 200.Shown in Fig. 8 E, the back side of the wafer 200 after thinning covers layer of metal layer 209.Afterwards in being coated with metal level 209 and the back side of wafer 200 after being thinning, wafer 200 is cut, formed be positioned at thinning after the cutting groove 216 for isolating chip 200 ' of side, wafer 200 back side, and be arranged in thinning after the cutting groove 216 of side, wafer 200 back side stop at the substrate 200A of wafer 200 and contact with the plastic packaging material being filled in the cutting groove 215 being arranged in side, wafer 200 front further, namely cutting groove 216 is kept to aim in vertical direction with cutting groove 215 and contact with each other, as shown in Figure 8 F.Metal level 209 is cut into the bottom electrode metal layer 209 ' covering every chips 200 ' bottom surface simultaneously.Plastic packaging is carried out to wafer 200 in the back side of the wafer 200 after thinning, formed coated thinning after the second plastic packaging layer 211 at the back side of wafer 200, second plastic packaging layer 211 goes back covered with metal layer 209 simultaneously, the plastic packaging material that simultaneously the second plastic packaging layer 211 comprises also be filled in be arranged in thinning after the cutting groove 216 of side, wafer 200 back side, as shown in fig. 8g.Grind the first plastic packaging layer 206 afterwards to be exposed in the first plastic packaging layer 206 ' of solder projection 205 after thinning, obtain the first plastic packaging layer 206 ' thinning in Fig. 8 H.Simultaneously in be arranged in side, wafer 200 front cutting groove 216, be arranged in thinning after the cutting groove 215 of side, wafer 200 back side cut, multiple chip 200 ' is carried out the encapsulating structure 200 being separated to obtain wafer scale " G; as shown in fig. 81, the first plastic packaging layer 206 ' after thinning forms the top plastic-sealed body 206 covering chip 200 ' front in this cutting process ".
The encapsulating structure 200 of wafer scale " in G; comprise the top plastic-sealed body 206 of coating chip 200 ' ", the a of top plastic-sealed body 206 " lateral extension portions 206 " covers the front of chip 200 ', a part of sidewall of chip 200 ' is also covered the top plastic-sealed body vertical with a of top plastic-sealed body 206 " lateral extension portions 206 " 206 " side extensions 206 " by b simultaneously, and solder projection 205 is in top plastic-sealed body 206 " in exposed.Also comprise the bottom plastic-sealed body 211 ' of coating chip 200 ', the lateral extension portions 211 ' a of bottom plastic-sealed body 211 ' covers the bottom surface of chip 200 ', and also covers on bottom electrode metal layer 209 ' simultaneously; Side extensions 211 ' the b of the bottom plastic-sealed body 211 ' vertical with the lateral extension portions 211 ' a of bottom plastic-sealed body 211 ', also by an other part for chip 200 ', not by side extensions 206, " the coated sidewall of b is covered, and now the side extensions 211 ' b of the b of top plastic-sealed body 206 " side extensions 206 " and bottom plastic-sealed body 211 ' contacts with each other and by sealing seamless for chip 200 ' simultaneously.In a kind of execution mode, the deposition process of metal level 209 is cancelled in above-mentioned preparation flow, just bottom electrode metal layer 209 ' is there is not in the device of then follow-up acquisition, the now chip 200 ' IC that is planar structure, its all signal input output ends is all arranged on the side of chip 200 ' end face.In a kind of execution mode, the chip 200 ' comprising bottom electrode metal layer 209 ' can be then two MOSFET of rectilinear common drain; And the drain electrode of a MOSFET and the drain electrode of another MOSFET are electrically connected by described bottom electrode metal layer 209 ' in two MOSFET, and arrange source electrode and the gate electrode that solder joint 204 forms any one MOSFET in two MOSFET respectively at least partially.In a kind of execution mode, comprise in the chip 200 ' of bottom electrode metal layer 209 ' and at least comprise multiple diode, and described diode electrode terminal to be electrically connected on bottom electrode metal layer 209 ' jointly, and arranging another electrode terminal that solder joint 204 forms described diode respectively at least partially, each arrangement solder joint 204 forms another electrode terminal of a diode.
Based on Fig. 8 A-8I, " G can also be prepared according to the flow process shown in Fig. 9 A-9E packaging body 200; complete the front of plastic packaging wafer 200 in Fig. 8 C; after the front of the first plastic packaging layer 206 coated silicon wafer 200 and solder projection 205; as shown in Figure 9 A; first grind the first plastic packaging layer 206 to be exposed in the first plastic packaging layer 206 ' of solder projection 205 after thinning, then carry out CMP grinding at the back side of wafer 200 with the thickness of thinned wafer 200, as shown in Figure 9 B.After the segment thickness (as D6) of wafer 200 is polished, the back side of the wafer 200 after thinning can be selected to carry out etching and the back side of wafer 200 after thinning covers layer of metal layer 209, as Fig. 9 C.Afterwards in being coated with metal level 209 and the back side of wafer 200 after being thinning, wafer 200 is cut, formed be positioned at thinning after the cutting groove 216 for isolating chip 200 ' of side, wafer 200 back side, and be arranged in thinning after the cutting groove 216 of side, wafer 200 back side stop at the substrate 200A of wafer 200 and contact with the plastic packaging material being filled in the cutting groove 215 being arranged in side, wafer 200 front further, namely cutting groove 216 is kept to aim in vertical direction with cutting groove 215 and contact with each other, as shown in fig. 9d.Plastic packaging is carried out to wafer 200 in the back side of the wafer 200 again after thinning, formed coated thinning after the second plastic packaging layer 211 at the back side of wafer 200, second plastic packaging layer 211 goes back covered with metal layer 209 simultaneously, the plastic packaging material that simultaneously the second plastic packaging layer 211 comprises also be filled in be arranged in thinning after the cutting groove 216 of side, wafer 200 back side, as shown in fig. 9e.Now, Fig. 9 E and Fig. 8 H, both are indistinction also.The encapsulating structure 200 of wafer scale as shown in fig. 81 " in G, comprise the top plastic-sealed body 206 of coating chip 200 ' ", the a of top plastic-sealed body 206 " lateral extension portions 206 " covers the front of chip 200 ', the partial sidewall of chip 200 ' is also covered the top plastic-sealed body vertical with a of top plastic-sealed body 206 " lateral extension portions 206 " 206 " side extensions 206 " by b simultaneously, and solder projection 205 is in top plastic-sealed body 206 " in exposed, second plastic packaging layer 211 forms the bottom plastic-sealed body 211 ' covering bottom electrode metal layer 209 ' in cutting process, " a covers on the bottom electrode metal layer 209 ' of the bottom surface of chip 200 ' lateral extension portions 211 of bottom plastic-sealed body 211 ', also other a part of sidewall of chip 200 ' is covered with lateral extension portions 211 " side extensions 211 of the bottom plastic-sealed body 211 ' that a the is vertical " b of bottom plastic-sealed body 211 ' simultaneously, " b's then side extensions 211 of the just b of top plastic-sealed body 206 " side extensions 206 " and bottom plastic-sealed body 211 ' contacts with each other and by sealing seamless for chip 200 '.
Flow process shown in above-mentioned Fig. 8 A-8I or 9A-9E is applicable to the preparation of the IC of planar structure and the MOSFET of vertical stratification, and is equally also applicable to the preparation via RDL technical finesse or the chip without RDL technical finesse.
See the method for a kind of wafer-level packaging of Figure 10 A-10G, composition graphs 1B-1D, distribution again technology RDL is utilized to become to be arranged in cover the arrangement solder joint 204 of the insulating medium layer 202 of chip 200 ' by the weld pad 201 being distributed in chip 200 ' end face again layout designs, as shown in Figure 10 A.And carry out planting ball arrangement solder projection 205 on arrangement solder joint 204, cut in the front of wafer 200 afterwards, form the cutting groove 215 for isolating chip 200 ' being positioned at side, wafer 200 front, and this cutting groove 215 stops in the substrate 200A of wafer 200.Carry out plastic packaging in the front of wafer 200 afterwards, with the first plastic packaging layer 206 coated insulation dielectric layer 202 and solder projection 205, as shown in Figure 10 B, the plastic packaging material that the first plastic packaging layer 206 comprises simultaneously is also filled in cutting groove 215.Carry out CMP grinding again at the back side of wafer 200 with the thickness of thinned wafer 200, as illustrated in figure 10 c, the back side of the wafer 200 after thinning can be selected afterwards to etch, and the back side of wafer 200 after thinning covers layer of metal layer 209.Afterwards in being coated with metal level 209 and the back side of wafer 200 after being thinning, wafer 200 is cut, formed be positioned at thinning after the cutting groove 216 for isolating chip 200 ' of side, wafer 200 back side, and be arranged in thinning after the cutting groove 216 of side, wafer 200 back side stop at the substrate 200A of wafer 200 and contact with the plastic packaging material being filled in the cutting groove 215 being arranged in side, wafer 200 front further, namely cutting groove 216 is kept to aim in vertical direction with cutting groove 215 and contact with each other, as shown in Figure 10 D.Metal level 209 is cut into the bottom electrode metal layer 209 ' being positioned at every chips 200 ' bottom surface.Plastic packaging is carried out to wafer 200 in the back side of the wafer 200 after thinning, formed coated thinning after the second plastic packaging layer 211 at the back side of wafer 200, second plastic packaging layer 211 goes back covered with metal layer 209 simultaneously, the plastic packaging material that simultaneously the second plastic packaging layer 211 comprises also be filled in be arranged in thinning after the cutting groove 216 of side, wafer 200 back side, as shown in figure 10e.Grind the first plastic packaging layer 206 to be exposed in the first plastic packaging layer 206 ' of solder projection 205 after thinning, obtain the first plastic packaging layer 206 ' thinning in Figure 10 F.Simultaneously in the cutting groove 216 being arranged in side, wafer 200 front, be arranged in thinning after the cutting groove 215 of side, wafer 200 back side cut, multiple chip 200 ' is carried out the encapsulating structure 200 " H being separated to obtain wafer scale, as shown in figure 10g, insulating medium layer 202 is also cut into the top insulating medium layer 202 ' being positioned at every chips 200 ' end face, the first plastic packaging layer 206 ' after thinning forms the top plastic-sealed body 206 covering top insulating medium layer 202 ' in this cutting process ", and the substrate 200A that wafer 200 comprises is cut into the substrate unit 200 ' A that each chip 200 ' comprises.
In method flow shown in Figure 10 A-10G, cover layer of metal layer 209 to the wafer 200 after thinning the back side before, implementation of class can also be selected like the step of 2F-2I: backside coating one deck barrier layer 207 of the wafer 200 after thinning, and form the opening 207 ' being arranged in barrier layer 207; Etched by the back side of the wafer 200 of opening 207 ' after thinning, form the through hole 208 of contact first kind arrangement solder joint 204a in the substrate 200A comprised in wafer and insulating medium layer 202, remove barrier layer 207 afterwards; Fill in metal material 208 ' to described through hole 208, and the layer of metal layer 209 that the back side of the wafer 200 after thinning covers is electrically connected to by the metal material 208 ' be filled in described through hole 208 first kind contacted with through hole 208 and arranges on solder joint 204a, now select the described first kind that contacts with through hole 208 to arrange the position of solder joint 204a, be arranged in the insulating medium layer 202 on the substrate 200A non-active device cell region that covers.
In method flow shown in Figure 10 A-10G, settle solder projection 205 on arrangement solder joint 204 before, implementation of class can also be selected like the step of Fig. 3 A-3F: coating one deck is coated is positioned at the insulating medium layer 202 in wafer 200 front and the barrier layer 213 of arrangement solder joint 204, and formation is arranged in the opening 213 ' that barrier layer 213 contacts first kind arrangement solder joint 204a; By described opening 213 ', described first kind arrangement solder joint 204a and insulating medium layer 202, substrate 200A are etched, in substrate 200A and insulating medium layer 202, form the through hole 214 running through this first kind arrangement solder joint 204a, and remove barrier layer 213; While settling solder projection 205 afterwards on arrangement solder joint 204, some solder 214 ' is also filled in described through hole 214 in the lump.In this flow process, carry out in the back side of wafer 200 in process of lapping, the back side of the wafer 200 after thinning exposes outside the solder 214 ' be filled in through hole 214, and the layer of metal layer 209 that the back side of wafer 200 afterwards after thinning covers is electrically connected at by the solder 214 ' be filled in through hole 214 first kind contacted with through hole 214 arranges on solder joint 204a.
The encapsulating structure 200 of wafer scale " in H; the top plastic-sealed body 206 of coating chip 200 ' ", the a of top plastic-sealed body 206 " lateral extension portions 206 " covers on top insulating medium layer 202 ', the sidewall of top insulating medium layer 202 ', the partial sidewall of chip 200 ' are also covered the top plastic-sealed body vertical with a of top plastic-sealed body 206 " lateral extension portions 206 " 206 " side extensions 206 " by b simultaneously, and solder projection 205 is in top plastic-sealed body 206 " in exposed; And the bottom plastic-sealed body 211 ' of coating chip 200 ', lateral extension portions 211 ' a of bottom plastic-sealed body 211 ' covers the bottom surface of chip 200 ', other a part of sidewall of chip 200 ' is also covered by the side extensions 211 ' b of the bottom plastic-sealed body 211 ' vertical with the lateral extension portions 211 ' a of bottom plastic-sealed body 211 ' simultaneously, and the side extensions 211 ' b of the b of top plastic-sealed body 206 " side extensions 206 " and bottom plastic-sealed body 211 ' contacts with each other with by sealing seamless for chip 200 '.Also be included in one deck bottom electrode metal layer 209 ' that chip 200 ' bottom surface covers, while the bottom surface of the lateral extension portions 211 ' a covering chip 200 ' of bottom plastic-sealed body 211 ', also cover bottom electrode metal layer 209 '.The through hole 208 shown in similar Fig. 2 M can also be included in Figure 10 G, now chip 200 ' is rectilinear MOSFET, be formed in the through hole 208 of substrate unit 200 ' A that chip 200 ' comprises and top insulating medium layer 202 ' middle contact first kind arrangement solder joint 204a, and the first kind contacted with through hole 208 is arranged solder joint 204a by the metal material 208 ' of filling in through hole 208 to be electrically connected on described bottom electrode metal layer 209 ', bottom electrode metal layer 209 ' forms the drain electrode of MOSFET.Wafer level packaging structure 200 " H-1 as shown in Figure 10 H.In another embodiment, chip 200 ' in Figure 10 G is also rectilinear MOSFET, and the through hole 214 shown in similar Fig. 3 J can be included, now through hole 214 runs through the first kind contacted with through hole 214 and arranges solder joint 204a, and the first kind contacted with through hole 214 is arranged solder joint 204a is electrically connected on bottom electrode metal layer 209 '; And the planar cross-sectional size of through hole 214 is less than the planar dimension of arrangement solder joint 204, and the metal material of filling in through hole 214 is the extension of the solder projection 205 be placed on first kind arrangement solder joint 204a, wafer level packaging structure 200 " H-2 as shown in figure 10i.
In above-described embodiment, complete to the first plastic packaging layer 206 grind rear acquisition one thinning after the end face of the first plastic packaging layer 206 ', and solder projection 205 can be selected in this process of lapping to carry out part grinding until solder projection 205 expose to thinning after the first plastic packaging layer 206 ', simultaneously solder projection 205 due to polished and surface (mark) that is that formed exposes to thinning after the first plastic packaging layer 206 ' (also namely expose to top plastic-sealed body 206 "), and the surface of solder projection 205 and thinning after the end face of end face (also i.e. top plastic-sealed body 206 " of the first plastic packaging layer 206 ') keep coplanar.So in each packaging body formed, top plastic-sealed body 206 " solder projection 205 is not enveloped completely; but top plastic-sealed body 206 " around the side being centered around solder projection 205, and top plastic-sealed body 206 " end face and any one solder projection 205 expose to top plastic-sealed body 206 " surface co-planar.In the above-described embodiments, different capsulation materials can be utilized to carry out plastic package process to obtain the first plastic packaging layer 206, second plastic packaging layer 211 of different plastic packaging material respectively.
By illustrating and accompanying drawing, give the exemplary embodiments of the ad hoc structure of embodiment, such as, this case is set forth with MOSFET, the two MOSFET of common drain, and based on the present invention's spirit, chip also can do the conversion of other types.Although foregoing invention proposes existing preferred embodiment, but these contents are not as limitation.
For a person skilled in the art, after reading above-mentioned explanation, various changes and modifications undoubtedly will be apparent.Therefore, appending claims should regard the whole change and correction of containing true intention of the present invention and scope as.In Claims scope, the scope of any and all equivalences and content, all should think and still belong to the intent and scope of the invention.

Claims (26)

1. a method for wafer-level packaging, is characterized in that, comprises the following steps:
The wafer that one includes multiple chip is provided, is formed in the front of wafer and protrude from wafer frontside and the solder projection being electrically connected to chip pad,
The front of wafer described in plastic packaging, with the front of the first plastic packaging layer coated silicon wafer and solder projection;
Grind in the back side of wafer;
The back side of the wafer after thinning is cut wafer, form the cutting groove of isolating chip, and cutting groove stops in the first plastic packaging layer;
Plastic packaging is carried out to wafer in the back side of the wafer after thinning, formed coated thinning after the second plastic packaging layer at the back side of wafer, plastic packaging material is also filled in cutting groove simultaneously;
Grind the first plastic packaging layer to be exposed in the first plastic packaging layer of solder projection after thinning;
Cut in described cutting groove, chip is separated, the chip of described first plastic packaging layer and the coated described separation of the second plastic packaging layer, exposed in the first plastic packaging layer of described solder projection after thinning;
Wherein after the grinding back surface of wafer, the back side of the wafer after thinning, penetrates the through hole that substrate that wafer comprises and insulating medium layer form the first kind weld pad in the described chip pad of contact, and fills in metal material to described through hole; The position of the described first kind weld pad contacted with through hole, is positioned on the insulating medium layer on the substrate non-active device cell region covering wafer.
2. the method for claim 1, is characterized in that, formation described through hole after, also on the inwall of described through hole, deposit isolation liner bed course, and fill metal material by isolation liner bed course and be looped around around through hole substrate region insulation.
3. method as claimed in claim 2, is characterized in that, also covers the back side of layer of metal layer to the wafer after thinning.
4. method as claimed in claim 3, it is characterized in that, described chip is rectilinear MOSFET, and described metal layer on back is electrically connected to by the metal material of described filling vias the drain electrode that described first kind weld pad forms described MOSFET.
5. the method for claim 1, is characterized in that, the planar cross-sectional size of the through hole formed is less than the planar dimension of weld pad.
6. a method for wafer-level packaging, is characterized in that, comprises the following steps:
The wafer that one includes multiple chip is provided, is formed in the front of wafer and protrude from wafer frontside and the solder projection being electrically connected to chip pad,
The front of wafer described in plastic packaging, with the front of the first plastic packaging layer coated silicon wafer and solder projection;
Grind in the back side of wafer;
The back side of the wafer after thinning is cut wafer, form the cutting groove of isolating chip, and cutting groove stops in the first plastic packaging layer;
Plastic packaging is carried out to wafer in the back side of the wafer after thinning, formed coated thinning after the second plastic packaging layer at the back side of wafer, plastic packaging material is also filled in cutting groove simultaneously;
Grind the first plastic packaging layer to be exposed in the first plastic packaging layer of solder projection after thinning;
Cut in described cutting groove, chip is separated, the chip of described first plastic packaging layer and the coated described separation of the second plastic packaging layer, exposed in the first plastic packaging layer of described solder projection after thinning;
Wherein before the front of wafer forms solder projection, in the front of wafer, penetrate the substrate that the first kind weld pad in described chip pad, insulating medium layer and part wafer comprise, form the through hole of contact first kind weld pad; The position of described first kind weld pad, is positioned on the insulating medium layer on the substrate non-active device cell region covering wafer; And
Settle on described weld pad in the process of solder projection, some solder is filled in described through hole simultaneously.
7. method as claimed in claim 6, it is characterized in that, after the described through hole of formation, also on the inwall of described through hole, deposit isolation liner bed course, and be filled in solder in described through hole by isolation liner bed course and the substrate region insulation that is looped around around through hole.
8. method as claimed in claim 7, is characterized in that, also covers the back side of layer of metal layer to the wafer after thinning.
9. method as claimed in claim 8, it is characterized in that, described chip is rectilinear MOSFET, and described metal layer on back is electrically connected to by the solder of described filling vias the drain electrode that described first kind weld pad forms described MOSFET.
10. method as claimed in claim 6, is characterized in that, the mode forming through hole is dry etching or wet etching or laser ablation.
The method of 11. 1 kinds of wafer-level packaging, is characterized in that, comprises the following steps:
The wafer that one includes multiple chip is provided, is formed in the front of wafer and protrude from wafer frontside and the solder projection being electrically connected to chip pad,
The front of wafer described in plastic packaging, with the front of the first plastic packaging layer coated silicon wafer and solder projection;
Grind in the back side of wafer;
The back side of the wafer after thinning is cut wafer, form the cutting groove of isolating chip, and cutting groove stops in the first plastic packaging layer;
Plastic packaging is carried out to wafer in the back side of the wafer after thinning, formed coated thinning after the second plastic packaging layer at the back side of wafer, plastic packaging material is also filled in cutting groove simultaneously;
Grind the first plastic packaging layer to be exposed in the first plastic packaging layer of solder projection after thinning;
Cut in described cutting groove, chip is separated, the chip of described first plastic packaging layer and the coated described separation of the second plastic packaging layer, exposed in the first plastic packaging layer of described solder projection after thinning;
Wherein before plastic packaging is carried out in the front of wafer, cut in the front of wafer, formed and be positioned at the cutting groove for isolating chip of wafer frontside side, and this cutting groove stops in the substrate that wafer comprises;
In the process of the first plastic packaging layer in the front of formation coated silicon wafer, plastic packaging material is also filled in the cutting groove being arranged in wafer frontside side;
And formed be arranged in thinning after the cutting groove of wafer rear side stop in the substrate and contact with the plastic packaging material being filled in the cutting groove being positioned at wafer frontside side further.
12. methods as claimed in claim 11, is characterized in that, after the back side of wafer completes grinding, be also included in thinning after the back side of wafer etch, and cover the step of layer of metal layer to the back side of the wafer after thinning; And
Formed be arranged in thinning after the process of the cutting groove for isolating chip of wafer rear side, the back side being coated with metal level of the wafer after thinning is cut wafer; And
Formed coated thinning after wafer the back side the second plastic packaging layer process in, described second plastic packaging layer also simultaneously coated described metal level.
13. methods as claimed in claim 11, is characterized in that, before the back side of the wafer after covering layer of metal layer is extremely thinning, further comprising the steps of:
Backside coating one deck barrier layer of the wafer after thinning, and form the opening being arranged in barrier layer;
By be opened on thinning after the back side of wafer etch, form the through hole of the first kind weld pad in the described chip pad of contact in the substrate comprised in wafer and insulating medium layer, and remove barrier layer;
Fill metal material in described through hole, and the layer of metal layer that the back side of wafer after thinning covers is electrically connected to by the metal material be filled in described through hole on the first kind weld pad that contacts with through hole.
14. methods as claimed in claim 13, is characterized in that, the position of the described first kind weld pad contacted with through hole, are arranged in the insulating medium layer on the substrate non-active device cell region that covers.
15. methods as claimed in claim 11, is characterized in that, settle solder projection on weld pad before, further comprising the steps of:
One deck is coated is positioned at the insulating medium layer of wafer frontside and the barrier layer of weld pad in coating, and is formed and be arranged in the opening that barrier layer contacts first kind weld pad;
By described opening, described first kind weld pad and insulating medium layer, substrate are etched, formed and run through this first kind weld pad and insulating medium layer and the through hole ending at the predetermined depths of substrate one, and remove barrier layer;
While settling solder projection afterwards on weld pad, some solder is also filled in described through hole in the lump.
16. methods as claimed in claim 15, it is characterized in that, carry out in the back side of wafer in process of lapping, the back side of the wafer after thinning exposes outside filling solder in through-holes, and the layer of metal layer that the back side of wafer afterwards after thinning covers is electrically connected at by the solder of filling in through-holes on the first kind weld pad that contacts with through hole.
The method of 17. 1 kinds of wafer-level packaging, is characterized in that, comprises the following steps:
The wafer that one includes multiple chip is provided, is formed in the front of wafer and protrude from wafer frontside and the solder projection being electrically connected to chip pad,
The front of wafer described in plastic packaging, with the front of the first plastic packaging layer coated silicon wafer and solder projection;
Grind in the back side of wafer;
The back side of the wafer after thinning is cut wafer, form the cutting groove of isolating chip, and cutting groove stops in the first plastic packaging layer;
Plastic packaging is carried out to wafer in the back side of the wafer after thinning, formed coated thinning after the second plastic packaging layer at the back side of wafer, plastic packaging material is also filled in cutting groove simultaneously;
Grind the first plastic packaging layer to be exposed in the first plastic packaging layer of solder projection after thinning;
Cut in described cutting groove, chip is separated, the chip of described first plastic packaging layer and the coated described separation of the second plastic packaging layer, exposed in the first plastic packaging layer of described solder projection after thinning;
Wherein after the grinding back surface completing wafer, be also included in thinning after the back side of wafer cover the step of layer of metal layer; And
In the process of cutting groove forming isolating chip, the back side being coated with metal level of the wafer after thinning is cut wafer; And
Formed coated thinning after wafer the back side the second plastic packaging layer process in, described second plastic packaging layer also simultaneously covered with metal layer.
18. methods as claimed in claim 17, is characterized in that, described chip is two MOSFET of rectilinear common drain; And
In two MOSFET, the drain electrode of a MOSFET and the drain electrode of another MOSFET are electrically connected by described metal level, and weld pad forms source electrode and the gate electrode of any one MOSFET in two MOSFET respectively at least partially.
The encapsulating structure of 19. 1 kinds of wafer scale, in this encapsulating structure, the end face of chip be formed protrude from chip end face and be electrically connected to the solder projection of chip pad, it is characterized in that, also comprise:
Be coated on the top plastic-sealed body of chip end face, described top plastic-sealed body is centered around around the side of described solder projection, the end face of described top plastic-sealed body and the surface co-planar exposing to top plastic-sealed body of solder projection described in any one;
The bottom plastic-sealed body of coated described chip bottom, the lateral extension portions of described bottom plastic-sealed body covers the bottom surface of chip, the sidewall of chip is also covered by the side extensions of the bottom plastic-sealed body vertical with lateral extension portions simultaneously, and the side extensions of described bottom plastic-sealed body extends contact described top plastic-sealed body with by sealing seamless for chip;
Cover one deck bottom electrode metal layer of die bottom surface, while the back side of the lateral extension portions covering chip of described bottom plastic-sealed body, also cover bottom electrode metal layer.
The encapsulating structure of 20. wafer scale as claimed in claim 19, is characterized in that, also comprise
Be formed in the through hole contacting the first kind weld pad in described chip pad in the substrate unit and top insulating medium layer that chip comprises, and the first kind weld pad contacted with through hole is electrically connected on described bottom electrode metal layer by the metal material of filling in through hole.
The encapsulating structure of 21. wafer scale as claimed in claim 20, is characterized in that, the inwall of described through hole is also provided with isolation liner bed course, and the metal material of filling is by isolation liner bed course and the substrate region insulation that is looped around around through hole.
The encapsulating structure of 22. wafer scale as claimed in claim 21, is characterized in that, described through hole runs through this first kind weld pad contacted with through hole further; And
The planar cross-sectional size of through hole is less than the planar dimension of weld pad, and the metal material of filling in through hole is the extension of the solder projection be placed on first kind weld pad.
The encapsulating structure of 23. wafer scale as claimed in claim 20, it is characterized in that, described chip is rectilinear MOSFET, and the described first kind weld pad contacted with through hole forms the drain electrode of described MOSFET.
The encapsulating structure of 24. wafer scale as claimed in claim 19, is characterized in that:
Described top plastic-sealed body comprises the front that lateral extension portions covers chip, and the partial sidewall of chip is also covered by the side extensions of the top plastic-sealed body vertical with the lateral extension portions of top plastic-sealed body simultaneously;
The bottom plastic-sealed body of coating chip, the lateral extension portions of bottom plastic-sealed body covers the bottom surface of chip, other a part of sidewall of chip is also covered by the side extensions of the bottom plastic-sealed body vertical with the lateral extension portions of bottom plastic-sealed body simultaneously, and the side extensions of top plastic-sealed body and the side extensions of bottom plastic-sealed body contact with each other with by sealing seamless for chip.
The encapsulating structure of 25. wafer scale as claimed in claim 19, is characterized in that: described top plastic-sealed body and described bottom plastic-sealed body are made up of different capsulation materials.
The encapsulating structure of 26. wafer scale as claimed in claim 19, is characterized in that, described chip is two MOSFET of rectilinear common drain; And
In two MOSFET, the drain electrode of a MOSFET and the drain electrode of another MOSFET are electrically connected by described metal level.
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