CN102969267B - The manufacture method of silicon-on-insulator silicon chip and buoyancy aid DRAM cell - Google Patents
The manufacture method of silicon-on-insulator silicon chip and buoyancy aid DRAM cell Download PDFInfo
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- CN102969267B CN102969267B CN201110256000.4A CN201110256000A CN102969267B CN 102969267 B CN102969267 B CN 102969267B CN 201110256000 A CN201110256000 A CN 201110256000A CN 102969267 B CN102969267 B CN 102969267B
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 113
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 113
- 239000010703 silicon Substances 0.000 title claims abstract description 112
- 238000000034 method Methods 0.000 title claims abstract description 72
- 239000012212 insulator Substances 0.000 title claims abstract description 36
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 84
- 239000000758 substrate Substances 0.000 claims abstract description 52
- 239000012528 membrane Substances 0.000 claims abstract description 41
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 41
- 230000008569 process Effects 0.000 claims abstract description 16
- RPAJSBKBKSSMLJ-DFWYDOINSA-N (2s)-2-aminopentanedioic acid;hydrochloride Chemical compound Cl.OC(=O)[C@@H](N)CCC(O)=O RPAJSBKBKSSMLJ-DFWYDOINSA-N 0.000 claims abstract description 14
- 125000004433 nitrogen atom Chemical group N* 0.000 claims abstract description 14
- 230000003647 oxidation Effects 0.000 claims abstract description 7
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 7
- 230000015572 biosynthetic process Effects 0.000 claims abstract 2
- 238000002513 implantation Methods 0.000 claims description 7
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 6
- 239000001257 hydrogen Substances 0.000 claims description 6
- 229910052739 hydrogen Inorganic materials 0.000 claims description 6
- 239000007943 implant Substances 0.000 claims description 2
- 230000000694 effects Effects 0.000 abstract description 14
- 230000014759 maintenance of location Effects 0.000 abstract description 8
- SBEQWOXEGHQIMW-UHFFFAOYSA-N silicon Chemical compound [Si].[Si] SBEQWOXEGHQIMW-UHFFFAOYSA-N 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 description 8
- 230000008901 benefit Effects 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 238000002360 preparation method Methods 0.000 description 3
- 239000002800 charge carrier Substances 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- GPRLSGONYQIRFK-UHFFFAOYSA-N hydron Chemical compound [H+] GPRLSGONYQIRFK-UHFFFAOYSA-N 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000005685 electric field effect Effects 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
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- 230000001737 promoting effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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Abstract
The present invention proposes a kind of manufacture method of silicon-on-insulator silicon chip, comprises the steps: to be formed in the first silicon chip to be rich in hydrionic buried regions; Thermal oxidation process is adopted to form silica membrane at the second silicon chip surface; Adopt decoupled plasma nitridation method that nitrogen-atoms is implanted silica membrane surface; Second wafer bonding, above the first silicon chip, can form dangling bonds more in the interface of silica membrane and the first wafer bonding in bonding process; Wafer heat after para-linkage, makes the first silicon chip peel off formation silicon-on-insulator silicon chip from being rich in hydrionic buried regions.By the enforcement of technique scheme, provide a kind of raising data retention that can on insulator prepares by silicon silicon chip can the manufacture method of floater effect memory cell, to increase the interface dangling bonds between silica membrane and substrate, thus effective trapped electron, improve the data retention energy of the floater effect memory cell of PMOS structure.
Description
Technical field
The present invention relates to a kind of semiconductor technology of preparing, particularly relate to a kind of manufacture method of silicon-on-insulator silicon chip, to improve the data hold time of buoyancy aid DRAM cell.
Background technology
Along with the high speed development of integrated circuit technology, integrated level and technique allow the more memory of Embedded.In-line memory is at system level chip (SoC, SystemonChip) area proportion increases year by year, the area of 90% of 60-70% in 2007 and even 2014 is risen to by the chip area of 1999 annuals 20%, as can be seen here, the quality of in-line memory on the impact of chip by increasing.Wherein, dynamic random access memory (DRAM in in-line memory, DynamicRandomAccessMemory) possess the advantages such as speed is fast, low in energy consumption, high density, the development along with embedded dynamic memory technology has made Large Copacity DRAM be widely used in current system level chip SoC.Although the embedded dynamic memory (eDRAM of Large Copacity, embeddedDynamicRandomAccessMemory) utilization brings to SoC and such as improves broadband and reduce the functions such as power consumption, but SoC chip can only by the various benefits adopting embedded technology to realize eDRAM.Each memory cell of tradition eDRAM in addition to transistors, also need a deep trench capacitor structure, the deep trench of capacitor makes its width of the aspect ratio of memory cell much larger, therefore, eDRAM technique and regular logical process variations are very large, cause manufacturing process difficulty, its manufacture craft and cmos vlsi technique very incompatible, integrate quite difficulty, limit its application in embedded SoC.
In recent years, an important developing direction was the dynamic memory utilizing floater effect memory cell (FBC, FloatingBodyCell) to substitute eDRAM.FBC utilizes floater effect (FBE, FloatingBodyEffect) DRAM cell, see Fig. 1 a and 1b, its principle utilizes silicon-on-insulator (SOI, SilicononInsulator) floater effect that in device 208, the buffer action of oxygen buried regions 202 (BOX) is brought, using segregate buoyancy aid (FloatingBody) as memory node, realize one writing and write " 0 ".Adopt NMOS structure for floater effect memory cell below, composition graphs 1a and the operation principle of Fig. 1 b to FBC are set forth.As shown in Figure 1a, with source electrode (S) 220 as the reference voltage, source electrode can ground connection, positive bias is added at grid (G) 218 drain electrode (D) 222, break-over of device, in small size device, less source-drain voltage can form very high electric field in drain electrode end vicinity, due to this transverse electric field effect, in the high electric field area of drain terminal, channel electrons obtains very large drift velocity and energy, become hot carrier, these hot carriers part is near drain electrode and silicon atom ionization by collision, produce electron hole pair, part hole 228 is swept substrate by the longitudinal electric field being pointed to substrate by grid, form substrate current.Due to the existence of aerobic buried regions 202, substrate current cannot discharge, and hole is gathered at buoyancy aid, is defined as the first store status, may be defined as one writing.As shown in Figure 1 b, with source electrode as the reference voltage, grid applies positive bias, drain electrode applies back bias voltage, and by PN junction forward bias, hole is launched from buoyancy aid, is defined as the second store status, may be defined as and writes " 0 ".Due to gathering of substrate electric charge, the threshold voltage (Vt) of device can be changed, the difference of threshold voltage can be caused by this two states of size perception of electric current, namely realize read operation.Capacitor in traditional DRAM is eliminated owing to utilizing the floater effect memory cell of silicon-on-insulator silicon chip manufacture, not only its technological process is complete and CMOS technology is compatible, simultaneously can the higher memory of component density, be therefore hopeful alternative existing traditional eDRAM and be applied in embedded system chip.
To make soi wafer, existing more common a kind of smart peeling (SmartCut) technique, can see Fig. 3 a to Fig. 3 e.
First, see Fig. 3 a, Hydrogen implantation is carried out to the first silicon chip 300, in the first silicon chip formed be rich in hydrionic buried regions 302, and above buried regions 302 and below form the first substrate 3041, second substrate 3042 respectively.
See Fig. 3 b, adopt thermal oxidation process, in the second silicon chip 306, form silica membrane 308 and bottom silicon 310.
See Fig. 3 c, the second silicon chip 306 is bonded in above the first silicon chip 300 by silica membrane 308.
See Fig. 3 d, the first silicon chip 300 and the second silicon chip 306 heat treatment after para-linkage, first substrate 3041 of the first silicon chip 300 and the second substrate 3042 are peeled off from being rich in hydrionic buried regions 302, thus forming silicon-on-insulator silicon chip 312, it comprises the second silicon chip 306 and the first wafer sections with the second silicon chip 306 bonding from top to bottom successively.Wherein, the first wafer sections be bonded together with the second silicon chip 306 comprises the first substrate 3041 of the first silicon chip 300, and the part buried regions 302 ' below the first substrate 3041.
See Fig. 3 e, silicon-on-insulator silicon chip 312 is adopted and carries out the techniques such as chemico-mechanical polishing, remove the buried regions 302 ' be connected with the first substrate 3041, and planarization is carried out to the first substrate 3041 of the first silicon chip, prepare silicon-on-insulator silicon chip 312 '.
But, when but having met with problem upper the employing during FBC of PMOS structure of above-mentioned silicon-on-insulator silicon chip 312 '.Keep the performance in (DataRetention) poor relative to the FBC of the FBC of NMOS structure, PMOS structure in data.This is due to the floater effect memory cell for PMOS structure, when one writing, as shown in Figure 2, the charge carrier that substrate gathers is electronics 226, because the effective mass of electronics is much smaller than hole, so, the mobility of electronics is greater than hole, therefore, the electronics that substrate gathers is easier to be leaked from source, causes the hydraulic performance decline of the FBC of PMOS structure in data maintenance.
In order to solve the problem, need the ability of the FBC trapped electron promoting PMOS structure, the data retention of the FBC of PMOS structure can be improved, but in the implementation process of reality, still there is sizable barrier, urgently introduce the new method effectively improving above-mentioned defect, the topmost problem faced when using with the FBC solving PMOS structure.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of manufacture method of silicon-on-insulator silicon chip, to increase the interface dangling bonds between oxygen buried regions and substrate, thus effective trapped electron, improve the data retention energy of the buoyancy aid DRAM cell of PMOS structure.
For solving the problem, a kind of manufacture method realizing silicon-on-insulator silicon chip that the present invention proposes, comprises the steps:
Adopt method for implanting to carry out Hydrogen implantation to the first silicon chip, formed in the first silicon chip and be rich in hydrionic buried regions, and form the first substrate, the second substrate respectively at buried regions upper and lower;
In the second silicon chip surface, adopt thermal oxidation process to form silica membrane;
Nitrogen-atoms is implanted to silica membrane surface;
Second silicon chip is bonded in above the first silicon chip by silica membrane, forms dangling bonds;
The first silicon chip after para-linkage and the second wafer heat, first substrate of the first silicon chip and the second substrate are peeled off from being rich in hydrionic buried regions, thus forming silicon-on-insulator silicon chip, it comprises the second silicon chip and the first wafer sections with the second wafer bonding from top to bottom successively;
The silicon-on-insulator silicon chip adopting as above method to prepare is prepared the operable silicon-on-insulator silicon chip of subsequent technique.
As seen from the above technical solution, compared with the SOI device adopting smart cut technique to be formed with tradition, soi wafer disclosed by the invention is carrying out thermal oxidation to the second silicon chip and after forming silica membrane, continue to have employed decoupled plasma nitridation (DPN to the second silicon chip, DecoupledPlasmaNitridation) method, is implanted to silica membrane surface by nitrogen-atoms.Nitrogen-atoms due to free state is concentrated in silica membrane surface, so the comparision contents of the nitrogen-atoms on silica membrane surface is high in the second silicon chip.When the second silicon chip is by silica membrane surface and the first wafer bonding after heat-treating, can form the larger dangling bonds of density between first substrate and silica membrane surface of the first silicon chip.The buoyancy aid dynamic random access memory of the PMOS structure that the soi wafer basis adopting the inventive method to prepare manufactures, owing to there are the larger dangling bonds of density between first substrate and silica membrane surface of the first silicon chip, the electronics that these dangling bonds have certain probability and substrate to gather carries out compound, thus increase the retention time of electronics at substrate, reduce the speed that electronics leaks from source, the soi wafer utilizing the present invention to prepare can be applicable among 65nm buoyancy aid dynamic random access memory preparation technology, improve the data retention energy of PMOS structure floater effect memory cell.And, the present invention just increases DPN technique in the process of preparation SOI device, SOI device structure is not changed, the buoyancy aid DRAM cell of directly preparation on this basis, compared with traditional eDRAM technique, because structure is simple, decreases the cellar area of memory, improve integration density, reduce manufacturing cost, and its technological process is complete and CMOS technology is compatible.
Accompanying drawing explanation
Fig. 1 a is the one writing view of the DRAM cell of NMOS structure floater effect in prior art;
Fig. 1 b be the DRAM cell of NMOS structure floater effect in prior art write " 0 " view;
Fig. 2 is the one writing view of the DRAM cell of PMOS structure floater effect in prior art;
Fig. 3 a to Fig. 3 e is the manufacture method of silicon-on-insulator silicon chip in prior art;
Fig. 4 is the method flow of a kind of silicon-on-insulator silicon chip of the present invention;
Fig. 5 a to Fig. 5 f is the manufacture method of a kind of silicon-on-insulator silicon chip of the present invention;
Fig. 6 is the sectional view buoyancy aid DRAM cell of PMOS structure preparing by a kind of silicon-on-insulator silicon chip of the present invention.
Embodiment
For enabling above-mentioned purpose of the present invention, feature and advantage become apparent more, are described in detail the specific embodiment of the present invention below in conjunction with accompanying drawing.
Set forth a lot of detail in the following description so that fully understand the present invention.But the present invention can be much different from alternate manner described here to implement, those skilled in the art can when without prejudice to doing similar popularization when intension of the present invention, therefore the present invention is by the restriction of following public concrete enforcement.
Secondly, the present invention utilizes schematic diagram to be described in detail, when describing the embodiment of the present invention in detail; for ease of explanation; represent that the profile of device architecture can be disobeyed general ratio and be made partial enlargement, and described schematic diagram is example, it should not limit the scope of protection of the invention at this.In addition, the three-dimensional space of length, width and the degree of depth should be comprised in actual fabrication.
See Fig. 4, the manufacture method flow process of a kind of silicon-on-insulator silicon chip provided by the present invention is:
S100: adopt method for implanting to carry out Hydrogen implantation to the first silicon chip, is formed and is rich in hydrionic buried regions, and form the first substrate, the second substrate respectively at buried regions upper and lower in the first silicon chip;
S101: adopt thermal oxidation process to form silica membrane at the second silicon chip surface;
S102: nitrogen-atoms is implanted to silica membrane surface;
S103: the second silicon chip is bonded in above the first silicon chip by silica membrane, forms dangling bonds;
S104: the first silicon chip after para-linkage and the second wafer heat, first substrate of the first silicon chip and the second substrate are peeled off from being rich in hydrionic buried regions, thus forming silicon-on-insulator silicon chip, it comprises the second silicon chip and the first wafer sections with the second wafer bonding from top to bottom successively;
S105: prepare the operable silicon-on-insulator silicon chip of subsequent technique on the silicon-on-insulator silicon chip adopting as above method to prepare.
Below for the method flow shown in Fig. 4, by reference to the accompanying drawings 5a to 5f, a kind of manufacture craft of silicon-on-insulator silicon chip is described in detail.
S100: adopt method for implanting to carry out Hydrogen implantation to the first silicon chip, is formed and is rich in hydrionic buried regions, and form the first substrate, the second substrate respectively at buried regions upper and lower in the first silicon chip.
See Fig. 5 a, there is provided the first silicon chip 400, adopt method for implanting to carry out Hydrogen implantation to first piece of silicon chip 400, hydrogen ion can be formed and be rich in hydrionic buried regions 402 in the first silicon chip 400, meanwhile, above and below buried regions 402, form the first substrate 4041, second substrate 4042 respectively.The degree of depth of buried regions 402 is controlled by Implantation Energy.
S101: adopt thermal oxidation process to form silica membrane at the second silicon chip surface;
See Fig. 5 b, provide the second silicon chip 406, be oxidized on the surface at the second silicon chip 406, form silica membrane 408, being positioned at below silica membrane 408 is bottom silicon 410.
S102: nitrogen-atoms is implanted to silica membrane surface;
See Fig. 5 c, nitrogen-atoms is implanted in silica membrane 408 by DPN method, makes the nitrogen-atoms of the high concentration of free state concentrate on silica membrane 408 surface.The advantage of DPN method is that nitrogen-atoms is concentrated in the surface of silica membrane 408 and can not be deep into the inside of silica membrane 408.
S103: the second silicon chip is bonded in above the first silicon chip by silica membrane, forms dangling bonds;
See Fig. 5 d, adopt usual technique, by silica membrane 408 surface, the second silicon chip 406 is overlapped on the first silicon chip 400, the second silicon chip 406 and the first silicon chip 400 are bonded together.The oxygen buried regions of SOI device of described silica membrane 408 in order to serve as subsequent technique and prepare.Because silica membrane surface implants nitrogen-atoms, in bonding process, dangling bonds 412 more can be formed in the interface of silica membrane and the first silicon chip 400 bonding.
S104: the first silicon chip after para-linkage and the second wafer heat, first substrate of the first silicon chip and the second substrate are peeled off from being rich in hydrionic buried regions, thus forming silicon-on-insulator silicon chip, it comprises the second silicon chip and the first wafer sections with the second wafer bonding from top to bottom successively;
See Fig. 5 e, heat-treat after the first silicon chip 400 and the second silicon chip 406 bonding, can impel hydrogen ion at high temperature can nucleation form bubble, the sharply expansion of bubble can be rich in hydrionic buried regions 402 separately the first silicon chip 400, peel off into two parts, wherein a part is for forming soi wafer 414, and described soi wafer 414 comprises the second silicon chip 406 and the first wafer sections with the second silicon chip 406 bonding from top to bottom successively.Wherein, described the first wafer sections be bonded together with the second silicon chip 406 comprises the first substrate 4041 of the first silicon chip 400, and the part buried regions 402 ' below the first substrate 4041.By this step, can thinning soi wafer 414.
S05: prepare the operable silicon-on-insulator silicon chip of subsequent technique on the silicon-on-insulator silicon chip adopting as above method to prepare.
See Fig. 5 f, utilize but be not limited to the techniques such as chemico-mechanical polishing (CMP) and planarization is carried out to soi wafer 414, remove the part buried regions 402 ' below the first substrate 4041, and make the first substrate 4041 in the first silicon chip 400 be thinned to the thickness of technique needs, through above-mentioned steps, prepare for subsequent technique to process the soi wafer 414 ' of the buoyancy aid DRAM cell of PMOS structure.
Finally, see Fig. 6, soi wafer 414 ' is overturn and uses, in the first substrate 4041 of the soi wafer 414 ' prepared, shallow trench isolation is adopted to prepare shallow trench 416 from (STI) technique according to usual technique, its degree of depth extends to silica membrane 408 on the surface, then on the first substrate region 418 that STI isolates, prepare grid 420, grid curb wall 422, source electrode 424 and drain electrode 426 according to usual technique, make the floater effect memory cell of PMOS structure.
Known through Fig. 5 a to Fig. 5 f, SOI device 414 ' prepared by the present invention is owing to have employed DPN method, make the comparision contents of nitrogen-atoms between the surface of the silica membrane 408 in the first substrate 4041 of the first silicon chip 400 and the second silicon chip 406 high, thus form the larger dangling bonds of density 412 at the first substrate 4041 of the first silicon chip 400 with the interface on the surface of silica membrane 408.Compared with the soi wafer 312 ' that the smart cut technique adopted with tradition is formed, at the buoyancy aid dynamic random access memory of the upper PMOS structure manufactured in soi wafer 414 ' basis prepared with DPN method, see Fig. 6, although, the charge carrier that substrate gathers is electronics 428, owing to there are the larger dangling bonds of density 412 in the first substrate region 4041 with the interface on the surface of silica membrane 408, the effective trapped electron 428 of these dangling bonds 412 energy, thus the electronics 428 having certain probability and substrate to gather carries out compound, the electronics 428 that substrate is gathered is not easy to leak from source 424, thus increase the retention time of electronics in the first substrate region 418, improve the data retention energy of PMOS structure floater effect memory cell.
Although the present invention with preferred embodiment openly as above; but it is not for limiting claim; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible variation and amendment, the scope that therefore protection scope of the present invention should define with the claims in the present invention is as the criterion.
Claims (3)
1. a manufacture method for silicon-on-insulator silicon chip, comprises the steps:
Adopt method for implanting to carry out Hydrogen implantation to the first silicon chip, formed in the first silicon chip and be rich in hydrionic buried regions, and form the first substrate, the second substrate respectively at buried regions upper and lower;
Thermal oxidation process is adopted to form silica membrane at the second silicon chip surface;
Decoupled plasma nitridation method is adopted nitrogen-atoms to be implanted to silica membrane surface, to increase the density of the dangling bonds of formation;
Second silicon chip is bonded in above the first silicon chip by silica membrane, forms described dangling bonds;
The first silicon chip after para-linkage and the second wafer heat, first substrate of the first silicon chip and the second substrate are peeled off from being rich in hydrionic buried regions, thus forming silicon-on-insulator silicon chip, it comprises the second silicon chip and the first wafer sections with the second wafer bonding from top to bottom successively;
The silicon-on-insulator silicon chip adopting as above method to prepare is prepared the operable silicon-on-insulator silicon chip of subsequent technique.
2. the manufacture method of silicon-on-insulator silicon chip according to claim 1, is characterized in that: because silica membrane surface implants nitrogen-atoms, can form dangling bonds more in bonding process in the interface of silica membrane and the first wafer bonding.
3. a manufacture method for buoyancy aid DRAM cell, is characterized in that, comprising:
The method of claim 1 is adopted to make silicon-on-insulator silicon chip;
Described silicon-on-insulator silicon chip makes the buoyancy aid DRAM cell of PMOS structure.
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