CN102956267A - Memory programming method and flash memory device using same - Google Patents

Abstract

The invention discloses a memory programming method and a flash memory device using the same. The memory programming method is applied to a flash memory comprising a first memory Plane and a second memory Plane , and comprises the following steps: receiving a programming instruction including a programming logical address; establishing a first Logic-to-Physical (L2P) lookup table to correspond the programmed Logic address to a main storage space in the first memory plane; judging whether the flash memory is operated in a Random Access mode; if yes, establishing a second L2P comparison table to correspond the programming logic address to the backup storage space in the second storage layer; writing the programming data into the main storage space and the backup storage space of the second storage layer at the same time; then judging whether the main storage space is programmed successfully; if not, the address corresponding to the main storage space points to the backup storage space.

Description

Memory programming method and flash memory device using same

technical field

The present invention relates to a memory programming method and a flash memory device using the same, and in particular to a memory programming method for performing error recovery against data programming errors and a flash memory device using the same.

Background technique

In today's era of rapid technological development, non-volatile memory devices are widely used in various electronic products; for example, flash memory is one of the most widely used non-volatile memories. Generally, a memory cell in a flash memory has a programmable threshold voltage, and the programmable threshold voltage is used to indicate the data value stored in the memory cell.

In the data programming operation of the flash memory, a program failure situation occasionally occurs. Accordingly, it is necessary to implement such as Error Correction Code (Error Correction Code, ECC) to perform related reply operations. However, in some serious programming errors, even if the ECC is executed, the failed data cannot be recovered, which will result in data loss. Accordingly, how to propose a more complete programming method for the flash memory to effectively recover the data of the programming failure when the programming failure occurs is one of the continuous efforts of the industry.

Contents of the invention

The present invention relates to a memory programming method and a flash memory device using the same, which is applied to a flash memory with first and second memory planes (Memory Plane). The memory programming method related to the present invention and the flash memory device using it further set up a first Logic-to-Physical (L2P) comparison table to receive received data when the flash memory operates in the random access mode The programming logical address is corresponding to the main storage space in the first memory level, and the second L2P comparison table is established to correspond the programming logical address to the backup storage space in the second memory level, so as to write the programming data into the main storage space at the same time and this backup storage space. When programming failure occurs in the main storage space, the related memory programming method of the present invention and the flash memory device using it can point the address corresponding to the main storage space to the backup storage space, so as to repair the flash memory. Accordingly, compared with the traditional flash memory, the related memory programming method and the flash memory device applied thereto of the present invention can effectively restore the data of programming failure.

According to a first aspect of the present invention, a memory programming method is proposed, which is applied to a flash memory, wherein the flash memory includes a first and a second memory layer (Plane), and the memory programming method includes the following steps: first receiving a programming instruction including a programming logic address; Then establish a first logic-to-physical (Logic-to-Physical, L2P) comparison table to correspond the programming logic address to the main storage space in the first storage layer; then determine whether the flash memory is operated in the Random Access mode; if , establish a second L2P comparison table to correspond the programming logic address to the backup storage space in the second memory level; then program the first and second memory levels simultaneously to write programming data into the main storage space and the second memory level backup storage space; then judge whether the programming of the main storage space is successful; if not, point the address corresponding to the main storage space to the backup storage space.

According to a second aspect of the present invention, a flash memory device is provided, which performs a data programming operation in response to a programming instruction, and the programming instruction includes a programming logic address. The flash memory device includes a flash memory, a register and a memory controller. The flash memory includes first and second memory levels. The register temporarily stores programming data corresponding to the programming instruction. The memory controller establishes the first L2P comparison table in response to the programming instruction, so as to correspond the programming logic address to the main storage space of the first memory level; the memory controller further judges whether the flash memory is operated in the fetch operation mode; if so, then establishes the second The second L2P comparison table corresponds the programming logic address to the backup storage space of the second memory level. The memory controller further programs the first and second memory levels simultaneously to write programming data into the main storage space and the backup storage space. The memory controller further determines whether the programming of the main storage space is successful, and if not, points the address corresponding to the main storage space to the backup storage space.

In order to have a better understanding of the above and other aspects of the present invention, preferred embodiments will be described in detail below together with the accompanying drawings.

Description of drawings

FIG. 1 is a block diagram of a flash memory device according to an embodiment of the present invention.

FIG. 2 is a schematic diagram of operations according to the logic to the entity mapping table L2P_1.

FIG. 3 is a schematic diagram illustrating operations according to the logic to the entity mapping table L2P_2.

FIG. 4 is a flowchart of a memory programming method according to an embodiment of the present invention.

FIG. 5 shows a partial flowchart of a memory programming method according to an embodiment of the present invention.

[Description of main component symbols]

1: Flash memory device

2: Host

10: Flash memory

20: buffer

30: memory controller

10_P1, 10_P2: memory level

Page_M: main storage paging

Page_T: backup storage paging

B(L): Logical memory block

P(L_N)-P(L_N+M): logical memory paging

B(P), B(P_X)-B(P_Z): physical memory block

P(P_N)-P(P_N+M): Physical memory paging

Detailed ways

Please refer to FIG. 1 , which shows a block diagram of a flash memory device according to an embodiment of the present invention. The flash memory device 1 of this embodiment performs a data programming operation in response to a programming command CMD provided by the host 2, and the programming command CMD includes a programming logical address Addr_P. The flash memory device 1 includes a flash memory 10 , a register 20 and a memory controller 30 . The register 20 temporarily stores programming data Data corresponding to the programming command CMD.

The flash memory 10 includes memory planes (Plane) 10_P1 and 10_P2. For example, the memory level 10_P1 includes a plurality of storage blocks (Blocks), and each storage block includes a storage page (Page); the memory level 10_P2 includes backup storage blocks. Furthermore, the storage block is the operation unit of the erase operation (Erase) of the NAND flash memory, and the storage page is the operation unit of the program operation (Program) and the read operation (Read) of the NAND flash memory.

The memory controller 30 establishes a Logic-to-Physical (L2P) mapping table L2P_1 in response to the programming command CMD to map the programming logic address Addr_P to the main storage space in the memory layer 10_P1 . For example, the L2P comparison table L2P_1 is corresponding to the block operation mode (Block Mode), which is used to map the programming logic address Addr_P to the main memory page Page_M in a specific memory block.

For example, the L2P comparison table L2P_1 corresponding to the block operation mode uses a block as a unit to map a logical level page address to a physical memory page, as shown in FIG. 2 . Furthermore, for multiple logical memory pages P(L_N), P(L_N+1), . The entity level also corresponds to multiple physical memory pages P(P_N), P(P_N+1), . . . , P(P_N+M) in the same physical memory block B(P), where N and M is a natural number.

The memory controller 30 further determines whether the flash memory 10 is operating in a Random Access mode. For example, the memory controller 30 determines whether the flash memory 10 is operating in the random fetch operation mode by referring to the programming command CMD and the capacities of the memory levels 10_P1 and 10_P2 .

When the flash memory 10 operates in the random fetch operation mode, the memory controller 30 establishes the L2P mapping table L2P_2 to map the programming logical address CMD to the backup storage space in the memory level 10_P2. For example, the L2P comparison table L2P_2 corresponds to the paging operation mode (Page Mode), which is used to map the programming logic address Addr_P to the temporary storage page Page_T in a temporary storage block Block_T in the memory layer 10_P2. After establishing the L2P comparison tables L2P_1 and LTP_2, the memory controller 30 further programs the memory levels 10_P1 and 10_P2 at the same time, so as to write the programming data Data into the main storage page Page_M of the memory level 10_P1 and into the backup storage page of the memory level 10_p2 Page_T.

For example, the L2P comparison table L2P_2 corresponding to the paging operation mode uses a page as a unit to map the logical level paging address to the physical memory page, as shown in FIG. 3 . Furthermore, for multiple logical memory pages P(L_N), P(L_N+1), . May correspond to some pages P(L_N+1), P(L_N+2), . . . , P(L_N+M) in different memory blocks B(P_X), B(P_Y) and B(P_Z) ), where N and M are natural numbers.

After programming the main memory page Page_M and the backup memory page Page_T, the memory controller 30 further determines whether the main memory page Page_M is programmed successfully. For example, the memory controller 30 refers to the status flag Status to determine whether the program operation of the main storage space Page_M and the backup storage space Page_T fails. When the status flag Status indicates that part or all of the programming operations in the main storage space Page_M and the backup storage space Page_T fail, the memory controller 30 further determines whether the operation in the main storage space Page_M fails.

When the programming of the main storage page Page_M fails, the memory controller 30 points the address corresponding to the main storage page Page_T to the backup storage page Page_T. In other words, when the programming operation of the main memory page Page_M fails, the memory controller 30 corresponds the command for accessing the main memory page to the command for accessing the backup memory page Page_T, thereby providing the programming data Data stored in the backup memory page Page_T to perform bug fixes on flash memory 10.

Similar to the aforementioned operations, the memory controller 30 can simultaneously program the memory levels 10_P1 and 10_P2 according to the L2P comparison tables L2P_1 and L2p_2, so as to simultaneously write the programming data Data corresponding to other main storage pages of the memory level 10_P1 into the memory levels 10_P1. other main storage pages and the corresponding backup storage pages, and when the other main storage pages fail to program, use the data stored in the corresponding backup storage pages to repair them.

In other operation examples, when the flash memory 10 is not operating in the random access operation mode, but for example operates in the sequence operation (Sequential Access) mode, the memory controller 30 writes the programming data Data into the main storage space Page_M of the memory layer 10_P1, and Programming against backing storage paging is not performed.

Please refer to FIG. 4 , which shows a flowchart of a memory programming method according to an embodiment of the present invention. First, as in step (a), the memory controller 30 receives a programming command CMD, which includes a programming logical address Addr_P. Next, as step (b), the memory controller 30 establishes an L2P comparison table L2P_1 to map the programming logic address CMD to the main memory page Page_M in the memory level 10_P1 .

Then as in step (c), the memory controller 30 judges whether the flash memory 10 operates in the random access operation mode; if step (d) is performed, the memory controller 30 establishes an L2P comparison table L2P_2 to correspond the programming logic address Addr_P to the memory level 10_P2 The backup stores pages in Page_T.

Then in step (e), the memory controller 30 simultaneously programs the memory planes 10_P1 and 10_P2 to write the program data Data into the main storage page Page_M of the memory plane 10_P1 and into the backup storage page Page_T of the memory plane 10_P2 .

Then in step (f), the memory controller 30 determines whether the main memory page Page_M is programmed successfully. For example, step (f) includes sub-steps (f1) and (f2), as shown in FIG. 5 . In step (f1), the memory controller 30 refers to the status flag Status to determine whether the programming operation of the main storage page Page_M and the backup storage page Page_T has failed; if step (f2) is performed, the memory controller 30 further determines the main storage page Page_M whether the operation failed.

Step (g) is executed when the programming of the main storage page Page_M fails, and the memory controller 30 directs the address corresponding to the main storage page Page_M to the backup storage page Page_T, so as to perform error repair on the flash memory 10 .

After step (c), when the flash memory 10 is not operating in the fetch operation mode, step (h) is executed, and the memory controller 30 writes the programming data Data into the main storage page Page_M of the memory level 10_P1 without performing backup Operation of memory page Page_T programming.

The memory programming method and the flash memory device using the memory programming method in the embodiment of the present invention are applied in the flash memory having the first and the second memory levels. The memory programming method and the flash memory device using it in the embodiment of the present invention further establish a first L2P comparison table to correspond the received programming logic address to the main memory in the first memory level when the flash memory operates in the random access mode. space, establishing a second L2P comparison table to map the programming logic address to the backup storage space in the second memory level, and accordingly write programming data into the main storage space and the backup storage space at the same time. When programming failure occurs in the main storage space, the memory programming method of the embodiment of the present invention and the flash memory device using it can point the address corresponding to the main storage space to the backup storage space, so as to repair the flash memory. Accordingly, compared with the traditional flash memory, the memory programming method of the embodiment of the present invention and the flash memory device using the same can effectively recover the data that fails to be programmed.

To sum up, although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Those skilled in the art of the present invention can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be defined by the appended claims.

Claims (10)

1. A memory programming method, applied to a flash memory, wherein the flash memory includes a first memory level (Plane) and a second memory level, the memory programming method comprising: receiving a programming instruction, including a programming logic address; Establishing a first logic-to-physical (Logic-to-Physical, L2P) comparison table, so as to correspond the programming logic address to a main storage space in the first memory level; Judging whether the flash memory operates in a Random Access mode; When the flash memory is operated in the fetch operation mode, a second L2P comparison table is established to correspond the programming logic address to a backup storage space in the second memory level; and The first and the second memory levels are programmed simultaneously to write a programming data into the main storage space of the first memory level and into the backup storage space of the second memory level. 2. The memory programming method according to claim 1, wherein when the flash memory is not operating in the fetch operation mode, perform: The programming data is written into the main storage space of the first memory level. 3. The memory programming method according to claim 1, wherein the step of judging whether the main storage space is successfully programmed further comprises: Referring to a status flag, it is judged whether the programming operation of the main storage space and the backup storage space fails; and When the status flag indicates that the programming operation of the main storage space and the backup storage space is failure, it is judged whether the operation of the main storage space fails. 4. The memory programming method according to claim 1, further comprising: It is judged whether the programming of the main storage space is successful. 5. The memory programming method according to claim 4, further comprising: When the programming of the main storage space fails, point the address corresponding to the main storage space to the backup storage space. 6. A flash memory device that performs a data programming operation in response to a programming command, the programming command includes a programming logical address, the flash memory device comprising: A flash memory, including a first memory level (Plane) and a second memory level; a register for temporarily storing a program data corresponding to the program command; and A memory controller, in response to the programming instruction, establishes a first logic-to-physical (Logic-to-Physical, L2P) comparison table, so as to correspond the programming logic address to a main storage space in the first memory level, the The memory controller further determines whether the flash memory operates in a Random Access mode; Wherein, when the flash memory operates in the fetch operation mode, the memory controller establishes a second L2P comparison table to correspond the programming logic address to a backup storage space in the second memory level, the memory controller Furthermore, the first and the second memory levels are programmed simultaneously to write the program data into the main storage space of the first memory level and into the backup storage space of the second memory level. 7. The flash memory device according to claim 6, wherein when the flash memory is not operating in the random access operation mode, the memory controller writes the programming data into the main storage space of the first memory level. 8. The flash memory device according to claim 6, wherein the memory controller refers to a status flag to determine whether the programming operation of the main storage space and the backup storage space fails; When the status flag indicates that the programming operations of the main storage space and the backup storage space fail, the memory controller further determines whether the operation of the main storage space fails. 9. The flash memory device according to claim 6, wherein the memory controller further determines whether the main storage space is programmed successfully. 10. The flash memory device according to claim 9, wherein when the programming of the main storage space fails, the memory controller points the address corresponding to the main storage space to the backup storage space.

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