CN102931116B - Synchronous defect detecting method for memorizer - Google Patents
Synchronous defect detecting method for memorizer Download PDFInfo
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- CN102931116B CN102931116B CN201210451663.6A CN201210451663A CN102931116B CN 102931116 B CN102931116 B CN 102931116B CN 201210451663 A CN201210451663 A CN 201210451663A CN 102931116 B CN102931116 B CN 102931116B
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Abstract
The invention provides a synchronous defect detecting method for a memorizer. The method includes the following steps: (1) operating a structure extraction step used for extracting minimum repetition structures in memorizer areas in different directions on the chip, (2) operating a scanning step used for scanning a complete array or a row of chipsets and storing data information of the chipset in a database, (3) operating a data comparing step used for comparing data collected through the scanning step along the horizontal and perpendicular directions according to a unit structure defined through the structure extraction step, (4) repeating the scanning step and the data comparing step until defect detection of a whole wafer is finished. By means of the synchronous defect detecting method, the defect detection can be carried out to the memorizers of different directions and cycles in the same detection process so that fast scanning can be achieved and detection precision of each memorizer area can be well controlled.
Description
Technical field
The present invention relates to semiconductor fabrication process, more particularly, the present invention relates to the synchronous defect inspection method of a kind of memory.
Background technology
Along with the development of design and manufaction technology, integrated circuit (IC) design develops into the integrated of gate from the integrated of transistor, develops into again the integrated of IP now, and the integrated level of chip is more and more higher.The general defects detection that all can relate to optics in the chip manufacturing proces of advanced person, the basic functional principle of defects detection the optical imagery on chip is converted into the data image that can be represented by the bright dull gray rank of difference, picture signal comparison is carried out while scanning, what Fig. 1 represented is exactly will obtain the process that image P1 is converted into data image feature P2 under a light microscope, the position of defect is relatively detected again by the data in adjacent chips, what represent as Fig. 2 is the comparison of the adjacent chips of X1 in the horizontal direction, the ratio of the adjacent chips of X2 in the vertical direction that what Fig. 3 represented is.
But, chip is integrated with a lot of functional modules, as microprocessor/microcontroller, memory and other specialized functional logic districts etc., particularly memory module is due to place the highest on its pattern density often whole chip, so some trickle graphic difference or minimum outer boundry particle all can cause the inefficacy of whole chip electrical property as shown at right.Analyze from the graphic designs of memory, its figure has in the horizontal or vertical directions periodically repetitive structure, current detection method is on chip, be divided in the minimum unit structure that horizontal or vertical direction has repeatability, each repetitive structure itself and contiguous unit carry out data and compare, but as mentioned above, the scanning of horizontal or vertical direction can only be accomplished in a testing process, in a testing process, the defects detection of both direction memory construction can not be completed simultaneously.
Summary of the invention
Technical problem to be solved by this invention is for there is above-mentioned defect in prior art, provide a kind of can realize rapid scanning while can control again the synchronous defect inspection method of memory of the accuracy of detection of each memory area well.
In order to realize above-mentioned technical purpose, according to the present invention, provide the synchronous defect inspection method of a kind of memory, it comprises: first perform the structure extraction step of memory areas repetitive structure being used for different directions on extraction chip simultaneously; Then perform for scanning a complete column or row chipset and the data message of chipset being kept at the scanning step of database; After this cellular construction performed for defining according to structure extraction step carries out the data comparison step of the comparison on horizontal and vertical direction to the data message gathered by scanning step; After this, multiple scanning step and data comparison step, until complete the defects detection of whole wafer.
Preferably, described different directions is two mutually perpendicular directions.
Preferably, described different directions is horizontal direction and vertical direction.
Preferably, when completing the defects detection of whole wafer, scanning the comparison that the whole wafer that is over completes all data simultaneously, obtaining a defect map.
Preferably, described memory areas repetitive structure is minimum memory areas repetitive structure.
Preferably, described data message is graphical information.
By utilizing the synchronous defect inspection method of memory of the present invention, in same testing process, the detection of defect can be carried out the memory construction with the different directions cycle, thus the accuracy of detection of each memory area while realizing rapid scanning, can be controlled again well.
Accompanying drawing explanation
By reference to the accompanying drawings, and by reference to detailed description below, will more easily there is more complete understanding to the present invention and more easily understand its adjoint advantage and feature, wherein:
Fig. 1 schematically shows the schematic diagram that circuit optical imagery is converted into data gray scale image.
Fig. 2 schematically shows the schematic diagram of horizontal direction defects detection.
Fig. 3 schematically shows the schematic diagram of vertical direction defects detection.
Fig. 4 schematically shows horizontal direction memory repetitive structure figure.
Fig. 5 schematically shows vertical direction memory repetitive structure figure.
Fig. 6 schematically shows the flow chart according to the synchronous defect inspection method of embodiment of the present invention memory.
It should be noted that, accompanying drawing is for illustration of the present invention, and unrestricted the present invention.Note, represent that the accompanying drawing of structure may not be draw in proportion.Further, in accompanying drawing, identical or similar element indicates identical or similar label.
Embodiment
In order to make content of the present invention clearly with understandable, below in conjunction with specific embodiments and the drawings, content of the present invention is described in detail.
In embodiments of the present invention, first extracting the information of on-chip memory region repetitive structure, being saved in checkout equipment by comprising the minimum unit structure that horizontal and vertical direction is repeated respectively.Such as, as shown in Figure 4 and Figure 5, the minimum unit structure that horizontal and vertical direction is repeated comprises horizontal direction memory repetitive structure as shown in Figure 4: unit Y1, unit Y2, unit Y3, and vertical direction memory repetitive structure as shown in Figure 5: unit X1, unit X2, unit X3.
When scanning chip, the figure signal collected is saved in a certain database, until complete the collection of horizontal or vertical direction lastrow or row complete chip set signal, then while next row or column chipset is scanned to the comparing that the graphical information being stored in one group of complete chip in certain database is carried out in the horizontal and vertical directions.
Fig. 6 schematically shows the flow chart according to the synchronous defect inspection method of embodiment of the present invention memory.
As shown in Figure 6, comprise according to the synchronous defect inspection method of embodiment of the present invention memory:
When program starts, first, wafer 1 is put into checkout equipment 2 to detect;
Subsequently, the information (step 3) of the memory area repetitive structure of the chip in wafer 1 is extracted;
Subsequently, the complete chip of first group of horizontal or vertical direction is scanned, and the information of whole core assembly sheet is preserved in a database (step 4);
On the one hand, the information of whole core assembly sheet is carried out the comparison (step 6) in horizontal and vertical direction according to the memory construction of setting; On the other hand, next core assembly sheet is scanned (step 5);
Finally, scan the comparison that complete wafer completes all data simultaneously, thus obtain a defect map (step 7).
EP (end of program) subsequently.
By utilizing the synchronous defect inspection method of the memory of the embodiment of the present invention, in same testing process, the detection of defect can be carried out the memory construction with the different directions cycle, thus the accuracy of detection of each memory area while realizing rapid scanning, can be controlled again well.
Such as, for embody rule, the periodic structure in the different memory region on the good chip of definable (preferably, minimum memory repetitive structure), start to scan the complete chip of first group of horizontal or vertical direction of wafer, and the information (such as graphical information) of a whole core assembly sheet is preserved in a database, the information of the whole core assembly sheet scanned is carried out the comparison in horizontal and vertical direction while next core assembly sheet is scanned according to the memory construction of setting, until complete the detection of whole wafer, thus the accuracy of detection of each memory area while realizing rapid scanning, can be controlled again well.
In a specific embodiment, such as, the structure extraction step of the minimum repetitive structure in memory areas being used for different directions (preferably two mutually perpendicular directions, such as horizontal direction and vertical direction) on extraction chip simultaneously is first performed; Then perform for scanning a complete column or row chipset and the data message of chipset being kept at the scanning step of database; After this cellular construction performed for defining according to structure extraction step carries out the data comparison step of the comparison on horizontal and vertical direction to the data gathered by scanning step; After this, multiple scanning step and data comparison step, until complete the defects detection of whole wafer.
Be understandable that, although the present invention with preferred embodiment disclose as above, but above-described embodiment and be not used to limit the present invention.For any those of ordinary skill in the art, do not departing under technical solution of the present invention ambit, the technology contents of above-mentioned announcement all can be utilized to make many possible variations and modification to technical solution of the present invention, or be revised as the Equivalent embodiments of equivalent variations.Therefore, every content not departing from technical solution of the present invention, according to technical spirit of the present invention to any simple modification made for any of the above embodiments, equivalent variations and modification, all still belongs in the scope of technical solution of the present invention protection.
Claims (6)
1. the synchronous defect inspection method of memory, is characterized in that comprising: first perform the structure extraction step of memory areas repetitive structure being used for different directions on extraction chip simultaneously; Then perform for scanning a complete column or row chipset and the data message of chipset being kept at the scanning step of database; After this cellular construction performed for defining according to structure extraction step carries out the data comparison step of the comparison on horizontal and vertical direction to the data message gathered by scanning step; After this, multiple scanning step and data comparison step, until complete the defects detection of whole wafer.
2. the synchronous defect inspection method of memory according to claim 1, is characterized in that, described different directions is two mutually perpendicular directions.
3. the synchronous defect inspection method of memory according to claim 1 and 2, is characterized in that, described different directions is horizontal direction and vertical direction.
4. the synchronous defect inspection method of memory according to claim 1 and 2, is characterized in that, when completing the defects detection of whole wafer, scanning the comparison that the whole wafer that is over completes all data simultaneously, obtaining a defect map.
5. the synchronous defect inspection method of memory according to claim 1 and 2, is characterized in that, described memory areas repetitive structure is minimum memory areas repetitive structure.
6. the synchronous defect inspection method of memory according to claim 1 and 2, is characterized in that, described data message is graphical information.
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Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103336239B (en) * | 2013-06-03 | 2016-12-28 | 上海华虹宏力半导体制造有限公司 | The method of wafer sort |
| CN103604814A (en) * | 2013-10-23 | 2014-02-26 | 上海华力微电子有限公司 | Detection method for chip defect |
| CN104062305B (en) * | 2014-07-28 | 2017-10-03 | 上海华力微电子有限公司 | A kind of analysis method of integrated circuit defect |
| CN104157309B (en) * | 2014-08-20 | 2017-12-15 | 上海华力微电子有限公司 | The detection device and detection method of static memory |
| CN104332422A (en) * | 2014-09-01 | 2015-02-04 | 上海华力微电子有限公司 | Defect detection method of integrated circuit layouts in different directions |
| CN109994398A (en) * | 2019-04-18 | 2019-07-09 | 上海华力微电子有限公司 | A kind of wafer defect scanning control methods |
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| CN1182921A (en) * | 1996-09-17 | 1998-05-27 | 株式会社日立制作所 | Graph testing method and device |
| CN1497697A (en) * | 2002-10-07 | 2004-05-19 | 株式会社瑞萨科技 | Checking method of semiconductor chip |
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