CN102890970B

CN102890970B - POP (Post Office Protocol) packaged SOC (System on Chip) DRAM (Dynamic Random Access Memory) input/output test method and device

Info

Publication number: CN102890970B
Application number: CN201110205287.8A
Authority: CN
Inventors: 丁杰; 鲍东山
Original assignee: GUANGZHOU NUFRONT COMPUTER SYSTEM CHIP CO Ltd
Current assignee: GUANGZHOU NUFRONT COMPUTER SYSTEM CHIP CO Ltd
Priority date: 2011-07-21
Filing date: 2011-07-21
Publication date: 2017-04-19
Anticipated expiration: 2031-07-21
Also published as: CN102890970A

Abstract

The invention discloses POP (Post Office Protocol) packaged SOC (System on Chip) DRAM (Dynamic Random Access Memory) input/output test method and device. On the basis of simple abstraction of IO (Input/Output), a return circuit is naturally formed, so that the SOC test of DRAMIO (Dynamic Random Access Memory Input/Output) during the POP packaging is possible; and an IOBIST (Input/Output Built-in Self Test) module is utilized, so that the test result is output to the bottom of an SOC through GPIO (General Purpose Input/Output) and then the test purpose is realized. According to the test method and device provided by the invention, the problem that the DRAMIO is not located at the lower part of the chip during the POP packaging and thus the direct test cannot be obtained is solved, so that the SOC packaging cost of the POP packaging is reduced and the speed is accelerated.

Description

A kind of SOC DRAM input/output method of testing and device of POP encapsulation

Technical field

The invention belongs to technical field of integrated circuits, more particularly to a kind of SOC DRAM input/output of POP encapsulation Method of testing and device.

Background technology

At present POP (Package on package) encapsulation technologies encapsulate DRAM in consumer-elcetronics devices such as mobile phones It is widely used during (Dynamic Rand Access Memory) chip, is that dram chip is encapsulated in SOC (System on Chip) on chip, as shown in Figure 1.In the prior art, when testing chip, entered to encapsulating the SOC for completing Row functional test, and for the POP chips that complete of encapsulation, when needing to carry out SOC IO (Input/output) to test, but ten Divide trouble.On the one hand, DRAM I/O pins are a kind of selection below SOC, but pin is below, and SOC IO can be caused to increase, So that package area increase, due to cost consideration, package area is not too big, therefore DRAM IO can not go out below.The opposing party Face, DRAM I/O pins are on SOC, but if pin is on SOC, during packaging and testing DRAM IO, it is difficult to SOC cores Piece carries out direct IO tests.

The content of the invention

In view of this, the technical problem to be solved is in POP encapsulation, DRAM IO to be gone out in chip top In the case of, complete to be tested with regard to the IC of SOC, for this purpose, a kind of SOC DRAM input of POP encapsulation of present invention offer/defeated Go out method of testing and device.In order to have a basic understanding to some aspects for the embodiment for disclosing, shown below is simple Summary.The summarized section is not extensive overview, nor to determine key/critical component or describe these embodiments Protection domain.Its sole purpose is that some concepts are presented with simple form, in this, as the preamble of following detailed description.

It is an aspect of the present invention to provide a kind of SOC DRAM input/output test device of POP encapsulation, including：

Built-in self-test module I OBIST being connected with DRAM IO in SOC, the IOBIST be used for send check code to DRAM IO；

The IOBIST receives and checks the check code after returning；

Universal input/output module GPIO is connected with IOBIST, and the GPIO is used to judge that check code Yes/No is identical, really Determine DRAM IO pass/fails；

Wherein, DRAM IO are made up of two three state buffers, and during output, OE gatings, the value of DO is just appeared on I/O, During input, OE is closed, and the value of I/O is appeared on DI.

In some optional embodiments, described check code is parity check code or pre-stored values check code.

In some optional embodiments, described DRAM IO include：

Option cartoon input OE is connected with control circuit, and the OE ends keep high level；

Input DO is connected with the IOBIST, and the DO ends are used to receive the check code；

Outfan DI is connected with the IOBIST, and the DI ends are used to return the check code.

Another aspect of the present invention is to provide a kind of SOC DRAM input/output method of testing of POP encapsulation, and it is special Levy and be, including：

Built-in self-test module I OBIST sends check code to DRAM IO；

The IOBIST receives and checks the check code after returning；

Universal input/output module GPIO judges that check code Yes/No is identical, determines DRAM IO pass/fails；

In some optional embodiments, in described DRAM IO：

Option cartoon input OE keeps high level；

Input DO receives the check code；

Outfan DI returns the check code.

Figure of description

Fig. 1 is POP encapsulation schematic diagrams；

Fig. 2 is the test device schematic diagram of the present invention；

Fig. 3 is three buffer schematic diagrams of DRAM IO；

Fig. 4 is three buffer schematic diagrams of DRAM IO；

Fig. 5 is the method for testing flow chart of the present invention.

Specific embodiment

The following description and drawings fully illustrate specific embodiments of the present invention, to enable those skilled in the art to Put into practice them.Other embodiments can include structure, logic, it is electric, process and it is other changes.Embodiment Only represent possible change.Unless explicitly requested, otherwise single component and function are optional, and the order for operating can be with Change.The part of some embodiments and feature can be included in or replace part and the feature of other embodiments.This The scope of bright embodiment includes the gamut of claims, and all obtainable equivalent of claims Thing.Herein, these embodiments of the invention individually or generally can be represented with term " invention " that this is only For convenience, and if in fact disclosing the invention more than, it is not meant to automatically limit the scope of the application to appoint What single invention or inventive concept.

In some optional embodiments, the SOC DRAM input/output test device of POP encapsulation, including：

The IOBIST receives and checks the check code after returning；

Universal input/output module GPIO is connected with IOBIST, and the GPIO is used to judge that check code Yes/No is identical, really Determine DRAM IO pass/fails.

Wherein, described DRAM IO include：

As shown in figure 3, the composition of DRAM IO is made up of two three state buffers, and during output, OE gatings, the value of DO will Occur on I/O, during input, OE is closed, and the value of I/O is just embodied on DI.

I/O is not exposed in POP encapsulation, if control OE is always height, DRAM IO are equivalent to a DO and arrive The loop (loopback) of DI, as shown in Figure 4.

Therefore, in SOC, CPU is controlled always and sends out the operation for writing Memory, or some verifications are sent out by IO BIST modules To PAD, all data write, address and order appear at DO to code, also due to OE is gated always (open during write operation), it is actual What upper DI occurred also should be exactly the value of DO.If it is observed that the value of DI is not the value of DO, it is have scarce to turn out this DRAM IO Sunken.The purpose of test DRAM IO is reached with this.

As shown in Fig. 2 all of DI ends of DRAM IO all enter IO BIST modules.By the module come comparative observation to DI It is whether identical with DO.Test completes to export " Done " " Fail " two signals, to 2 GPIO (going out face under the die), complete with this Test.

In some optional embodiments, as shown in figure 5, a kind of SOC DRAM input/output test of POP encapsulation Method, including：

S01：Built-in self-test module I OBIST sends check code to DRAM IO；

S02：The IOBIST receives and checks the check code after returning；

S03：Universal input/output module GPIO judges that check code Yes/No is identical, determines DRAM IO pass/fails.

In some optional embodiments, in described DRAM IO：

Option cartoon input OE keeps high level；

Input DO receives the check code；

Outfan DI returns the check code.

Even-odd check：The value of DO can be control, allow whole cycle testss value even-odd check all, allow test As a result it is a level signal, for observing in GPIO.

Pre-stored values：The value of DO is placed in the SRAM of " IO BIST " as pre-stored values, and the DI in each cycle does with pre-stored values Relatively.Cycle testss terminate, and output results to GPIO.

Described above includes the citing of one or more embodiments.Certainly, in order to above-described embodiment is described and description portion The all possible combination of part or method is impossible, but it will be appreciated by one of ordinary skill in the art that each enforcement Example can do further combinations and permutations.Therefore, embodiment described herein is intended to fall into appended claims Protection domain in all such changes, modifications and variations.Additionally, with regard to the term used in description or claims "comprising", the word covers mode similar to term " including ", just as " including, " solved as link word in the claims As releasing.Additionally, the use of any one term "or" in the description of claims being to represent " non-exclusionism Or ".

Claims

1. the SOC DRAM input/output test device that a kind of POP is encapsulated, it is characterised in that include：

Built-in self-test module I OBIST being connected with DRAM IO in SOC, the IOBIST is used to send check code to DRAM IO；

The IOBIST receives and checks the check code after returning；

Universal input/output module GPIO is connected with IOBIST, and the GPIO is used to judge that check code Yes/No is identical, it is determined that DRAM IO pass/fails；

Wherein, DRAM IO are made up of two three state buffers, during output, option cartoon input OE gatings, and the value of input DO Just appear on I/O, during input, OE is closed, and the value of I/O is appeared on outfan DI.

2. device as claimed in claim 1, it is characterised in that described check code is parity check code or pre-stored values verification Code.

3. device as claimed in claim 1, it is characterised in that described DRAM IO include：

The option cartoon input OE is connected with control circuit, and the OE ends keep high level；

The input DO is connected with the IOBIST, and the DO ends are used to receive the check code；

The outfan DI is connected with the IOBIST, and the DI ends are used to return the check code.

4. the SOC DRAM input/output method of testing that a kind of POP is encapsulated, it is characterised in that include：

Built-in self-test module I OBIST sends check code to DRAM IO；

The IOBIST receives and checks the check code after returning；

Universal input/output module GPIO judges that check code Yes/No is identical, determines DRAM IO pass/fails；Wherein, DRAM IO is made up of two three state buffers, and during output, option cartoon input OE gatings, the value of input DO just appears in I/O On, during input, OE is closed, and the value of I/O is appeared on outfan DI.

5. method as claimed in claim 4, it is characterised in that described check code is parity check code or pre-stored values verification Code.

6. method as claimed in claim 4, it is characterised in that in described DRAM IO：

The option cartoon input OE keeps high level；

The input DO receives the check code；

The outfan DI returns the check code.