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CN102823337A - 具有固定的底部填充的电路板 - Google Patents

具有固定的底部填充的电路板 Download PDF

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Publication number
CN102823337A
CN102823337A CN2011800132791A CN201180013279A CN102823337A CN 102823337 A CN102823337 A CN 102823337A CN 2011800132791 A CN2011800132791 A CN 2011800132791A CN 201180013279 A CN201180013279 A CN 201180013279A CN 102823337 A CN102823337 A CN 102823337A
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CN
China
Prior art keywords
solder mask
circuit board
opening
solder
semiconductor chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN2011800132791A
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English (en)
Inventor
罗登·托帕西欧
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ATI Technologies ULC
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ATI Technologies ULC
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Publication date
Application filed by ATI Technologies ULC filed Critical ATI Technologies ULC
Publication of CN102823337A publication Critical patent/CN102823337A/zh
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3452—Solder masks
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/36—Assembling printed circuits with other printed circuits
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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Abstract

公开了各种电路板和利用该电路板的制造方法。一方面，提供一种制造方法，其包括在电路板（20）的面（17）上施加焊接掩膜（90）和在焊接掩膜（90）中形成至少一个通向所述面（17）的开口（105）。将底部填充（25）定位在阻焊膜（90）上以使其中的一部分（100）突入至少一个开口（105）中。

Description

具有固定的底部填充的电路板
技术领域
本发明总体涉及半导体工艺，尤其涉及半导体芯片焊料凸块焊盘（solder bump pads）和制造所述焊盘的方法。
背景技术
倒装芯片（flip-chip）安装方案已被使用了几十年，用以安装半导体芯片到电路板上，诸如半导体芯片封装基底。在许多传统倒装芯片改变的方案中，在半导体芯片的输入/输出（I/O）位置和相应的电路板的I/O位置之间建立了多个焊接节点。在一个传统工艺中，焊料凸块金相地结合到给定的I/O位置或者该半导体芯片的焊盘上和所谓的预焊料金相地结合到该电路板的相应的I/O位置。随后焊料凸块和预焊料达到接近并承受热处理，该热处理重熔（reflow）焊料凸块和该预焊料中的一个或者两个以确定所需焊接点。
倒装芯片焊接点可受到来自各种来源的机械应力，诸如热膨胀系数（CTE）不匹配、延展性差异和电路板翘曲。这些应力会使上述的传统的焊接点受到弯曲力矩。该影响在某种程度上是定向的，其中应力在接近芯片边缘和角落趋向最大且随着靠近芯片中心而减少。
为了减缓CTE不匹配的影响，底部填充材料通常定位在芯片和下伏封装基底之间，尤其定位在芯片和封装基底上的阻焊层之间。与焊接点相似，就连底部填充也可受到弯曲力矩。当足够严重时或者当底部填充到阻焊层的结合部分地变弱时，会发生分层（delamination）。底部填充分层会导致在焊接点中形成开裂并最终导致器件失效。
传统的设计依赖在焊接掩膜的相对光滑的表面和底部填充之间粘结结合的强度。应力可能会超过该结合。另一种传统的设计利用等离子体蚀刻工艺使焊接掩膜的上表面变粗糙以增强该粘结结合。该粗糙度通常仅透入少于一微米。还有另外一种技术基于在底部填充沉积之前进行焊接掩膜的额外的清洁。在最后一个技术中，粘结结合到光滑的表面也是所述目的。
本发明旨在直接克服或减少一个或多个前述缺点的影响。
发明内容
依照本发明的实施例的一个方面，提供一种制造方法，其包括在电路板的面上施加焊接掩膜和在该焊接掩膜中形成至少一个通向所述面上的开口。在该焊接掩膜上定位底部填充以便其中的部分突进至少一个开口中。
依照本发明的实施例的另一方面，提供一种耦接半导体芯片到电路板的方法，其包括在电路板的面上施加焊接掩膜和在焊接掩膜中形成多个通向所述面上的开口。使所述半导体芯片耦接到所述电路板的所述面以留出空隙。使底部填充位于所述空隙上以便其中的部分突进每个所述开口中。
依照本发明的实施例的另一方面，提供一种装置，其包括包含面的电路板。焊接掩膜位于所述面上并且包括至少一个通向该面的开口。底部填充位于焊接掩膜上和包括突进所述至少一个开口中的部分。
附图说明
通过阅读下面的详细说明以及参照附图，本发明的前述优点以及其他优点将变得显而易见，在附图中：
图1是半导体芯片器件的示例性实施例的示意图，该半导体芯片器件包括安装在电路板上的半导体芯片；
图2是图1在截面2-2上的截面图；
图3是图2的部分的放大图；
图4是在截面4-4上的图3的部分的截面图；
图5是与图4类似的剖视图，但是其描绘了替代的示例性的焊接掩膜和底部填充构型；
图6是描绘了位于示例性焊接掩膜上的示例性非接触掩膜的截面图；
图7是与图6类似的截面图，但是描绘了焊接掩膜的光刻曝光过程；
图8是与图7类似的截面图，但是描绘了焊接掩膜的显影以在其中产生选择性开口；
图9是与图8类似的截面图，但是描绘了在焊接掩膜上焊料结构的安置；
图10是与图9类似的截面图，但是描绘了底部填充的安置；以及
图11是与图4类似的截面图，但是以较小的放大率描绘的。
具体实施方式
本文描述了诸如半导体芯片封装基底之类的印制电路板的各个实施例。一个示例包括焊接掩膜，其被图形化具有一个或者多个通向电路板的面上的开口。位于该焊接掩膜上的底部填充包括突入开口的部分并形成机械接点以增强强度并抑制底部填充分层。现在将对额外的细节进行说明。
在下文所述的附图中，当相同的元件出现在多于一个的图中时，附图标识一般就重复。现在转到附图，尤其转到图1，其中示出了示例性的常规半导体芯片器件10的示意图，其包括安装到电路板20的面17上的半导体芯片15。底部填充材料层25位于半导体芯片15和电路板20之间。半导体芯片15可为用在电子中的任何的各式各样的不同类型的电路组件，诸如，例如微处理器，图形处理器、微处理器/图形处理器组合、特定集成电路应用，存储器等等，且可为单核或多核或者额外晶粒（dice）堆叠。半导体芯片15可由体型半导体（bulk semiconductor）构成，诸如硅或锗，或者绝缘体上半导体材料，诸如绝缘体上硅材料。半导体芯片15可倒装地安装到电路板20上并通过焊接点或其他结构电连接到其上（在图1中是不可见的但在接下的附图中所示）。
电路板20可为半导体芯片封装基底、电路卡、或实际上任何类型的印刷电路板。尽管单片结构可用于电路板20，更为典型的配置将利用增层（build-up）设计。在这方面，电路板20可由其上形成有一个或者多个增层以及其下形成有额外的一个或者多个增层的中央核心组成。该核心自身由一个或者多个层的堆叠组成。这样构型的一个示例可称为所谓的2-2-2构型，其中单层核心叠夹在两组的两个增层之间。当执行作为半导体芯片封装基底，电路板20中的层数可从四变化到十六或者更多，尽管也可利用少于四层。也可利用所谓的“无核”设计。电路板20的层可由绝缘材料组成，该绝缘材料诸如加入金属互连的各种公知的环氧树脂（epoxies）。除了使用增层还可使用多重层的构型。可选地，电路板20可由公知的陶瓷或者适于封装基底或者其他印刷电路板的其他材料组成。
半导体芯片器件10的额外的细节将结合图2描述，图2为图1在截面2-2方向上的截面图。在转到图2之前，知道截面所示的封装10的局部的确切位置是有帮助的。注意到截面2-2穿过包括边界30的半导体芯片15的小部分。了解这些背景，现在将注意力转到图2。在电路板20上提供具有多个导体轨迹（trace）和通孔以及其他结构以在半导体芯片15和其他未示出的电路装置之间提供能量，接地位和信号传输。为了促进这些传输，封装板20提供所示球栅阵列33形式的输入/输出，或者插针栅阵列，网格栅阵列或其他类型的互连体系。如上所述，半导体芯片15可配置为体型半导体或者绝缘体上硅构造。在该解说性的实施例中，半导体芯片15执行为包括体型半导体层35和半导体器件层40的体型半导体。半导体器件层40包括为半导体芯片15提供功能的多种电路，并且通常包括多个金属化和/或方便传输到半导体芯片15或者从半导体芯片15中传输出功率接地和信号的其他类型的导体层。介电叠夹层（laminate layer）45形成在半导体器件层40上，且可由多层绝缘材料组成，在示例性实施例中，介电堆叠可由例如替代二氧化硅和氮化硅层组成。然而，这些或其它绝缘材料之一的单片结构可用于叠层的替代。
半导体芯片可倒装地安装到电路板20的面17上以留出空隙47且通过多个焊料结构或者焊接点的方式电气连接到该面，该焊料结构的其中两个是可见的并分别标识为50和55。由于截面2-2的定位，仅有部分的焊接点55是可见的。对焊接点50的以下的描述也是对其他焊接点的例解。焊接点50包括焊料结构或者凸块60，其金相地结合到另外的有时称为预焊料的焊料结构65。焊料凸块60和预焊料65通过焊接回流工艺金相地连接。不规则连线70表示在回流工艺后焊料凸块60和预焊料65之间的假设的边界。然而，熟练的技术人员将理解该边界70甚至在显微镜观测中也不大容易可见。焊料凸块60可由多种的铅基焊料或无铅焊料组成。一个示例性的铅基焊料可具有组分是或接近共熔比例为，诸如大约63%的锡和37%的铅。无铅焊料的示例包括锡-银（大约97.3%的锡和2.7%的银），锡-铜（大约99%的锡和1%的铜），锡-银-铜（大约96.5%的锡和3%的银和0.5%的铜）或类似的组成。预焊料65可由相同类型的材料组成。可选地，可免除使用预焊料65，以有利于单一焊料结构或焊料结构加上导体柱构型。焊料凸块60可金相地连接到导体结构75，其可称为凸块下金属化结构或者UBM结构。在本文其他地方更细节的描述中，可提供具有阶梯构型的UBM结构75，该阶梯构型提供对各种应力和弯曲力矩的改善的抵抗。随后，UBM结构75电气连接到在芯片15中的另外的导体结构或者焊盘，其标识为80且可为半导体芯片15中的多个金属化层的部分。导体结构80可称为重新分配层或者RDL结构。导体结构80可用于功率、接地或者信号的输入/输出站或者用于并未与其他的结构电连接的伪焊盘。预焊料65相似地金相地焊接到被焊接掩膜90横向框边的导体85。导体85可形成多层导体结构的部分并由通孔互连且由介电材料层围绕。
底部填充材料层25分布在半导体芯片15和基底20之间，特别地在半导体芯片15和焊接掩膜90之间以减少半导体芯片15、焊接点50、55等和电路板20之间的热膨胀系数（CTE）差异的影响。在所需情况下底部填充25可延伸到或经过焊接掩膜的边缘97。底部填充材料层25可以例如是混合二氧化硅填料的环氧树脂和酚醛树脂，并且在回流焊工艺之前或之后淀积该材料层以生成焊接点50和55。多种物理过程可在底部填充25和阻焊膜90之间的结合上导致巨大的应力。在热循环中半导体芯片15、电路板20和底部填充材料层25之间的应变率的差异造成了一部分的该应力。另一个导致差异应力的因素可为在焊料凸块60和预焊料65之间的延展度的差异。由于公知的边缘效应的现象，该差异应力和合成应变可最接近半导体芯片15的边缘30，且可逐步地沿箭头92的指向减少，该箭头从边缘30伸向半导体15的中央。
底部填充材料层25通过粘性力方式粘附在焊接掩膜90的上表面95上。然而，底部填充25从焊接掩膜90的分层通过跨装焊接点50的底部填充突点（projection）得到额外的限制。底部填充突点的其中一个标识为100。底部填充突点100和尚未标识的其他的突点通过在焊接掩膜90中形成开口而确立，诸如开口105。底部填充25、突点100和开口105等的额外的细节可通过现在参照图3得到理解，图3是在更大的放大率下用虚线椭圆110圈出的图2的一部分的示意图。在图3中电路板20的部分、导体焊盘85、焊接点50的预焊料65的部分以及焊接掩膜90的部分和底部填充25是可见的。在该截面图中，不仅底部填充25的突点100是可见的，定位于在焊接掩膜90上的相应开口130、135和140中的突点115、120和125也是可见的。如上所述，突点100定位于在焊接掩膜中的开口105中。由于与焊接掩膜90化学结合，以及抵抗底部填充25相对于焊接掩膜90的转动的力矩的机械连接，突点100、115、120和125对底部填充25提供从焊接掩膜90的分层的额外的抗力。实质上，给定突点的横向的边缘或者边界，诸如突点100，顶住反向的焊接掩膜90的开口105的横向的边缘或边界。该效应与合作配件之间的过盈配合相似。
应当理解突点100、115、120和125的数量和形状可有很大变化。在这方面，现在将注意力转到图4，图4是图3在截面4-4上所示的截面图。在该截面图中，突点100、115、120和125以及安排围绕在预焊料65边缘以将预焊料框住的四个额外的突点145、150、155和160是可见的。在此示意性实施例，突点105、115、120和125通常具有圆形的横截面。然而，实际上可使用任何形状，诸如矩形，正方形或者其他形状。进而，突点100、115、120和125的空间构型可有很大变化并可根据设计酌情决定。实际上，底部填充突点的数量、空间构型、和覆盖面积（footprint）可在焊接点到焊接点之间变化，并且根据设计考虑，给定的焊接点可根本不存在其中紧邻的底部填充的突点。
在图5中描述了一个可能的替代的构型，图5是图4类似的截面图。在此，提供了带有开口的焊接掩膜90’，其中围绕预焊料65’安置底部填充突点165、170、175和180在该开口中。突点165、170、175和180总共为四且具有通常的正方形的覆盖面积。
通过参照图6、图7、图8、图9和图10以及首先参照图6来理解用以制造焊接掩膜90和底部填充突点100、115、120和125的示例性方法。应当理解，在本文将结合在图3所描绘的底部填充25的部分、电路板20和阻焊膜90描述该示例性制造过程，但是也将对这些结构的其他部分进行说明。也应当理解，本文中描述的实施在电路板20上的工艺可实施在带状或者其他形式的许多电路板中的分立电路板或者全体上。现在将注意力转到图6。在此阶段，在电路板20上形成导体结构85和可能其他的金属化结构。导体结构85可由多种导体材料组成，诸如铝、铜、银、金、钛、难熔金属、难熔金属化合物、这些材料的合金等等。作为整体式结构的替代，导体结构85可由多个金属层的叠层组成，诸如钛层随后是镍-钒层随后是铜层。在另一个实施例中，钛层可覆有铜层，随后是镍的表面涂层。然而，熟练的技术人员应该理解可以使用多种的传导性材料形成导体结构85。可使用施加金属性材料的各种公知的技术，诸如物理气相沉积，化学气相沉积、电镀等等。应当理解可利用额外的导体结构。
首先，可将焊接掩膜90施加到电路板20以覆盖导体焊盘85。焊接掩膜90通过旋涂或其他技术施加并且利用制造焊接掩膜的多种适合材料制造而成，诸如，材料例如Taiyo Ink Mfg.Co.,Ltd生产的PSR-4000 AUS703和Hitachi Chemical Co.,Ltd生产的SR7000。在这个阶段，可将非接触式光掩膜170定位到焊接掩膜145上。非接触式掩膜190包括透明的基底192和不透明部分195、200、205、210和215，不透明部分的形状和尺寸是根据形成在焊接掩膜90上的开口的预设的形状和尺寸得到的。铬或者类似材料可用于不透明部分195、200、205、210和215以及一些种类的玻璃可用于基底192。选择地，可在焊接掩膜90上形成光刻掩膜并用公知的技术进行光刻图形化。
现在将结合图7，实施曝光工艺以使焊接掩膜90的未掩蔽部分曝光并致使它们在接下来的显影溶液中不溶解。曝光之后，可移除掩膜190，或者当抗蚀剂形成时通过灰化脱胶、溶剂剥离脱胶等等。根据焊接掩膜90的性质使用曝光光线220的适合的波长和强度以及曝光时间。
现在参考图8，在曝光后接着移除在图7中描绘的非接触掩膜190和用公知的显影液对焊接掩膜90显影以在焊接掩膜90中确定开口105、130、135和140以及设计为容纳随后形成的预焊料的更大的开口225（如图3中的65）。随着开口225的形成，导体焊盘85露出并准备接纳焊料结构。
现在将注意力转到图9。在此，预焊料65可施加在导体焊盘85上。通过印刷、电镀、拾取和定位或者其他施加焊料结构的技术可施加预焊料65。显而易见，应当特别小心以避免沉积任何的预焊料65到焊接掩膜90的开口105、130、135和140内。
如图10所示，底部填充25可通过底部填充材料的配制熔滴或珠230沉积在焊接掩膜90上。这个底部填充25的沉积过程可在半导体芯片15（如图2）安装到电路板20上之前或者之后完成。当底部填充25铺开穿过焊接掩膜90，填充开口105、130、135和140以确定上述突点。在图10中注意到，已经确定了其中两个突点120和125。在沉积之后，底部填充25受到热固化。根据树脂中使用的环氧树脂可用多种参数进行固化。在示例性实施例中，固化可在约140-160℃下实施约60-120分钟。
应该理解如果除了使用光敏化合物也可利用其他的技术确定焊接掩膜90中的开口105、130、135和140。在这点上，可通过化学腐蚀、激光消融或所需其他材料移除技术刻开开口105、130、135和140。
熟练的技术人员将会理解到加固的底部填充突点不需要连接到焊接点或其他互连结构位置。在这方面上，现在转到图11，图11为与示意图4相似的俯视图，但是在更低的放大率上。由于较低的放大率，焊接掩膜90的边缘97和电路板20（也如图2中所示）的表面17的部分都是可见的。为简化说明，仅标识了预焊料65和底部填充突点100、115、120和150，如图4所示。在本文的其他地方描述了在焊接掩膜90上可形成共同标识为235的额外的底部填充。底部填充235可位于底部填充材料与电路板20的界面的任何地方。在该图中，底部填充突点235沿着焊接掩膜90的边界240。
本文所公开的任意的示例性实施例可具体化成计算机可读介质中处理的指令，诸如，例如半导体、磁盘、光盘或其他存储介质或者可作为计算机数据信号。指令或软件能够合成和/或模拟本文中公开的电路结构。在示例性的实施例中，诸如Cadence APD、Encore等电子设计自动程序可用于合成公开的电路结构。其结果代码可用于制造公开的电路结构。
尽管本发明易于受到各种修改和可选形式的影响，但已经通过举例的方式在附图中显示了并且已在本文详细描述了特定实施例。然而，应当理解的是，本发明不旨在局限于所公开的特定形式。而是，本发明旨在涵盖所有落在如随附的权利要求书限定的本发明的主旨和范围内的所有修改、等同和替代方案。

Claims (20)

1.一种制造方法，包括：
在电路板（20）的面（17）上施加焊接掩膜（90）；
在所述焊接掩膜（90）中形成至少一个通向所述面（17）的开口（105）；以及，将底部填充（25）定位在所述焊接掩膜（90）上以使该底部填充的一部分（100）突入所述至少一个开口（105）中。
2.如权利要求1所述的方法，固化所述底部填充使所述部分凝固。
3.如权利要求1所述的方法，包括在所述焊接掩膜上形成多个通向所述面的开口并定位所述底部填充以使其中的部分突入所述多个开口中的每个中。
4.如权利要求3所述的方法，包括耦接焊料（50）结构到所述焊接掩膜。
5.如权利要求4所述的方法，其中，所述焊料结构由所述多个开口横向地框住。
6.如权利要求1所述的方法，包括耦接半导体芯片（15）到所述电路板的所述面。
7.如权利要求1所述的方法，包括通过光刻图形化所述焊接掩膜形成所述至少一个开口。
8.如权利要求1所述的方法，其中，利用存储在计算机可读介质中的指令来形成所述至少一个开口。
9.一种耦接半导体芯片（15）到电路板（20）的方法，包括：
在所述电路板（20）的面（17）上施加焊接掩膜（90）；
在所述焊接掩膜（90）中形成多个通向所述面（17）的开口（105，135）；
耦接所述半导体芯片（15）到所述电路板（20）的所述面（17）以留出空隙（47）；
将底部填充（25）定位在所述空隙（47）中以使其中的部分（100，120）突入每个所述开口（105，135）中。
10.如权利要求9所述的方法，固化所述底部填充使所述部分凝固。
11.如权利要求9所述的方法，包括在所述半导体芯片和所述电路板之间耦接多个焊接点（50，55）。
12.如权利要求11所述的方法，其中所述焊接点中的所述至少一个通过所述多个开口中的至少一些横向地框住。
13.如权利要求9所述的方法，包括通过光刻图形化所述焊接掩膜形成所述多个开口。
14.如权利要求9所述的方法，其中，利用存储在计算机可读介质的指令来形成所述多个开口。
15.一种装置，包括：
电路板（20），其包括面（17）；
在所述面（17）上的焊接掩膜（90），其包括至少一个通向所述面（17）的开口（105）；以及
在所述焊接掩膜（90）上的底部填充（25），其包括突入所述至少一个开口（105）的部分（100）。
16.如权利要求15所述的装置，其中，所述焊接掩膜包括多个通向所述面的开口和所述底部填充包括突入每个所述多个开口的部分。
17.如权利要求16所述的装置，包括耦接到所述电路板的所述面上的焊料结构（50）。
18.如权利要求17所述的装置，其中，所述焊料结构通过所述多个开口中的至少一些横向地框住。
19.如权利要求16所述的装置，其中，所述电路板包括半导体芯片封装基底。
20.如权利要求15所述的装置，包括耦接到所述电路板的所述面的半导体芯片（15）。
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