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CN102687255A - 凹陷半导体衬底 - Google Patents

凹陷半导体衬底 Download PDF

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Publication number
CN102687255A
CN102687255A CN2011800053817A CN201180005381A CN102687255A CN 102687255 A CN102687255 A CN 102687255A CN 2011800053817 A CN2011800053817 A CN 2011800053817A CN 201180005381 A CN201180005381 A CN 201180005381A CN 102687255 A CN102687255 A CN 102687255A
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CN
China
Prior art keywords
semiconductor substrate
via hole
nude film
coupled
sunk area
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN2011800053817A
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English (en)
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CN102687255B (zh
Inventor
吴亚伯
陈若文
韩忠群
刘宪明
卫健群
常润滋
吴嘉洛
郑全成
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kaiwei International Co
Marvell International Ltd
Marvell Asia Pte Ltd
Original Assignee
Mawier International Trade Co Ltd
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Publication of CN102687255A publication Critical patent/CN102687255A/zh
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Abstract

本公开内容的实施例提供一种装置，该装置包括：半导体衬底，具有第一表面，与第一表面相对设置的第二表面，其中第一表面的至少部分被凹陷以形成半导体衬底的凹陷区域，以及一个或者多个过孔，形成于半导体衬底的凹陷区域中以在半导体衬底的第一表面与第二表面之间提供电或者热通路；以及裸片，耦合到半导体衬底，该裸片电耦合到在半导体衬底的凹陷区域中形成的一个或者多个过孔。可以描述和/或要求保护其它实施例。

Description

凹陷半导体衬底
相关申请的交叉引用
本公开内容要求对2011年1月24日提交的第13/012,644号美国专利申请的优先权，该专利申请要求要求2010年2月3日提交的第61/301,125号美国临时专利申请、并且2010年3月22日提交的第61/316,282号美国临时专利申请、并且2010年4月5日提交的第61/321,068号美国临时专利申请、并且2010年4月16日提交的第61/325,189号美国临时专利申请的优先权，这些临时专利申请的全部说明书除了与本说明书不一致的那些章节(如果有)之外出于所有目的通过整体引用而结合于此。
技术领域
本公开内容的实施例涉及集成电路领域，并且更具体地涉及用于封装组件的凹陷半导体衬底的技术、结构和配置。
背景技术
这里提供的背景描述是出于大体上呈现本公开内容的上下文这样的目的。当前提名的发明人的工作在它在这一背景章节中被描述的程度上以及该描述的可能在提交时另外不合适作为现有技术而限定的方面既未明确也未暗示地承认为相对于本公开内容的现有技术。
集成电路器件(比如晶体管)形成于在尺寸上不断缩减成更小尺度的裸片或者芯片上。裸片的尺度的收缩正在对目前用来对去往或者来自半导体裸片的电信号路由的常规衬底制作和/或封装组装技术提出挑战。例如层叠衬底技术可能未在衬底上产生充分小的特征以与形成于裸片上的互连或者其它信号路由特征的更精细间距对应。
发明内容
在一个实施例中，本公开内容提供一种装置，该装置包括：半导体衬底，其具有第一表面，与第一表面相对设置的第二表面，其中第一表面的至少部分被凹陷以形成半导体衬底的凹陷区域，以及一个或者多个过孔，形成于半导体衬底的凹陷区域中以在半导体衬底的第一表面与第二表面之间提供电或者热通路；以及裸片，耦合到半导体衬底，该裸片电耦合到在半导体衬底的凹陷区域中形成的一个或者多个过孔。
在另一实施例中，本公开内容提供一种方法，该方法包括：提供半导体衬底，半导体衬底具有(i)第一表面和(ii)与第一表面相对设置的第二表面；凹陷第一表面的至少部分以形成半导体衬底的凹陷区域；在半导体衬底的凹陷区域中形成一个或者多个过孔以在半导体衬底的第一表面与第二表面之间提供电或者热通路；以及将裸片耦合到半导体衬底，该裸片电耦合到在半导体衬底的凹陷区域中形成的一个或者多个过孔。
附图说明
结合附图通过下文具体描述将容易理解本公开内容的实施例。为了便于这一描述，相似参考标记表示相似结构要素。在附图的各图中通过示例而不是通过限制来图示这里的实施例。
图1至图19示意地图示了用于包括具有凹陷区域的半导体衬底的各种示例封装组件的配置。
图20是用于制作包括具有凹陷区域的半导体衬底的封装组件的方法的工艺流程图。
图21是用于制作包括具有凹陷区域的半导体衬底的封装组件的另一方法的工艺流程图。
图22是用于制作包括具有凹陷区域的半导体衬底的封装组件的又一方法的工艺流程图。
具体实施方式
本公开内容的实施例描述用于具有凹陷区域的半导体衬底的技术、结构和配置以及相关联的封装组件。
该描述可以使用基于视角的描述(比如上/下、之上/之下和顶部/底部)。这样的描述仅用来便于讨论而并非旨在于使这里描述的实施例的应用限于任何特定定向。
出于本公开内容的目的，短语“A/B”意味着A或者B。出于本公开内容的目的，短语“A和/或B”意味着“(A)、(B)或者(A和B)”。出于本公开内容的目的，短语“A、B和C中的至少一个”意味着“(A)、(B)、(C)、(A和B)、(A和C)、(B和C)或者(A、B和C)”。出于本公开内容的目的，短语“(A)B”意味着“(B)或者(AB)”，也就是说，A为可选要素。
以在理解要求保护的主题内容时最有帮助的方式，将各种操作依次描述为多个分立操作。然而描述顺序不应解释为意味着这些操作必然依赖于顺序。具体而言，可以不按呈现顺序执行这些操作。在附加实施例中，可以执行附加的操作和/或可以省略描述的操作。
该描述使用短语“在一个实施例中”、“在实施例中”或者类似言语，每个短语可以指代相同或者不同实施例中的一个或者多个实施例。另外，如关于本公开内容的实施例而使用的术语“包括”、“包含”、“具有”等是同义的。
图1至图19示意地图示了各种示例封装组件，这些封装组件包括具有凹陷区域(例如半导体衬底102的设置于区域104(下文称为凹陷区域104)内的部分)的半导体衬底102。图1描绘了根据各种实施例的用于封装组件100的配置。封装组件100包括半导体衬底102，该半导体衬底是基本上包括半导体材料(如例如硅(Si))的衬底或者中介片。也就是说，半导体衬底102的材料的大部分为半导体材料。半导体材料可以包括晶态和/或非晶态类型的材料。例如在硅的情况下，硅可以包括单晶和/或多晶硅类型。在其它实施例中，半导体衬底102可以包括也可以从这里描述的原理受益的其它半导体材料(如例如锗、III-V族材料或者II-VI材料)。
半导体衬底102包括第一表面A1和与第一表面A相对设置的第二表面A2。第一表面A1和第二表面A2一般指代半导体衬底102的相对表面以便于描述这里描述的各种配置。
根据各种实施例，第一表面A1的部分相对于第一表面A1的其它部分被凹陷以形成半导体衬底102的凹陷区域104。凹陷区域104一般提供半导体衬底102的相对更薄区域以便于形成形成经过半导体衬底102的一个或者多个过孔108。在一些实施例中，半导体衬底102凹陷使得凹陷区域104具有在约10微米与约500微米之间的厚度T1。
图1的半导体衬底102包括半导体衬底102的在凹陷区域104外部并且比凹陷区域104更厚的区域106(下文称为更厚区域106)。在更厚区域106内的半导体衬底102的厚度T2大于凹陷区域104的厚度T1。
使用与一般已知用于在裸片或者芯片上制作集成电路(IC)结构的技术相似的技术来制作半导体衬底102。例如用于在裸片上制作IC器件的公知图案化工艺(比如光刻/蚀刻和/或沉积工艺)可以用来形成半导体衬底102的特征。通过使用半导体制作技术，半导体衬底102可以包括比其它类型的衬底(比如层叠(例如有机)衬底)更小的特征。半导体衬底102便于路由用于当前裸片(这些裸片在尺寸上不断收缩)的电信号(比如输入/输出(I/O)和/或功率/接地信号)。例如，在一些实施例中，半导体衬底102允许细微间距的Si到Si互连以及在半导体衬底102与一个或者多个裸片112之间的最后线路路由。
根据各种实施例，一个或者多个过孔108形成于半导体衬底102的凹陷区域104中。一个或者多个过孔108由电和/或热传导的材料(比如金属)填充。电介质材料可以设置于一个或者多个过孔的金属与半导体衬底的半导体材料之间。一个或者多个过孔108一般提供在半导体衬底102的第一表面A1与第二表面A2之间的电或者热通路。在其中半导体衬底102包括硅的一个实施例中，一个或者多个过孔108为一个或者多个贯穿硅过孔(TSV)。
一个或者多个重新分布层110可以形成于半导体衬底102的第一表面A1和/或第二表面A2上，以路由耦合到半导体衬底102的一个或者多个裸片112的电信号。例如一个或者多个重新分布层110可以提供在一个或者多个裸片112与一个或者多个过孔108之间以及在一个或者多个过孔108与一个或者多个封装互连结构114之间的电路由。
可以例如通过在半导体衬底102的表面上形成例如包括二氧化硅(SiO2)、氮化硅(SiN)、氮氧化硅(SiOxNy)或者其它适当电介质材料的电介质层并且在电介质层上沉积和/或图案化电传导材料(如例如金属(例如铜或者铝)或者掺杂半导体材料(例如掺杂多晶硅))来形成一个或者多个重新分布层110。在其它实施例中，其它适当电传导材料可以用来形成一个或者多个重新分布层110。
一个或者多个重新分布层110可以包括用于路由电信号的多种结构(如例如焊盘、焊区或者迹线)。虽然未描绘，但是包括电绝缘材料(如比如聚酰亚胺)的钝化层可以沉积于一个或者多个重新分布层110上并且被图案化成在钝化层中提供开口以允许一个或者多个裸片112电耦合到一个或者多个重新分布层110。
一个或者多个裸片112如描绘的那样使用例如包括倒装芯片配置的任何适当配置耦合到半导体衬底102。在其它实施例中可以使用其它适当裸片附接配置(如比如接线键合配置)。在图1的描绘实施例中，一个或者多个裸片112耦合到半导体衬底102的凹陷区域104的第一表面A1。
一个或者多个裸片112一般包括半导体材料(如例如硅)。在一个实施例中，使用相同半导体材料来制作一个或者多个裸片112和半导体衬底102以减少与材料的加热/冷却失配(如比如失配的热膨胀系数(CTE))相关联的应力。
一个或者多个裸片112一般具有有源侧(该侧包括多个集成电路(IC)器件(未示出)(比如用于逻辑和存储器的晶体管)形成于其上的表面)和与有源侧相对设置的无源侧。一个或者多个裸片112的有源侧电耦合到一个或者多个重新分布层110。在一些实施例中，一个或者多个裸片112的有源侧如可见的那样使用一个或者多个凸块111耦合到一个或者多个重新分布层110。在其它实施例中，一个或者多个裸片112的有源侧使用其它结构(如例如一个或者多个键合接线)电耦合到一个或者多个重新分布层110。
在图1的描绘实施例中，一个或者多个凸块111形成于一个或者多个裸片112上并且键合到一个或者多个重新分布层110。一个或者多个凸块111一般包括用于路由一个或者多个裸片112的电信号的电传导材料(如比如焊料或者其它金属)。根据各种实施例，一个或者多个凸块111包括铅、金、锡、铜或者无铅材料或者其组合。一个或者多个凸块111可以具有包括球形、圆柱形、矩形或者其它形状的多种形状并且可以使用凸块(bumping)工艺(如比如受控塌陷芯片连接(C4)工艺、柱形凸块或者其它适当工艺)来形成。
一个或者多个凸块111可以形成于一个或者多个裸片112上，而一个或者多个裸片112是晶片或者单一化形式的任一种。一个或者多个裸片112可以附接到半导体衬底102，而半导体衬底102是晶片或者单一化形式的任一种。
虽然未示出，但是一个或者多个其它有源或者无源部件可以装配于半导体衬底102上。部件可以包括电子部件和集成电路(IC)。部件可以例如包括滤波器部件、电阻器、电感器、功率放大器、电容器或者封装IC。在其它实施例中其它有源或者无源部件可以耦合到半导体衬底102。
一个或者多个封装互连结构114(如比如一个或者多个焊球、金属杆或者凸块)可以形成于一个或者多个重新分布层110上，以进一步路由一个或者多个裸片112的电信号。在图1的描绘实施例中，一个或者多个封装互连结构114耦合到在半导体衬底102的第二表面A2上形成的一个或者多个重新分布层110。一个或者多个封装互连结构114一般包括电传导材料。一个或者多个封装互连结构114可以被形成为包括球形、平面型或者多边形形状的多种形状并且可以被定位于多种位置(包括定位于一行中或者多行的阵列中)。虽然一个或者多个封装互连结构114被描绘为在半导体衬底102的外围部分上，但是在其它实施例中一个或者多个封装互连结构114可以设置于半导体衬底102的中心部分上或者附近。
图2描绘了根据各种实施例的用于封装组件200的另一配置。封装组件200具有耦合到半导体衬底102的相对表面的一个或者多个裸片112。一个或者多个裸片112耦合到在半导体衬底102的第一表面A1和半导体衬底的第二表面A2二者上的一个或者多个重新分布层110。封装组件200允许一个或者多个裸片112到半导体衬底102的双面式耦合。在图2的描绘实施例中，在第一表面A1上的一个或者多个裸片112耦合到半导体衬底102的相同凹陷区域104。
封装组件200可以使用设置于半导体衬底102的第二表面A2上的一个或者多个封装互连结构114电耦合到另一电子设备250(比如印刷电路板(PCB)(例如母板)、模块或者另一封装组件)以进一步将一个或者多个半导体裸片112的电信号路由到其它电子设备250。
图3描绘了根据各种实施例的用于封装组件300的另一配置。封装组件300具有形成于半导体衬底102的第一表面A1上以将半导体衬底102电耦合到另一电子设备250的一个或者多个封装互连结构114。也就是说，一个或者多个封装互连结构114可以耦合到凹陷以形成凹陷区域104的相同表面(例如图3中的第一表面A1)。
图4描绘根据各种实施例的用于封装组件400的另一配置。封装组件400具有设置于半导体衬底102的第一表面A1和第二表面A2二者上的一个或者多个封装互连结构114。封装组件400允许另一电子设备250使用设置于第一表面A1上的一个或者多个封装互连结构114耦合到第一表面A1，并且允许另一电子设备250使用设置于第二表面A2上的一个或者多个封装互连结构114耦合到第二表面A2。例如在一个实施例中，耦合到第一表面A1的另一电子设备250为印刷电路板，而耦合到第二表面A2的另一电子设备250为另一封装组件。封装组件400可以被配置成多种多堆叠式封装上的封装(POP)或者其它三维(3D)封装配置。
图5描绘了根据各种实施例的用于封装组件500的另一配置。封装组件500具有形成于半导体衬底102的第一表面A1中的凹陷区域104(该区域为第一凹陷区域)和至少另一凹陷区域504(该区域为第二凹陷区域)。可以通过凹陷第一表面A1的第一部分来形成凹陷区域104，并且可以通过凹陷第一表面A1的第二部分来形成另一凹陷区域504。凹陷区域104和另一凹陷区域504由半导体衬底102的更厚区域106隔开。更厚区域106提供用于封装组件500的更强机械支撑(包括在制作、封装和/或组装操作期间)。
在描绘的实施例中，一个或者多个过孔108形成于凹陷区域104和另一凹陷区域504二者中，并且一个或者多个裸片112中的至少一个裸片设置于凹陷区域104和另一凹陷区域504中的每个凹陷区域中。在其它实施例中可以使用附加凹陷区域。
图6描绘了根据各种实施例的用于封装组件600的另一配置。封装组件600的半导体衬底102具有用于形成凹陷区域104的凹陷第一表面A1。一个或者多个裸片112设置于半导体衬底102的第二表面A2上。在描绘的实施例中，一个或者多个裸片112耦合到半导体衬底102的凹陷区域104的相对于第一表面A1而言基本上为平面型的第二表面A2。一个或者多个封装互连结构114可以布置成包括球栅阵列(BGA)配置的多种配置。
图7描绘了根据各种实施例的用于封装组件700的另一配置。封装组件700具有形成于半导体衬底102的第一表面A1中的凹陷区域104(该区域为第一凹陷区域)和至少另一凹陷区域504(该区域为第二凹陷区域)。凹陷区域104和另一凹陷区域504由半导体衬底102的更厚区域106隔开。
一个或者多个裸片112耦合到凹陷区域104的第一表面A1，并且一个或者多个封装互连结构114耦合到另一凹陷区域504的第一表面A1。如可见的那样，封装组件700(该封装组件具有耦合到另一凹陷区域504的一个或者多个封装互连结构114)提供比具有耦合到更厚区域(例如更厚区域106)的一个或者多个封装互连结构的封装组件更薄的封装组件700。在描绘的实施例中，一个或者多个封装互连结构114使用在半导体衬底102的第一表面A1上形成的一个或者多个重新分布层110电耦合到一个或者多个裸片112。
图8描绘了根据各种实施例的用于封装组件800的另一配置。封装组件800包括与图7的封装组件700相似的凹陷区域104、另一凹陷区域504和更厚区域106。封装组件800还包括形成于另一凹陷区域504中以将一个或者多个封装互连结构114电耦合到一个或者多个裸片112的一个或者多个过孔108。如可见的那样，设置于另一凹陷区域504中的一个或者多个过孔108至少经过形成于第二表面A2上的一个或者多个重新分布层110和设置于凹陷区域104中的一个或者多个过孔108电耦合到一个或者多个裸片112。
图9描绘了根据各种实施例的用于封装组件900的另一配置。封装组件900包括与结合图7和图8描述的封装组件相似的凹陷区域104、另一凹陷区域504和更厚区域106。在图9中，半导体衬底102的第二表面A2的至少部分被凹陷以暴露凹陷区域104中设置的一个或者多个过孔108，从而使得一个或者多个过孔108延伸超出第二表面A2的凹陷部分从而限定一个或者多个过孔108的延伸部分960。一个或者多个过孔108的延伸部分960可以充当散热器的一个或者多个翅片(fin)以便于从一个或者多个裸片112去除热。
图10描绘了根据各种实施例的用于封装组件1000的另一配置。封装组件1000包括通过凹陷半导体衬底102的第二表面A2的至少部分而形成的一个或者多个过孔108的延伸部分960。例如包括氧化物的电介质衬垫120或者膜设置于一个或者多个过孔108的电和/或热传导材料上。电介质衬垫120可以例如作为保护层以保护一个或者多个过孔108的电和/或热传导材料免受凹陷半导体衬底的第二表面A2以暴露一个或者多个过孔108的工艺(例如蚀刻)的影响。如可见的那样，一个或者多个裸片112可以使用一个或者多个凸块111电耦合到一个或者多个过孔108的延伸部分960。
图11描绘了根据各种实施例的用于封装组件1100的另一配置。如可见的那样，封装组件1100包括凹陷区域104和更厚区域106。一个或者多个选择性凹陷区域113(比如孔或者沟道)形成于更厚区域106的表面上以增加半导体衬底102的表面积并且由此便于从封装组件1100的热源散热。
图12描绘了根据各种实施例的用于封装组件1200的另一配置。如可见的那样，封装组件1200包括凹陷区域104、另一凹陷区域504和设置于凹陷区域104与另一凹陷区域504之间的更厚区域106。一个或者多个过孔108形成于凹陷区域104和另一凹陷区域504中。一个或者多个封装互连结构114的至少一个封装互连结构设置于凹陷区域104和另一凹陷区域504的第一表面A1上。这样的配置可以减少封装组件1200的总高度或者总厚度。如可见的那样，一个或者多个裸片112耦合到更厚区域106的第一表面A1和/或第二表面A2。
图13描绘了根据各种实施例的用于封装组件1300的另一配置。封装组件1300包括完全穿过半导体衬底102的一个或者多个过孔108。也就是说，一个或者多个过孔108形成于凹陷区域104和另一凹陷区域504中，以在半导体衬底102的第一表面A1与第二表面A2之间形成连续电或者热连接。一个或者多个附加过孔1308形成于半导体衬底102的更厚区域106的第二表面A2中。一个或者多个附加过孔1308未完全穿过半导体衬底102。也就是说，在描绘的实施例中一个或者多个附加过孔1308仅设置于半导体衬底102的第二表面A2上而未到达第一表面A1。一个或者多个附加过孔1308通过为在封装组件1300中的热提供热通路来提供便于去除热的指状物结构。
图14描绘了根据各种实施例的用于封装组件1400的另一配置。封装组件1400包括形成于半导体衬底102的更厚区域106的第一表面A1中的一个或者多个附加过孔1308。一个或者多个附加过孔1308未完全穿过半导体衬底102。也就是说，在描绘的实施例中一个或者多个附加过孔1308仅设置于半导体衬底102的第一表面A1上而未到达第二表面A2。一个或者多个附加过孔1308通过为在封装组件1400中的热提供热通路来提供便于去除热的指状物结构。
图15描绘了根据各种实施例的用于封装组件1500的另一配置。如可见的那样，封装组件1500包括形成于半导体衬底102的第二表面A2中的凹陷区域104和另一凹陷区域504。如可见的那样，通过凹陷半导体衬底102的第一表面A1的至少部分来形成附加凹陷区域1504。如可见的那样，一个或者多个过孔108设置于凹陷区域104、另一凹陷区域504和附加凹陷区域1504中。一个或者多个封装互连结构114设置于凹陷区域104和另一凹陷区域504的第二表面A2上。一个或者多个裸片112设置于附加凹陷区域1504的第一表面A1上。这样的配置提供具有减少的高度或者厚度的封装组件1500。
图16描绘了根据各种实施例的用于封装组件1600的另一配置。封装组件1600包括以与图15的封装组件1500的半导体衬底102相似的方式配置的半导体衬底102。如可见的那样，封装组件1600还包括堆叠于半导体衬底102上的另一半导体衬底1602。如可见的那样，另一半导体衬底1602包括形成于另一半导体衬底1602的第二表面A2中的凹陷区域104和另一凹陷区域504。如可见的那样，附加凹陷区域1504形成于另一半导体衬底1602的第一表面A1中。一个或者多个过孔108形成于附加凹陷区域1504中，并且一个或者多个半导体裸片112电耦合到设置于附加凹陷区域1504中的一个或者多个过孔108。
根据各种实施例，半导体衬底102的第二表面A2耦合到另一半导体衬底1602的第二表面A2。如可见的那样，可以例如使用一个或者多个封装互连结构114耦合半导体衬底102和另一半导体衬底1602。在其它实施例中可以在半导体衬底102与另一半导体衬底1602之间形成其它类型的电连接或者结构性连接。
图17描绘了根据各种实施例的用于封装组件1700的另一配置。封装组件1700包括以与图4的封装组件400的半导体衬底102相似的方式配置的半导体衬底102。封装组件1700还包括设置于半导体衬底102的第一表面A1和/或第二表面A2上的模制化合物130。在一些实施例中，模制化合物130被设置成基本上包封一个或者多个半导体裸片112。模制化合物130一般保护一个或者多个半导体裸片112免受潮气、氧化或者与操纵相关联的剥落(clipping)的影响。
在一些实施例中模制化合物130可以与下填充材料(未示出)结合使用。例如下填充材料可以设置于一个或者多个裸片112与半导体衬底102之间以包封一个或者多个凸块111，并且模制化合物130可以被设置成包封一个或者多个裸片112。在一些实施例中，模制化合物130可以被形成为使得暴露一个或者多个裸片112的表面以便于从一个或者多个裸片112散热。模制化合物130可以被选择成具有与半导体衬底102和/或一个或者多个裸片112的热膨胀系数基本上相同或者相似的热膨胀系数。
图18描绘了根据各种实施例的用于封装组件1800的另一配置。封装组件1800包括耦合到半导体衬底102的一个或者多个裸片112。如可见的那样，使用粘合剂142将一个或者多个裸片112中的裸片的无源表面附接到半导体衬底的第二表面A2来将该裸片耦合到半导体衬底。如可见的那样，一个或者多个键合接线140将裸片的有源表面电耦合到一个或者多个重新分布层110。
如可见的那样，模制化合物130被设置成基本上包封一个或者多个裸片112和一个或者多个键合接线140。在各种实施例中可以使用倒装芯片和接线键合配置的其它组合或者仅使用接线键合配置。
图19描绘了根据各种实施例的用于封装组件1900的另一配置。半导体衬底102包括形成于第一表面A1中的凹陷区域104和形成于凹陷区域104中的一个或者多个过孔108。第一表面A1凹陷以暴露一个或者多个过孔108的延伸部分960。如可见的那样，电介质衬垫120设置于一个或者多个过孔108的电和/或热传导材料上。如可见的那样，一个或者多个裸片112耦合到一个或者多个过孔108的延伸部分960。如可见的那样，模制化合物130被设置成基本上包封一个或者多个裸片112并且填充在一个或者多个半导体裸片与半导体衬底102之间的区域。
如这里描述的用于使用半导体衬底的封装组件的配置可以提供以下益处：减少与在半导体衬底中制作一个或者多个过孔相关联的工艺复杂性和/或成本、实现半导体衬底的双面利用、便于多堆叠式封装配置、减少封装组件的尺寸和/或增加散热。本公开内容在它的范围内包括结合图1至图19描述的实施例的任何适当组合。
图20是用于制作封装组件(例如图1的封装组件100)的方法2000的工艺流程图，该封装组件包括具有凹陷区域(例如图1的凹陷区域104)的半导体衬底(例如图1的半导体衬底102)。在2002处，该方法2000包括提供半导体衬底。该半导体衬底具有第一表面(例如图1的第一表面A1)和与第一表面相对设置的第二表面(例如图1的第二表面A2)。该半导体衬底包括半导体材料(如例如硅)。可以例如从单晶或者多晶硅半导体材料的锭切割半导体衬底。在结合方法2000描述的工艺期间半导体衬底可以是以单一化或者晶片形式。
在2004处，方法2000还包括凹陷半导体衬底以形成一个或者多个凹陷区域(例如图1的凹陷区域104)。凹陷半导体衬底的表面的至少部分以从半导体衬底去除半导体材料并且提供更薄的凹陷区域以便于形成经过凹陷区域的一个或者多个过孔。可以使用包括公知蚀刻工艺(如比如硅湿蚀刻工艺)的任何适当工艺来凹陷半导体衬底的表面。
在一些实施例中，凹陷仅第一表面的部分。在其它实施例中，如这里描述的那样，凹陷第一表面和/或第二表面的部分以提供具有多个凹陷区域的封装组件配置。根据各种实施例，凹陷区域具有比半导体衬底的在凹陷区域外部的区域(例如图1的更厚区域106)的厚度更小的厚度。
在2006处，方法2000还包括在半导体衬底中形成一个或者多个过孔(例如图1的一个或者多个过孔108)。一个或者多个过孔一般形成于凹陷区域中，以在半导体衬底的第一表面与第二表面之间提供电和/或热通路。根据各种实施例，一个或者多个过孔包括贯穿硅过孔(TSV)。
一般通过从凹陷区域去除半导体材料以形成经过半导体衬底的一个或者多个沟道来形成一个或者多个过孔。多种适当工艺可以用来形成一个或者多个沟道(包括从凹陷区域去除半导体材料的激光钻孔和/或蚀刻工艺)。凹陷区域可以通过提供允许完全经过半导体衬底钻孔或者蚀刻一个或者多个过孔的半导体材料的厚度而便于形成一个或者多个过孔。虽然可以通过从半导体衬底的第一侧或者第二侧去除材料来形成过孔，但是可以通过从更平面或者平坦的表面(例如图1的第二表面A2)去除材料来便于过孔形成工艺。
在形成一个或者多个沟道之后，电介质膜可以形成于一个或者多个沟道的表面上。可以通过使用沉积技术(如比如物理气相沉积(PVD)、化学气相沉积(CVD)和/或原子层沉积(ALD))以沉积电介质材料(如比如二氧化硅(SiO2)、氮化硅(SiN)或者氮氧化硅(SiOxNy)，其中x和y代表适当化学计量值)来形成电介质膜。在其它实施例中可以使用其它适当沉积技术和/或电介质材料。电介质膜一般为设置于一个或者多个过孔中的电传导材料提供电隔离以防止在电传导材料与半导体衬底的半导体材料(例如硅)之间的电流泄漏。
向一个或者多个沟道中沉积电和/或热传导材料(如例如铜或者另一金属)。在一个实施例中，沉积电和/或热传导材料以基本上填充一个或者多个沟道。在另一实施例中，沉积电和/或热传导材料以在一个或者多个沟道的表面上涂覆电介质膜，并且沉积电绝缘材料(如比如环氧树脂、树脂或者氧化物)以填充一个或者多个沟道的剩余部分。
一个或者多个过孔可以用来路由耦合到半导体衬底的一个或者多个裸片的电信号。在一些实施例中，一个或者多个过孔(例如图13的一个或者多个附加过孔1308)形成于半导体衬底的更厚区域(例如图13的更厚区域106)中以便于散热。这样的过孔一般设置于半导体衬底的第一表面和第二表面中的仅一个表面上。也就是说，形成于更厚区域中的一个或者多个过孔未完全穿过半导体衬底。
在一些实施例中，在形成一个或者多个过孔之后凹陷半导体衬底的表面以提供一个或者多个过孔的延伸超出半导体衬底的凹陷表面的延伸部分(例如图9的延伸部分960)。设置于一个或者多个过孔的一个或者多个沟道的表面上的电介质膜(例如图10的电介质衬垫120)可以保护一个或者多个过孔的电和/或热传导材料免受用来暴露延伸部分的蚀刻工艺的影响。另一蚀刻工艺(比如间隔物蚀刻工艺)可以用来去除电介质膜的部分以便于将一个或者多个裸片耦合到一个或者多个过孔的电和/或热传导材料。
在2008处，方法2000还包括在半导体衬底上形成重新分布层(例如图1的一个或者多个重新分布层110)。一般通过在半导体衬底的表面上沉积电介质膜并且在电介质膜上沉积电传导材料来形成重新分布层。在一些实施例中，与沉积电介质膜以形成一个或者多个过孔同时沉积电介质膜。可以图案化和/或蚀刻沉积的电传导材料以提供路由一个或者多个裸片的电信号的重新分布层的路由结构。多个重新分布层可以堆叠于半导体衬底的第一表面和/或第二表面上，以提供电信号的所需路由。
在2010处，方法2000还包括将一个或者多个裸片耦合到半导体衬底。一个或者多个裸片可以以多种配置(例如倒装芯片或者接线键合配置或者其组合)耦合到半导体衬底。在倒装芯片配置中，裸片的有源表面使用一个或者多个凸块(例如图1的一个或者多个凸块111)耦合到重新分布层。在接线键合配置中，裸片的无源表面使用粘合剂(例如图18的粘合剂142)耦合到半导体衬底，并且裸片的有源表面使用一个或者多个键合接线140耦合到重新分布层。一个或者多个裸片电耦合到在半导体衬底的凹陷区域中形成的一个或者多个过孔。
一个或者多个裸片可以耦合到半导体衬底的第一表面和/或第二表面。另外，一个或者多个裸片可以根据各种实施例耦合到半导体衬底的凹陷区域或者更厚区域。
在2012处，方法2000还包括将一个或者多个封装互连结构(例如图1的一个或者多个封装互连结构114)耦合到半导体衬底。可以通过多种适当工艺(例如包括通过网印、电镀、布局或者其它公知方法)形成一个或者多个封装互连结构。一个或者多个封装互连结构电耦合到在半导体衬底的第一表面和第二表面之一或者二者上的重新分布层以向封装组件或者从封装组件向另一电子设备(例如图2的另一电子设备250)路由一个或者多个裸片的电信号。
在2014处，方法2000还包括在半导体衬底上形成模制化合物(例如图17的模制化合物130)。模制化合物可以形成于半导体衬底的第一表面和第二表面之一或者二者上。模制化合物一般被设置成包封一个或者多个裸片。根据各种实施例，可以通过向模具中以固体形式(例如粉末)沉积树脂(例如热固树脂)并且施加热和/或压力以熔融树脂来形成模制化合物。在其它实施例中可以使用用于形成模制化合物的其它公知技术。
在一些实施例中，在一个或者多个封装互连结构耦合到半导体衬底之后形成模制化合物。在这样的情况下，模制化合物可以被形成为提供到一个或者多个封装互连结构的电接通。例如可以沉积模制化合物使得模制化合物未完全包封一个或者多个封装互连结构。在另一示例中，可以例如通过蚀刻或者激光工艺在模制化合物中形成开口以暴露用于电接通的一个或者多个封装互连结构，其中一个或者多个封装互连结构作为蚀刻/激光停止材料来工作。在另一示例中，可以抛光或者以别的方式凹陷模制化合物以暴露一个或者多个封装互连结构。
在其它实施例中，在一个或者多个封装互连结构耦合到半导体衬底之前形成模制化合物。在这样的情况下，可以选择性地形成模制化合物使得模制化合物未覆盖重新分布层的如下区域，在该区域中一个或者多个封装互连结构将被耦合。在另一示例中，可以例如使用激光或者蚀刻工艺在模制化合物中形成一个或者多个开口以暴露重新分布层，并且可以在开口中形成一个或者多个封装互连结构。
在2016处，方法2000还包括将半导体衬底耦合到另一电子设备(例如图2的另一电子设备250)。半导体衬底使用一个或者多个封装互连结构电耦合到另一电子设备(如例如印刷电路板或者另一半导体衬底或者中介片)。半导体衬底可以使用多种配置(例如包括球栅阵列(BGA)配置)耦合到另一电子设备。在一个实施例中，半导体衬底的一个表面耦合到印刷电路板，并且半导体衬底的相对表面耦合到另一半导体衬底。
图21是用于制作封装组件的另一方法2100的工艺流程图，该封装组件包括具有凹陷区域的半导体衬底。方法2100一般描述如下技术，其中在将一个或者多个裸片耦合到半导体衬底之前形成一个或者多个过孔。方法2100可以与结合方法2000描述的相似实施例相似。
在2102处，方法2100包括提供半导体衬底。该衬底包括第一表面和与第一表面相对设置的第二表面。
在2104处，方法2100还包括在半导体衬底中形成一个或者多个过孔。一个或者多个过孔可以形成于半导体衬底的表面中，从而使得一个或者多个过孔起初穿过半导体衬底的仅部分而未到达半导体衬底的相对表面。可以使用如结合方法2000描述的相似技术来形成一个或者多个过孔。
在2106处，方法2100还包括在半导体衬底上形成重新分布层。可以使用如结合方法2000描述的相似技术来形成重新分布层。
在2108处，方法2100还包括将一个或者多个裸片耦合到半导体衬底。一个或者多个裸片电耦合到重新分布层。一个或者多个裸片可以使用如结合方法2000描述的相似技术耦合到衬底。
在2110处，方法2100还包括在半导体衬底上形成模制化合物。可以使用如结合方法2000描述的相似技术来形成模制化合物。
在2112处，方法2100还包括凹陷半导体衬底的表面以暴露一个或者多个过孔。被凹陷的表面是与其中形成有一个或者多个过孔的表面相对的表面。也就是说，如果一个或者多个过孔形成于半导体衬底的第一表面中，则第二表面被凹陷，并且反之亦然。可以通过碾磨工艺或者蚀刻工艺凹陷半导体衬底以提供厚度在约10微米与约500微米之间的凹陷区域。在其它实施例中可以使用其它凹陷技术和厚度。根据各种实施例，使用模制化合物作为机械载体以在凹陷以暴露一个或者多个过孔期间支撑半导体衬底。
方法2100还可以包括在2114处在凹陷表面上形成重新分布层、在2116处将一个或者多个裸片耦合到凹陷表面，在2118处在凹陷表面上形成模制化合物以及在2120处将一个或者多个封装互连结构耦合到重新分布层。这样的动作可以与已经结合方法2000描述的相似动作一致。
图22是用于制作封装组件的又一方法2200的工艺流程图，该封装组件包括具有凹陷区域的半导体衬底。方法2200一般描述如下技术，其中在将一个或者多个裸片耦合到半导体衬底之后形成一个或者多个过孔。方法2200可以与结合方法2000描述的相似实施例一致。
在2202处，方法2200包括提供半导体衬底。该衬底包括第一表面和与第一表面相对设置的第二表面。
在2204处，方法2200还包括在半导体衬底上形成重新分布层。可以使用如结合方法2000描述的相似技术来形成重新分布层。
在2206处，方法2200还包括将一个或者多个裸片耦合到半导体衬底。一个或者多个裸片可以使用如结合方法2000描述的相似技术耦合到衬底。
在2208处，方法2200还包括在半导体衬底上形成模制化合物。可以使用如结合方法2000描述的相似技术来形成模制化合物。
在2210处，方法2200还包括凹陷半导体衬底的表面。凹陷与其上耦合有一个或者多个裸片的表面相对设置的表面。也就是说，如果一个或者多个裸片耦合到半导体衬底的第一表面，则第二表面被凹陷。可以通过碾磨工艺或者蚀刻工艺凹陷半导体衬底以提供厚度在约10微米与约500微米之间的凹陷区域。这样的厚度可以便于形成完全穿过半导体衬底的一个或者多个过孔。在其它实施例中可以使用其他凹陷技术和厚度。根据各种实施例，使用模制化合物作为机械载体以在凹陷期间支撑半导体衬底。
在2212处，方法2200还包括形成经过半导体衬底的一个或者多个过孔。可以使用如结合方法2000描述的相似技术来形成一个或者多个过孔。
方法2200还可以包括在2214处在凹陷表面上形成重新分布层、在2216处将一个或者多个裸片耦合到凹陷表面、在2218处在凹陷表面上形成模制化合物以及在2220处将一个或者多个封装互连结构耦合到重新分布层。这样的动作可以与已经结合方法2000描述的相似动作一致。
虽然这里已经图示和描述某些实施例，但是为了实现相同目的而设计的广泛多种替选和/或等效实施例或者实施方式可以替换图示和描述的实施例而不脱离本公开内容的范围。本公开内容旨在于覆盖这里讨论的实施例的任何适配或者变化。因此，明确旨在于这里描述的实施例仅由权利要求及其等价方式限定。

Claims (50)

1.一种装置，包括：
半导体衬底，具有：
第一表面，
第二表面，与所述第一表面相对设置，其中所述第一表面的至少部分被凹陷以形成所述半导体衬底的凹陷区域，以及
一个或者多个过孔，形成于所述半导体衬底的所述凹陷区域中以在所述半导体衬底的所述第一表面与所述第二表面之间提供电或者热通路；以及
裸片，耦合到所述半导体衬底，所述裸片电耦合到所述在半导体衬底的所述凹陷区域中形成的所述一个或者多个过孔。
2.根据权利要求1所述的装置，其中所述半导体衬底的凹陷区域具有比所述半导体衬底的在所述凹陷区域外部的区域的第二厚度更小的第一厚度。
3.根据权利要求1所述的装置，其中：
所述裸片耦合到所述半导体衬底的所述第一表面；
所述裸片耦合到所述凹陷区域；并且
所述裸片在倒装芯片配置中耦合到所述半导体衬底。
4.根据权利要求3所述的装置，还包括：
重新分布层，(i)形成于所述半导体衬底的所述第二表面上并且(ii)电耦合到所述一个或者多个过孔以路由所述裸片的电信号。
5.根据权利要求4所述的装置，还包括：
一个或者多个封装互连结构，(i)耦合到所述半导体衬底的所述第二表面并且(ii)电耦合到所述重新分布层以进一步路由所述裸片的所述电信号。
6.根据权利要求5所述的装置，其中所述一个或者多个封装互连结构包括焊球或者金属杆中的至少一种。
7.根据权利要求5所述的装置，其中：
所述重新分布层为第一重新分布层；
所述一个或者多个封装互连结构为第一组封装互连结构；并且
所述装置还包括：
第二重新分布层，(i)形成于所述半导体衬底的所述第一表面上并且(ii)电耦合到所述一个或者多个过孔以进一步路由所述裸片的所述电信号；以及
第二组封装互连结构，(i)耦合到所述半导体衬底的所述第一表面并且(ii)电耦合到所述第二重新分布层以进一步路由所述裸片的所述电信号。
8.根据权利要求5所述的装置，其中所述裸片为第一裸片，所述装置还包括：
第二裸片，(i)耦合到所述凹陷区域并且(ii)在倒装芯片配置中耦合到所述半导体衬底的所述第一表面，所述第二裸片电耦合到所述一个或者多个过孔。
9.根据权利要求5所述的装置，其中所述裸片为第一裸片，所述装置还包括：
第二裸片，(i)耦合到所述凹陷区域并且(ii)在倒装芯片配置中耦合到所述半导体衬底的所述第二表面，所述第二裸片电耦合到所述一个或者多个过孔。
10.根据权利要求5所述的装置，还包括：
印刷电路板，使用所述一个或者多个封装互连结构耦合到所述半导体衬底。
11.根据权利要求5所述的装置，其中所述半导体衬底为第一半导体衬底，所述装置还包括：
第二半导体衬底，使用所述一个或者多个封装互连结构耦合到所述第一半导体衬底。
12.根据权利要求2所述的装置，其中所述凹陷区域是通过凹陷所述第一表面的第一部分而形成的第一凹陷区域，所述装置还包括：
所述半导体衬底的一个或者多个第二凹陷区域，通过凹陷所述第一表面的一个或者多个第二部分来形成，其中所述半导体衬底的具有所述第二厚度的所述区域设置于所述第一凹陷区域与所述一个或者多个第二凹陷区域之间。
13.根据权利要求12所述的装置，其中所述一个或者多个过孔为一个或者多个第一过孔，所述装置还包括：
一个或者多个第二过孔，形成于所述一个或者多个第二凹陷区域中，以在所述半导体衬底的所述第一表面与所述第二表面之间提供电通路。
14.根据权利要求13所述的装置，还包括：
重新分布层，形成于所述半导体衬底的所述第二表面上，所述重新分布层电耦合到(i)所述一个或者多个第一过孔和(ii)所述一个或者多个第二过孔以路由所述裸片的电信号；以及
一个或者多个封装互连结构，(i)耦合到所述一个或者多个第二凹陷区域和(ii)所述半导体衬底的所述第一表面，所述一个或者多个封装互连结构使用所述一个或者多个第二过孔电耦合到所述裸片。
15.根据权利要求1所述的装置，其中：
所述裸片耦合到所述半导体衬底的所述第二表面；
所述裸片耦合到所述凹陷区域；并且
所述裸片在倒装芯片配置中耦合到所述半导体衬底。
16.根据权利要求1所述的装置，其中：
所述第二表面的部分被凹陷以暴露所述一个或者多个过孔；并且
所述一个或者多个过孔延伸超出所述半导体衬底的所述第二表面的所述凹陷部分，从而限定所述一个或者多个过孔的延伸部分。
17.根据权利要求16所述的装置，还包括：
电介质膜，设置于所述一个或者多个过孔的所述延伸部分的至少部分上，其中所述裸片电耦合到所述一个或者多个过孔的所述延伸部分。
18.根据权利要求2所述的装置，其中所述裸片耦合到所述半导体衬底的具有所述第二厚度的所述区域。
19.根据权利要求18所述的装置，其中所述一个或者多个过孔包括一个或者多个第一过孔，所述装置还包括：
一个或者多个第二过孔，形成于所述半导体裸片的具有所述第二厚度的所述区域中，其中所述一个或者多个第二过孔设置于所述半导体衬底的(i)所述第一表面和(ii)所述第二表面中的仅一个表面上。
20.根据权利要求1所述的装置，其中所述凹陷区域为第一凹陷区域，所述装置还包括：
第二凹陷区域，通过凹陷所述半导体衬底的所述第二表面的至少部分来形成。
21.根据权利要求20所述的装置，其中：
所述一个或者多个过孔为一个或者多个第一过孔；并且
所述第二凹陷区域包括形成于其中以在所述半导体衬底的所述第一表面与所述第二表面之间提供电或者热通路的一个或者多个第二过孔。
22.根据权利要求20所述的装置，其中所述半导体衬底为第一半导体衬底并且所述裸片为第一裸片，所述装置还包括：
第二半导体衬底，具有：
第三表面，其中所述第三表面的至少部分被凹陷以形成第三凹陷区域，
第四表面，与所述第三表面相对设置，其中所述第四表面的至少部分被凹陷以形成第四凹陷区域，以及
一个或者多个过孔，形成于所述第三凹陷区域中以在所述第二半导体衬底的所述第三表面与所述第四表面之间提供电或者热通路；以及
第二裸片，耦合到所述第二半导体衬底，所述第二裸片电耦合到在所述第二半导体衬底中形成的所述一个或者多个过孔，其中所述第二半导体衬底的所述第四表面耦合到所述第一半导体衬底的所述第二表面。
23.根据权利要求1所述的装置，还包括：
模制化合物，设置于所述半导体衬底的(i)所述第一表面和(ii)所述第二表面中的至少一个表面上，所述模制化合物还被设置成基本上包封所述裸片。
24.根据权利要求1所述的装置，其中：
所述半导体衬底包括硅；
所述裸片包括硅；并且
所述一个或者多个过孔包括贯穿硅过孔(TSV)。
25.根据权利要求1所述的装置，其中所述半导体衬底凹陷从而使得所述凹陷区域具有在10微米与500微米之间的厚度。
26.一种方法，包括：
提供半导体衬底，所述半导体衬底具有(i)第一表面和(ii)与所述第一表面相对设置的第二表面；
凹陷所述第一表面的至少部分以形成所述半导体衬底的凹陷区域；
在所述半导体衬底的所述凹陷区域中形成一个或者多个过孔以在所述半导体衬底的所述第一表面与所述第二表面之间提供电或者热通路；以及
将裸片耦合到所述半导体衬底，所述裸片电耦合到在所述半导体衬底的所述凹陷区域中形成的所述一个或者多个过孔。
27.根据权利要求26所述的方法，其中：
所提供的半导体衬底包括硅；
耦合到所述半导体衬底的所述裸片包括硅；并且
形成于所述凹陷区域中的所述一个或者多个过孔包括贯穿硅过孔(TSV)。
28.根据权利要求26所述的方法，其中使用蚀刻工艺去除所述半导体衬底的半导体材料来凹陷所述第一表面的所述部分。
29.根据权利要求26所述的方法，其中通过以下操作来形成所述一个或者多个过孔：
使用蚀刻工艺或者激光钻孔工艺从所述凹陷区域去除半导体材料以形成经过所述半导体衬底的一个或者多个沟道；
在所述一个或者多个沟道的表面上形成电介质膜；以及
将电和/或热传导材料沉积到所述一个或者多个沟道中。
30.根据权利要求26所述的方法，其中所述半导体衬底的所述凹陷区域具有比所述半导体衬底的在所述凹陷区域外部的区域的第二厚度更小的第一厚度。
31.根据权利要求26所述的方法，其中：
所述裸片耦合到所述半导体衬底的所述第一表面；
所述裸片耦合到所述凹陷区域；并且
所述裸片在倒装芯片配置中耦合到所述半导体衬底。
32.根据权利要求31所述的方法，还包括：
在所述半导体衬底的所述第二表面上形成重新分布层，所述重新分布层电耦合到所述一个或者多个过孔以路由所述裸片的电信号。
33.根据权利要求32所述的方法，还包括：
将一个或者多个封装互连结构耦合到所述半导体衬底的所述第二表面，所述一个或者多个封装互连结构电耦合到所述重新分布层以进一步路由所述裸片的所述电信号。
34.根据权利要求33所述的方法，其中通过在所述重新分布层上形成(i)焊球和(ii)金属杆中的至少一种来将所述一个或者多个封装互连结构耦合到所述第二表面。
35.根据权利要求34所述的方法，其中所述重新分布层为第一重新分布层并且所述一个或者多个封装互连结构为第一组封装互连结构，所述方法还包括：
在所述半导体衬底的所述第一表面上形成第二重新分布层，所述第二重新分布层电耦合到所述一个或者多个过孔以进一步路由所述裸片的所述电信号；以及
将第二组封装互连结构耦合到所述半导体衬底的所述第一表面，所述第二组封装互连结构电耦合到所述第二重新分布层以进一步路由所述裸片的所述电信号。
36.根据权利要求33所述的方法，其中所述裸片为第一裸片，所述方法还包括：
将第二裸片(i)耦合到所述凹陷区域并且(ii)在倒装芯片配置中耦合到所述半导体衬底的所述第一表面，所述第二裸片电耦合到所述一个或者多个过孔。
37.根据权利要求33所述的方法，其中所述裸片为第一裸片，所述方法还包括：
在倒装芯片配置中将第二裸片耦合到所述半导体衬底的所述第二表面，所述第二裸片电耦合到所述一个或者多个过孔。
38.根据权利要求33所述的方法，还包括：
使用所述一个或者多个封装互连结构将印刷电路板耦合到所述半导体衬底。
39.根据权利要求33所述的方法，其中所述半导体衬底为第一半导体衬底，所述方法还包括：
使用所述一个或者多个封装互连结构将第二半导体衬底耦合到所述第一半导体衬底。
40.根据权利要求30所述的方法，其中所述凹陷区域是通过凹陷所述第一表面的第一部分而形成的第一凹陷区域，所述装置还包括：
通过凹陷所述第一表面的一个或者多个第二部分来形成所述半导体衬底的一个或者多个第二凹陷区域，其中所述半导体衬底的具有所述第二厚度的所述区域设置于所述第一凹陷区域与所述一个或者多个第二凹陷区域之间。
41.根据权利要求40所述的方法，其中所述一个或者多个过孔为一个或者多个第一过孔，所述方法还包括：
在所述一个或者多个第二凹陷区域中形成一个或者多个第二过孔以在所述半导体衬底的所述第一表面与所述第二表面之间提供电通路。
42.根据权利要求41所述的方法，还包括：
在所述半导体衬底的所述第二表面上形成重新分布层，所述重新分布层电耦合到(i)所述一个或者多个第一过孔和(ii)所述一个或者多个第二过孔以路由所述裸片的电信号；以及
将一个或者多个封装互连结构耦合到(i)所述半导体衬底的所述第一表面和(ii)所述一个或者多个第二凹陷区域，其中所述一个或者多个封装互连结构使用所述一个或者多个第二过孔电耦合到所述裸片。
43.根据权利要求26所述的方法，其中：
所述裸片耦合到所述半导体衬底的所述第二表面；
所述裸片耦合到所述凹陷区域；并且
所述裸片在倒装芯片配置中耦合到所述半导体衬底。
44.根据权利要求26所述的方法，还包括：
凹陷所述第二表面的部分以暴露所述一个或者多个过孔，从而使得所述一个或者多个过孔延伸超出所述半导体衬底的所述第二表面的所述凹陷部分，所述凹陷所述第二表面的所述部分限定所述一个或者多个过孔的延伸部分。
45.根据权利要求44所述的方法，还包括：
在凹陷所述第二表面的所述部分以暴露所述一个或者多个过孔之前在所述一个或者多个过孔的所述延伸部分的至少部分上形成电介质衬垫，其中所述电介质衬垫在所述凹陷所述第二表面的所述部分期间保护所述一个或者多个过孔，并且其中所述裸片电耦合到所述一个或者多个过孔的所述延伸部分。
46.根据权利要求30所述的方法，其中所述裸片耦合到所述半导体衬底的具有所述第二厚度的所述区域。
47.根据权利要求46所述的方法，其中所述一个或者多个过孔包括一个或者多个第一过孔，所述方法还包括：
在所述半导体裸片的具有所述第二厚度的所述区域中形成一个或者多个第二过孔，其中所述一个或者多个第二过孔设置于所述半导体衬底的(i)所述第一表面和(i)所述第二表面中的仅一个表面上。
48.根据权利要求26所述的方法，其中所述凹陷区域为第一凹陷区域，所述方法还包括：
通过凹陷所述半导体衬底的所述第二表面的至少部分来形成第二凹陷区域。
49.根据权利要求48所述的方法，其中所述一个或者多个过孔为一个或者多个第一过孔，所述方法还包括：
在所述第二凹陷区域中形成一个或者多个第二过孔以在所述半导体衬底的所述第一表面与所述第二表面之间提供电或者热通路。
50.根据权利要求26所述的方法，还包括：
在所述半导体衬底的(i)所述第一表面和(i)所述第二表面中的至少一个表面上形成模制化合物，所述模制化合物被设置成基本上包封所述裸片。
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