Summary of the invention
The embodiment of the invention provides a kind of circuit of display driving, driving method and liquid crystal indicator, is used to prevent the generation of ripples line, improves the display performance of LCD.
A kind of display drive method is applied to liquid crystal indicator, may further comprise the steps:
Sequential control circuit is to first working storage or second working storage, source electrode drive circuit clock signal respectively, and to gate driver circuit output timing control signal;
Said first working storage or said second working storage receive data-signal according to said clock signal from system end, and the data-signal that receives are sent into said sequential control circuit change;
Said gate driver circuit sends chip selection signal according to the timing control signal that receives to said first working storage and said second working storage, and according to the image element circuit array output gate drive voltage of the timing control signal that receives in liquid crystal indicator;
Said first working storage or said second working storage send the data-signal after changing to said source electrode drive circuit after receiving said chip selection signal;
Said source electrode drive circuit is exported the source electrode driving voltage according to clock signal that receives and data-signal to said image element circuit array.
A kind of circuit of display driving is applied to liquid crystal indicator, comprising: sequential control circuit, first working storage, second working storage, source electrode drive circuit and gate driver circuit;
The first input end of said sequential control circuit links to each other with system end; Be used for to said first working storage or said second working storage, said source electrode drive circuit clock signal respectively; Data-signal to said first working storage or the reception of said second working storage is changed, and to said gate driver circuit output timing control signal;
The first input end of said first working storage or said second working storage links to each other with said system end; Be used for receiving data-signal from system end according to said clock signal; The data-signal that receives is sent into said sequential control circuit change, and at the data-signal after said source electrode drive circuit output conversion behind the effective chip selection signal that receives said gate driver circuit transmission;
Said source electrode drive circuit is used for exporting the source electrode driving voltage according to clock signal that receives and data-signal to the image element circuit array of said liquid crystal indicator;
Said gate driver circuit is used for exporting chip selection signal according to the timing control signal that receives to said first working storage and said second working storage, and exports gate drive voltage according to the timing control signal that receives to said image element circuit array.
A kind of liquid crystal indicator comprises described circuit of display driving.
The embodiment of the invention makes scanning hocket through both direction, thereby can effectively offset issuable ripples line through two working storages, improves the display performance of LCD.
Embodiment
Circuit of display driving in the embodiment of the invention comprises: sequential control circuit, first working storage, second working storage, source electrode drive circuit and gate driver circuit; The first input end of said sequential control circuit links to each other with system end; Be used for to said first working storage or said second working storage, said source electrode drive circuit clock signal respectively; Data-signal to said first working storage or the reception of said second working storage is changed, and to said gate driver circuit output timing control signal; The first input end of said first working storage links to each other with said system end; Be used for receiving data-signal from system end according to said clock signal; The data-signal that receives is sent into said sequential control circuit change, and at the data-signal after said source electrode drive circuit output conversion behind the effective chip selection signal that receives said gate driver circuit transmission; The first input end of said second working storage links to each other with said system end; Be used for receiving data-signal from system end according to said clock signal; The data-signal that receives is sent into said sequential control circuit change, and at the data-signal after said source electrode drive circuit output conversion behind the effective chip selection signal that receives said gate driver circuit transmission; Said source electrode drive circuit is used for exporting the source electrode driving voltage according to clock signal that receives and data-signal to the image element circuit array of said liquid crystal indicator; Said gate driver circuit is used for exporting chip selection signal according to the timing control signal that receives to said first working storage and said second working storage, and exports gate drive voltage according to the timing control signal that receives to said image element circuit array.The embodiment of the invention makes scanning hocket through both direction, thereby can effectively offset issuable ripples line through two working storages, improves the display performance of LCD.
Referring to Fig. 1, the circuit of display driving in the embodiment of the invention comprises sequential control circuit 101, first working storage 102, second working storage 103, source electrode drive circuit 104 and gate driver circuit 105.Said circuit of display driving links to each other with image element circuit array 109 in the liquid crystal indicator.The first input end of sequential control circuit 101 links to each other with system end; First output terminal links to each other with the first input end of source electrode drive circuit 104; Second output terminal links to each other with the first input end of gate driver circuit 105; First interaction end links to each other with the interaction end of gate driver circuit 105, and second interaction end links to each other with the interaction end of first working storage 102, and the 3rd interaction end links to each other with the interaction end of second working storage 103; Said first interaction end can think that input end also can be output terminal; Can bi-directional transmission of information, the first input end of first working storage 102 links to each other with system end, and second input end links to each other with first output terminal of gate driver circuit 105; Output terminal links to each other with second input end of source electrode drive circuit 104; The first input end of second working storage 103 links to each other with system end, and second input end links to each other with second output terminal of gate driver circuit 105, and output terminal links to each other with the 3rd input end of source electrode drive circuit 104; The source electrode of every row TFT (TFT) links to each other in the image element circuit array 109 in the output terminal of source electrode drive circuit 104 and the liquid crystal indicator, and the grid of every capable TFT links to each other in the image element circuit array 109 in the output terminal of gate driver circuit 105 and the liquid crystal indicator.Concrete, the embodiment of the invention is that example describes with the positivity liquid crystal.
Sequential control circuit 101 is used for to said first working storage 102 or said second working storage 103, said source electrode drive circuit 104 clock signals respectively; Data-signal to said first working storage 102 or 103 receptions of said second working storage is changed, and to said gate driver circuit 105 output timing control signals.Sequential control circuit 101 is to first working storage 102 or second working storage, 103 tranmitting data register signals; To control the data-signal that first working storage 102 or second working storage, 103 receiving system ends send, reach control first working storage 102 or second working storage 103 and send data-signals to source electrode drive circuit 104.The clock signal that sequential control circuit 101 receiving system ends send; For example; This signal can be LVDS (Low Voltage Differential Signal); Sequential control circuit 101 can convert this clock signal into MINI-LVDS (miniature Low Voltage Differential Signal), and through first output terminal MINI-LVDS is exported to source electrode drive circuit 104, with the clock signal as source electrode drive circuit 104.Sequential control circuit 101 also is used to produce various timing control signals; For example; Said timing control signal comprises CPV (line scanning clock) signal, L/R (shifted left/right) signal, frame start signal etc., and wherein frame start signal can comprise STV1I, STV2I, wherein; STV1I can be called first frame start signal; STV2I can be called second frame start signal, is 101 generations of sequential control circuit, and sequential control circuit 101 sends STV1I signal or STV2I signal through first interaction end to gate driver circuit 105 when confirming the scanning beginning.When the scanning beginning; If the L/R signal is first level signal, then sequential control circuit 101 sends the STV1I signal to gate driver circuit 105, so that gate driver circuit 105 sends effective chip selection signal to first working storage 102; Make 102 work of first working storage; And, second working storage 103 is interrupted, and sequential control circuit 101 is to first working storage, 102 tranmitting data register signals to the invalid chip selection signal of second working storage, 103 transmissions; First working storage 102 receives data-signal according to this clock signal from system end; Again the data-signal that receives is sent into sequential control circuit 101 through interaction end, sequential control circuit is changed the form of the data-signal that receives, and is concrete; The data-signal that first working storage 102 receives can be LVDS; Data-signal after sequential control circuit 101 conversions can be MINI-LVDS, and the data-signal after sequential control circuit 101 will be changed sends to first working storage 102 through second interaction end, by first working storage 102 this data-signal is sent to source electrode drive circuit 104 again; If the L/R signal is second level signal, then sequential control circuit 101 sends the STV2I signal to gate driver circuit 105, so that gate driver circuit 105 sends effective chip selection signal to second working storage 103; Make 102 work of second working storage; And, first working storage 102 is interrupted, and sequential control circuit 101 is to second working storage, 103 tranmitting data register signals to the invalid chip selection signal of first working storage, 102 transmissions; Second working storage 103 receives data-signal according to this clock signal from system end; Again the data-signal that receives is sent into sequential control circuit 101 through interaction end, sequential control circuit 101 is changed the form of the data-signal that receives, and is concrete; The data-signal that second working storage 103 receives can be LVDS; Data-signal after sequential control circuit 101 conversions can be MINI-LVDS, and the data-signal after sequential control circuit 101 will be changed sends to second working storage 103 through the 3rd interaction end, by second working storage 103 this data-signal is sent to source electrode drive circuit 104 again.The CPV signal is used to control the sweep time of every row, i.e. this signal controlling sweep frequency.The L/R signal is used for the gated sweep mode; If the L/R signal is first level signal; Then scan mode is for from left to right, and promptly first row from image element circuit array 109 begins sequential scanning, if the L/R signal is second level signal; Then scan mode is for from right to left, and promptly the last column from image element circuit array 109 begins reverse scanning.Be that low level signal, second level signal are that high level signal is that example describes with first level signal in the embodiment of the invention.
First working storage 102 is used for receiving data-signal according to said clock signal from system end; The data-signal that receives is sent into said sequential control circuit 101 change, and at the data-signal after said source electrode drive circuit 104 output conversions behind the effective chip selection signal that receives said gate driver circuit 105 transmissions.The data-signal that the clock signal receiving system end that first working storage 102 sends according to sequential control circuit 101 sends; Said data-signal returns first working storage 102 after sequential control circuit 101 is changed; First working storage 102 is temporarily stored it; After receiving effective chip selection signal that gate driver circuit 105 sends; Stored data signal is sent to source electrode drive circuit 104, converts this data-signal into source drive voltage for source electrode drive circuit 104, according to the clock signal that receives with this source drive voltage transmission to image element circuit array 109.Chip selection signal described in the embodiment of the invention can be the F/LCS signal.If the F/LCS signal is first level signal; Then first working storage 102 confirms that the chip selection signal that receives is effective chip selection signal; Then stored data signal is sent to source electrode drive circuit 104; If the F/LCS signal is second level signal, then first working storage 102 confirms that the chip selection signal that receives is invalid chip selection signal, does not operate.Be that low level signal, second level signal are that high level signal is that example describes with first level signal in the embodiment of the invention.Concrete, first working storage 102 can be FIFO (FIFO) working storage in the embodiment of the invention.
Second working storage 103 is used for receiving data-signal according to said clock signal from system end; The data-signal that receives is sent into said sequential control circuit 101 change, and at the data-signal after said source electrode drive circuit 104 output conversions behind the effective chip selection signal that receives said gate driver circuit 105 transmissions.The data-signal that the clock signal receiving system end that second working storage 103 sends according to sequential control circuit 101 sends; Said data-signal returns first working storage 102 after sequential control circuit 101 is changed; First working storage 102 is temporarily stored it; After receiving effective chip selection signal that gate driver circuit 105 sends; Stored data signal is sent to source electrode drive circuit 104, converts this data-signal into source drive voltage for source electrode drive circuit 104, according to the clock signal that receives with this source drive voltage transmission to image element circuit array 109.Chip selection signal described in the embodiment of the invention can be the F/LCS signal; If the F/LCS signal is first level signal; Then second working storage 103 confirms that the chip selection signal that receives is invalid chip selection signal, does not operate, if the L/R signal is second level signal; Then second working storage 103 confirms that the chip selection signal that receives is effective chip selection signal, then stored data signal is sent to source electrode drive circuit 104.Be that low level signal, second level signal are that high level signal is that example describes with first level signal in the embodiment of the invention.Concrete, second working storage 103 can be LIFO (afterwards going into earlier) working storage in the embodiment of the invention.
Source electrode drive circuit 104 is used for exporting the source electrode driving voltages according to clock signal that receives and data-signal to the image element circuit array 109 of said liquid crystal indicator.Source electrode drive circuit 104 receives the clock signal that sequential control circuit 101 sends; And the data-signal of first working storage 102 or 103 transmissions of second working storage; Convert said data-signal into source drive voltage, according to clock signal with said source drive voltage transmission to image element circuit array 109.Wherein, Said data-signal can be the MINI-LVDS signal; Source electrode drive circuit 104 can be to transfer to image element circuit array 109 behind TTL (transistor-transistor logic level) signal with this MINI-LVDS conversion of signals, and promptly said source drive voltage is the TTL signal.
Gate driver circuit 105 is used for exporting chip selection signals according to the timing control signal that receives to first working storage 102 and second working storage 103, and exports gate drive voltages according to the timing control signal that receives to image element circuit array 109.Gate driver circuit 105 is confirmed scan mode according to the L/R signal that receives; Reach according to the CPV signal that receives and confirm sweep frequency; When receiving STV1I signal or STV2I signal, begin to image element circuit array 109 output gate drive voltages according to scan mode and sweep frequency.When the end of scan; Gate driver circuit 105 can also generate STV1O signal or STV2O signal; STV1O, STV2O are frame end signal (wherein, STV1O can be called the first frame end signal, and STV2O can be called the second frame end signal); And send to sequential control circuit 101 through interaction end, so that sequential control circuit 101 produces STV2I signal or STV1I signals.For example, when the L/R signal that receives was first level signal, gate driver circuit 105 reached to the invalid chip selection signal of second working storage, 103 outputs to the effective chip selection signal of first working storage, 102 outputs; When the L/R signal that receives was second level signal, gate driver circuit 105 was to the effective chip selection signal of second working storage, 103 outputs, to the invalid chip selection signal of first working storage, 102 outputs.
Referring to Fig. 2; The embodiment of the invention also provides a kind of liquid crystal indicator, and it comprises said circuit of display driving, said image element circuit array 109; Backlight 110 also comprises DCDC (DC-to-dc) change-over circuit 106, gamma circuit (Gamma Circuit) 107 and backlight circuit 108.The input end of DCDC change-over circuit 106 links to each other with system end; First output terminal links to each other with second input end of sequential control circuit 101; Second output terminal links to each other with second input end of gate driver circuit 105; The 3rd output terminal links to each other with the four-input terminal of source electrode drive circuit 104, and the 4th output terminal links to each other with the input end of gamma circuit 107; The output terminal of gamma circuit 107 links to each other with the 5th input end of source electrode drive circuit 104; The input end of backlight circuit 108 links to each other with system end, and output terminal links to each other with backlight 110.
DCDC change-over circuit 106 is used for the voltage signal that receives is changed, and the voltage signal after will changing is exported to sequential control circuit 101, gate driver circuit 105, source electrode drive circuit 104 and gamma circuit 107 respectively.The voltage signal VDD of DCDC change-over circuit 106 receiving system ends output; Be converted into the required varying voltage signal of sequential control circuit 101, gate driver circuit 105, source electrode drive circuit 104 and gamma circuit 107, export to sequential control circuit 101, gate driver circuit 105, source electrode drive circuit 104 and gamma circuit 107 more respectively.For example; DCDC change-over circuit 106 can provide different digital voltage signals for sequential control circuit 101 and gate driver circuit 105; For source electrode drive circuit 104 provides the power supply signal of digital voltage signal as source electrode drive circuit 104; And the reference voltage signal of analog voltage signal as source electrode drive circuit 104 is provided, for gamma circuit 107 provides analog voltage signal.
Gamma circuit 107 is used to source electrode drive circuit 104 the GTG reference signal is provided.Gamma circuit 107 receives the analog voltage signal of DCDC change-over circuits 106 outputs, exports to source electrode drive circuit 104 after being converted into the required GTG reference signal of source electrode drive circuit 104.Wherein, the GTG reference signal is meant the magnitude of voltage of the different gray scales that liquid crystal display is corresponding, through the different angle of different voltages with different value control liquid crystal deflecting element, to realize different transmitances.
Backlight circuit 108 is used to backlight 110 driving voltage is provided.Backlight circuit 108 can provide pwm signal for backlight 110.
Below specifically introduce display drive method.
Referring to Fig. 3, be the main method flow process of display driving in the embodiment of the invention:
Step 301: sequential control circuit 101 reaches to gate driver circuit 105 output timing control signals to source electrode drive circuit 104, first working storage 102 or second working storage, 103 difference clock signals;
Step 302: said first working storage 102 or said second working storage 103 receive data-signal according to said clock signal from system end, and the data-signal that receives are sent into said sequential control circuit 101 change;
Step 303: said gate driver circuit 105 sends chip selection signal according to the timing control signal that receives to said first working storage 102 and said second working storage 103, and according to the image element circuit array 109 output gate drive voltages of the timing control signal that receives in liquid crystal indicator.Wherein, step 302 and step 303 can be by random orders;
Step 304: said first working storage 102 or said second working storage 103 receive the data-signal after said source electrode drive circuit 104 sends conversion behind the said chip selection signal.First working storage 102 or second working storage 103 send the data-signal after sequential control circuit 101 conversions to source electrode drive circuit 104 after receiving said chip selection signal;
Step 305: said source electrode drive circuit 104 is exported the source electrode driving voltages according to clock signal that receives and data-signal to said image element circuit array 109.
As shown in Figure 4, be the sequential chart of display drive method in the embodiment of the invention.This driving process can comprise following two stages:
Phase one:
The clock signal that sequential control circuit 101 receiving system ends send; The clock signal of this LVDS form is converted into the clock signal after source electrode drive circuit 104 output conversions after the clock signal of MINI-LVDS form; And to gate driver circuit 105 output CPV signals, L/R signal; Suppose that the L/R signal is first level signal this moment; Then sequential control circuit 101 to gate driver circuit 105 output be the STV1I signal, sequential control circuit 101 is to first working storage, 102 clock signals, so that first working storage 102 receives data-signal from system end simultaneously; And the data-signal that receives is sent into sequential control circuit 101 change, sequential control circuit 101 converts the data-signal of LVDS form into to be sent into first working storage 102 behind the data-signal of MINI-LVDS form and temporarily stores; After gate driver circuit 105 receives CPV signal, L/R signal, STV1I signal; Send effective chip selection signal to first working storage 102, first working storage 102 is started working, and send invalid chip selection signal to second working storage 103; Second working storage 103 is interrupted, do not operate.And gate driver circuit 104 begins after receiving CPV signal and L/R signal according to sweep frequency and scan mode to image element circuit array 109 output scanning signals; It is gate drive voltage; The scan mode of this moment is for from left to right; Promptly the first row grid from image element circuit array 109 begins scanning, to last column grid end of image element circuit array 109.First working storage 102 is exported to source electrode drive circuit 104 with stored data signal after receiving effective chip selection signal; Source electrode drive circuit 104 is exported the source electrode drive voltage signal according to clock signal that receives and data-signal to image element circuit array 109, and said source drive voltage signal can be the TTL signal.During the end of scan, gate driver circuit 105 can generate the STV1O signal and export to sequential control circuit 101, so that sequential control circuit 101 generates the STV2I signal after receiving this signal, and the driving process of beginning subordinate phase.
Subordinate phase:
The clock signal that sequential control circuit 101 receiving system ends send; The clock signal of this LVDS form is converted into the clock signal after source electrode drive circuit 104 output conversions after the clock signal of MINI-LVDS form; And to gate driver circuit 105 output CPV signals, L/R signal, STV2I signal; This moment, the L/R signal was second level signal; Sequential control circuit 101 is to second working storage, 103 clock signals simultaneously; So that second working storage 103 receives data-signal from system end, and sends the data-signal that receives into sequential control circuit 101 and change, sequential control circuit 101 converts the data-signal of LVDS form into to be sent into second working storage 103 behind the data-signal of MINI-LVDS form and temporarily stores; After gate driver circuit 105 receives CPV signal, L/R signal, STV2I signal; Send effective chip selection signal to second working storage 103, second working storage 103 is started working, and send invalid chip selection signal to first working storage 102; First working storage 102 is interrupted, do not operate.And gate driver circuit 104 begins after receiving CPV signal and L/R signal according to sweep frequency and scan mode to image element circuit array 109 output scanning signals; It is gate drive voltage; The scan mode of this moment is for from right to left; Promptly last column grid from image element circuit array 109 begins scanning, to the first row grid end of image element circuit array 109.Second working storage 103 is exported to source electrode drive circuit 104 with stored data signal after receiving effective chip selection signal; Source electrode drive circuit 104 is exported the source electrode drive voltage signal according to clock signal that receives and data-signal to image element circuit array 109, and said source drive voltage signal can be the TTL signal.During the end of scan, gate driver circuit 105 can generate the STV2O signal and export to sequential control circuit 101, so that sequential control circuit 101 produces the STV1I signal after receiving this signal, and the driving process of beginning phase one.So cycle alternation scans.
Circuit of display driving in the embodiment of the invention comprises: sequential control circuit 101, the first working storages 102, the second working storages 103, source electrode drive circuit 104 and gate driver circuit 105; The first input end of said sequential control circuit 101 links to each other with system end; Be used for to said first working storage 102 or said second working storage 103, said source electrode drive circuit 104 clock signals respectively; Data-signal to said first working storage 102 or 103 receptions of said second working storage is changed, and to said gate driver circuit 105 output timing control signals; The first input end of said first working storage 102 links to each other with said system end; Be used for receiving data-signal from system end according to said clock signal; The data-signal that receives is sent into said sequential control circuit 101 change, and at the data-signal after said source electrode drive circuit 104 output conversions behind the effective chip selection signal that receives said gate driver circuit 105 transmissions; The first input end of said second working storage 103 links to each other with said system end; Be used for receiving data-signal from system end according to said clock signal; The data-signal that receives is sent into said sequential control circuit 101 change, and at the data-signal after said source electrode drive circuit 104 output conversions behind the effective chip selection signal that receives said gate driver circuit 105 transmissions; Said source electrode drive circuit 104 is used for exporting the source electrode driving voltages according to clock signal that receives and data-signal to the image element circuit array 109 of said liquid crystal indicator; Said gate driver circuit 105 is used for exporting chip selection signals according to the timing control signal that receives to said first working storage 102 and said second working storage 103, and exports gate drive voltages according to the timing control signal that receives to said image element circuit array 109.
According to principle of interference; The generation of ripples line is that principle of the present invention is to interfere on the basis of the ripples line that produces in original frequency, adds a refreshing frequency again because the pulse width modulation frequency occurrence frequency interference of refreshing frequency and backlight 110 causes; Frequency to produce is in contrast interfered; Promptly two reverse refreshing frequencys and a pulse width modulation frequency carry out the frequency interference, and two interference effects are cancelled out each other, and reach the effect of eliminating the ripples line.For example: STV1 and modulating frequency are interfered and ripples line upwards occurred; Then opposite with the direction of scanning of STV1 STV2 and modulating frequency are interfered downward ripples line will occur; The rolling frequency of ripples line is identical with the ripples line rolling frequency that makes progress; So can offset, vice versa.Like this then realized eliminating the purpose of ripples lines, effectively improved the display performance of LCD.And be extra one second working storage 103 that increased, circuit of display driving is simple in structure, be easy to realize, and with low cost, help practical application.
Obviously, those skilled in the art can carry out various changes and modification to the present invention and not break away from the spirit and scope of the present invention.Like this, belong within the scope of claim of the present invention and equivalent technologies thereof if of the present invention these are revised with modification, then the present invention also is intended to comprise these changes and modification interior.