CN102565682B - Method for positioning fault testing vectors on basis of bisection method - Google Patents
Method for positioning fault testing vectors on basis of bisection method Download PDFInfo
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Abstract
The invention discloses a method for positioning fault testing vectors on the basis of a bisection method, which comprises the following steps of: loading the testing vectors onto a circuit to be detected and outputting characteristic sequence values corresponding to the testing vectors; obtaining expected characteristic sequence values by responding to a compressor and comparing the expected characteristic sequence values with the actually measured characteristic sequence values; if the expected characteristic sequence values are inconsistent with the actually measured characteristic sequence values, obtaining a result that a certain fault points are possibly detected on the circuit to be detected, and then roughly and equally dividing a testing vector set into a first subset and a second subset; directly finding a first fault testing vector which causes the testing failure by using the first subset as a novel test object; and finishing the testing vectors which are not positioned and repeating the steps by using the testing vectors which are not positioned as a novel testing vector set until all the fault testing vectors are found. According to the positioning method disclosed by the invention, the testing vector set is divided and then the test is respectively carried out, so that the testing times are greatly reduced and the efficiency is high.
Description
Technical field
The present invention relates to the technical field of hardware testing, relate in particular to integrated circuit board electrodes production test field.
Background technology
Along with day by day dwindling of integrated circuit technology size and improving constantly of circuit complexity, particularly SOC (system on a chip) (System-on-Chip, SoC) appearance and widespread use, the integrated level of VLSI (very large scale integrated circuit) has developed on a chip degree that can be more than integrated several ten million transistors.So exploring and apply low cost, high efficiency measuring technology and test macro has become an important topic in chip testing.
Utilizing logic built-in self test (Logic Built-In Self-Test, LBIST) while carrying out chip-scale fault test, the fault coverage of test and localization of fault precision depend on the diagnosis capability of test vector, and the test duration is depended on the length of number of times and the logic built-in self-test scan chain of logic built-in self-test.For specific circuit under test, the length of scan chain is fixed, thereby the test duration is depended on the number of times of test.In actual applications, both required test vector to there is higher trouble diagnosibility, again testing time had been had to higher requirement.
The test vector breaking down is positioned, general by the characteristic vector sequence value of the characteristic vector sequence value of comparison nominative testing vector set and the test vector set of actual test gained, thus judge in set, whether there is fault testing vector.Shown in please refer to the drawing 1, traditional linear orientation method need to be done single test to each test vector of test vector collection the inside, finally confirm all test vector combinations that cause this test failure, the method exists the problem that the test duration is long and testing time is many.
Summary of the invention
The object of the present invention is to provide a kind of localization method of the fault testing vector based on dichotomy, make test more efficient.
For realizing above goal of the invention, the present invention adopts following technical scheme: a kind of localization method of the fault testing vector based on dichotomy, comprises the steps:
S1: circuit under test is connected to test board;
S2: configuration testing vector generator and the response Seed Sequences of compressor reducer and the number of test vector, to generate some test vectors, all test vector composition test vector set, in order to detect circuit under test;
S3: test vector is loaded in circuit under test, until all test vectors have been tested;
S4: the characteristic sequence value of corresponding test vector in output step S3;
S5: obtain desired character sequential value by response compressor reducer, and the actual characteristic sequence value recording in itself and step S4 is made comparisons;
S6: if both results are consistent, illustrate that this circuit under test, by the test of current test vector set, can not detect any trouble spot;
S7: if both results are inconsistent, above-mentioned test vector set is divided into the first subclass and the second subclass;
S8: using the first subclass as new tested object, repeating step S2 to S7, until find first fault testing vector that causes test crash;
S9: arrange the test vector not being positioned, set it as a brand-new test vector set, repeating step S2 to S8, until all fault testing vectors are all found.
As a further improvement on the present invention, in step S3, load test vector by logic bist instruction.
As a further improvement on the present invention, in step S4, the characteristic sequence value of test vector is by again using logic bist instruction to export.
As a further improvement on the present invention, described response compressor reducer is provided with software simulator, and the characteristic sequence value of expecting in step S5 draws by this software simulator.
As a further improvement on the present invention, described test vector generator comprises one group of linear feedback shift register.
As a further improvement on the present invention, in step S8, if the first subclass test crash, test again with regard to further this first subclass being divided into less subclass, so go on, until only contain a test vector in subclass, this test vector is first fault testing vector.
As a further improvement on the present invention, if when a subclass is tested successfully, when another relative subclass also only remains a test vector, just this test vector is regarded as fault testing vector automatically.
Compared to prior art, the localization method of fault testing vector that the present invention is based on dichotomy to test vector set divide, then test respectively, greatly reduce testing time, shortened the test duration, thereby can locate fast and effectively a large amount of test vectors, efficiency is high.
Accompanying drawing explanation
Fig. 1 is logic built-in self-test ultimate principle figure.
The basic framework figure of the general built-in self-test of Fig. 2 institute of the present invention foundation.
Fig. 3 is the basic circuit structure figure of linear feedback shift register.
Embodiment
The present invention is based on the localization method of the fault testing vector of dichotomy, mainly utilize built-in self test to carry out the test of chip-scale logic fault, be connected to test board by circuit under test, generate test vector set by test board, and this test vector set is loaded in circuit under test, judge that by contrastive test result whether circuit under test is by the test of test vector set.Described test board meets the basic framework of general built-in self-test.Shown in please refer to the drawing 2, described test board is provided with test controller 1, and it comprises test vector generator 11 and response compressor reducer 12.Shown in please refer to the drawing 3, described test vector generator 11 comprises one group of linear feedback shift register (Linear Feedback Shift Register, LSFR).By configuration testing vector generator 11 and the response Seed Sequences of compressor reducer 12 and the number of test vector, just can generate some test vectors.All test vector composition test vector set, in order to detect circuit under test.The number of test vector depends on the selection of tandom number generator seed and circuit state quantity and the complexity of circuit under test thereof.But, as long as the basic structure of test vector generator 11 determines, just can calculate the value of the initial seed of any one test vector and the cycle tests of any number of test vectors subsequently thereof.
Test Application is according to logic built-in self-test flow process, by logic bist instruction, test vector is loaded in circuit under test, until all test vectors have been tested.Through the test of certain hour, collect all test results and compress by response compressor reducer 12, obtain one group of characteristic vector sequence for test vector and circuit under test.The software simulator that utilizes test vector generator and response compressor reducer, obtains desired character sequential value.By the sequential value of relatively expecting that characteristic vector sequence value and actual test obtain, just can judge whether to exist some or multiple test vectors some trouble spots to be detected.
The localization method that the present invention is based on the fault testing vector of dichotomy, comprises the steps:
S1: circuit under test is connected to test board by cable, guarantees to connect correctly, in order to avoid affect the correctness of test result;
S2: configuration testing vector generator and the response Seed Sequences of compressor reducer and the number of test vector on test board, to generate some test vectors, all test vector composition test vector set, in order to detect circuit under test;
S3: according to logic built-in self-test flow process, by logic bist instruction, test vector is loaded in circuit under test, until all test vectors have been tested;
S4: the characteristic sequence value (in the present embodiment, the characteristic sequence value of test vector is by again using logic bist instruction to export) of corresponding test vector in output step S3;
S5: obtain desired character sequential value by response compressor reducer 12, and the actual characteristic sequence value recording in itself and step S4 is made comparisons (in the present embodiment, response compressor reducer 12 is provided with software simulator, expects that characteristic sequence value draws by this software simulator in this step);
S6: if both results are consistent, illustrate that this circuit under test, by the test of current test vector set, can not detect any trouble spot;
S7: if both results are inconsistent, illustrate that this circuit under test fails, by the test of current test vector set, some trouble spot may be detected, and subsequently by roughly equal above-mentioned test vector set the first subclass V that is divided into
0with the second subclass V
1;
S8: by the first subclass V
0as new tested object, repeating step S2 to S7, until find first fault testing vector that causes test crash;
S9: arrange the test vector not being positioned, set it as a brand-new test vector set, repeating step S2 to S8, until all fault testing vectors are all found.
The emphasis that the present invention is based on the localization method of the fault testing vector of dichotomy is: in the time that fault testing vector is specifically located, test vector to be positioned is treated as to a set, and this set is divided into two equal-sized subsets, i.e. the first subclass V as much as possible
0with the second subclass V
1.Then, respectively to the first subclass V
0with the second subclass V
1test, if the test of some subclass is passed through, fault testing vector is described not therein, all test vectors in this subclass will be excluded.
Otherwise, if test crash (step S7) is further divided into this subclass two less roughly equal subset V
00, V
01and V
10, V
11, so go on, until only contain a test vector in subset, this test vector is first fault testing vector.In above-mentioned test process, in the time that a subset is tested successfully, if an also only surplus test vector of another relative subset, just this test vector would be regarded as fault testing vector automatically, to reduce once test.
Compared to prior art, the present invention possesses following beneficial effect:
(1). testing time is few; To the combination of test vector arbitrarily, owing to being only simple division to test vector set, testing time is all little, thereby can locate fast and effectively a large amount of test vectors, and efficiency is high.
(2). fault coverage is high; Because localization method location efficiency of the present invention is higher, thereby can improve fault coverage by the scale of effective increase test vector.
(3). test vector is realized simple; Owing to only circuit under test need to being connected to test board by cable, easy to operate.
In sum, these are only preferred embodiment of the present invention, should not limit the scope of the invention with this, i.e. every simple equivalence of doing according to the claims in the present invention book and description of the invention content changes and modifies, and all should still remain within the scope of the patent.
Claims (8)
1. a localization method for the fault testing vector based on dichotomy, is characterized in that, comprises the steps:
S1: circuit under test is connected to test board;
S2: configuration testing vector generator and the response Seed Sequences of compressor reducer and the number of test vector, to generate some test vectors, all test vector composition test vector set, in order to detect circuit under test;
S3: test vector is loaded in circuit under test, until all test vectors have been tested;
S4: the characteristic sequence value of corresponding test vector in output step S3;
S5: obtain desired character sequential value by response compressor reducer, and the actual characteristic sequence value recording in itself and step S4 is made comparisons;
S6: if both results are consistent, illustrate that this circuit under test, by the test of current test vector set, can not detect any trouble spot;
S7: if both results are inconsistent, above-mentioned test vector set is divided into the first subclass and the second subclass;
S8: using the first subclass as new tested object, repeating step S2 to S7, until find first fault testing vector that causes test crash;
S9: arrange the test vector not being positioned, set it as a brand-new test vector set, repeating step S2 to S8, until all fault testing vectors are all found.
2. the localization method of the fault testing vector based on dichotomy as claimed in claim 1, is characterized in that: in step S3, load test vector by logic bist instruction.
3. the localization method of the fault testing vector based on dichotomy as claimed in claim 1, is characterized in that: in step S4, the characteristic sequence value of test vector is by again using logic bist instruction to export.
4. the localization method of the fault testing vector based on dichotomy as claimed in claim 1, is characterized in that: described response compressor reducer is provided with software simulator, and the desired character sequential value in step S5 draws by this software simulator.
5. the localization method of the fault testing vector based on dichotomy as claimed in claim 1, is characterized in that: described test vector generator comprises one group of linear feedback shift register.
6. the localization method of the fault testing vector based on dichotomy as claimed in claim 1, it is characterized in that: in step S8, if the first subclass test crash, test again with regard to further this first subclass being divided into two less subclass, so go on, until only contain a test vector in subclass, this test vector is first fault testing vector.
7. the localization method of the fault testing vector based on dichotomy as claimed in claim 6, it is characterized in that: if a subclass is tested successfully, when another relative subclass also only remains a test vector, this test vector is just regarded as fault testing vector automatically.
8. the localization method of the fault testing vector based on dichotomy as claimed in claim 1, is characterized in that: the size of described the first subclass and the second subclass is roughly equal.
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| CN102841307B (en) * | 2012-09-29 | 2015-07-22 | 南京理工大学常熟研究院有限公司 | Method for positioning logic fault |
| CN105429803B (en) * | 2015-12-14 | 2018-11-23 | 南京国电南自电网自动化有限公司 | Quadratic Imaginary loop fault localization method based on fault zone Difference formula reasoning |
| CN108092850A (en) * | 2017-12-12 | 2018-05-29 | 郑州云海信息技术有限公司 | A kind of cluster server method for diagnosing faults and system based on heartbeat mechanism |
| CN110095711B (en) * | 2019-05-06 | 2021-10-15 | 苏州盛科通信股份有限公司 | Verification method based on test vector out-of-order and discarding behavior |
| CN112666451B (en) * | 2021-03-15 | 2021-06-29 | 南京邮电大学 | Integrated circuit scanning test vector generation method |
| CN115078887B (en) * | 2022-07-20 | 2022-11-25 | 度亘激光技术（苏州）有限公司 | Semiconductor laser aging test method and device |
| CN115952026B (en) * | 2023-03-15 | 2023-06-06 | 燧原智能科技(成都)有限公司 | Abnormal positioning method, device and equipment of virtual chip and storage medium |
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Address after: 215000 unit 13 / 16, 4th floor, building B, No.5 Xinghan street, Suzhou Industrial Park, Jiangsu Province Patentee after: Suzhou Shengke Communication Co.,Ltd. Address before: 215021 unit 13 / 16, floor 4, building B, No. 5, Xinghan street, Suzhou Industrial Park, Suzhou, Jiangsu Patentee before: CENTEC NETWORKS (SU ZHOU) Co.,Ltd. |