CN102544072B - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereof Download PDFInfo
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- CN102544072B CN102544072B CN201110421333.8A CN201110421333A CN102544072B CN 102544072 B CN102544072 B CN 102544072B CN 201110421333 A CN201110421333 A CN 201110421333A CN 102544072 B CN102544072 B CN 102544072B
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Abstract
The present invention provides a semiconductor device which restrains drain current between a source area and a drain area and has a LOCOS separation structure. The semiconductor device is provided with the following components: a first conductive type source area and drain area which are formed through being divided on one part of the upper part of a semiconductor substrate; a grid insulation film which comprises an area that is sandwiched by the source area and the drain area and is configured on the semiconductor substrate; an LOCOS insulation film which is configured continuously with the grid insulation film on the semiconductor substrate and has a thickness that is larger than that of the grid insulation film; and a grid electrode which is formed by a polysilicon film and is continuously configured on the grid insulation film and the LOCOS insulation film next to the grid insulation film, wherein the grid threshold voltage at the end in a trench width direction of the grid electrode, namely the peripheral area, is higher than that in the central area of the grid electrode.
Description
Technical field
The present invention relates to the semiconductor device of the MOS transistor with LOCOS isolating construction and the manufacture method of semiconductor device.
Background technology
In order to realize high withstand voltage MOS transistor, have employed the drain region being adjacent to the high impurity concentration connected with drain electrode, defining the structure in the impurity concentration region lower than this drain region (LDD region).By forming LDD region, the electric field near drain region can be relaxed.In addition, have studied method as described below: use LOCOS method to be formed and (hereinafter be referred to as " LOCOS dielectric film " than the field insulating membrane of gate insulation thickness.), the electric field between mitigation gate electrode and drain region is (for example, referring to patent documentation 1.)。Below, being formed than the structure of the LOCOS dielectric film of gate insulation thickness by having, being called " LOCOS isolating construction ".
[patent documentation 1] Japanese Unexamined Patent Publication 2010-206163 publication
In the MOS transistor of LOCOS isolating construction, there is phenomenon as described below sometimes: between than the low gate/source of gate threshold voltage during design voltage region in, between source region and drain region, flow through leakage current.
Summary of the invention
The object of the invention is to, provide a kind of inhibit the generation of leakage current between source region and drain region, the semiconductor device of LOCOS isolating construction and the manufacture method of semiconductor device.
According to a mode of the present invention, provide a kind of semiconductor device, it comprises: (A) Semiconductor substrate; (B) source region of the 1st conductivity type and drain region, it is separated from each other formation in the part on the top of Semiconductor substrate; (C) gate insulating film, it comprises the region clipped by source region and drain region, and configuration is on a semiconductor substrate; (D) LOCOS dielectric film, it is centered around the surrounding of the channel region formed between source region and drain region and configures continuously with gate insulating film on a semiconductor substrate, Film Thickness Ratio gate insulation thickness; And (E) gate electrode, it is made up of polysilicon film, and in the region clipped by source region and drain region, configure continuously across on the LOCOS dielectric film on gate insulating film and around gate insulating film, gate threshold voltage in the neighboring area of gate electrode is higher than the gate threshold voltage in the middle section of gate electrode, the gate threshold voltage when difference of the gate threshold voltage in the gate threshold voltage in the neighboring area of gate electrode and the middle section of gate electrode is greater than design and the difference of drain voltage, the neighboring area of this gate electrode is the end of the channel width dimension of this gate electrode.
According to another way of the present invention, provide a kind of manufacture method of semiconductor device, the method comprises the steps: (A) by LOCOS method, and the part on the surface of Semiconductor substrate forms LOCOS dielectric film; (B) in the remaining region in region defining LOCOS dielectric film, with LOCOS dielectric film continuous print mode, form the thin gate insulating film of Film Thickness Ratio LOCOS dielectric film on the surface of a semiconductor substrate; (C) form across on the LOCOS dielectric film on gate insulating film and around gate insulating film the gate electrode be made up of polysilicon film continuously; (D) clip the region being formed with gate electrode, form source region and the drain region of the 1st conductivity type on the top of Semiconductor substrate; And (E) makes the gate threshold voltage in the neighboring area of gate electrode higher than the gate threshold voltage in the middle section of gate electrode, gate threshold voltage when making the difference of the gate threshold voltage in the middle section of the gate threshold voltage in the neighboring area of gate electrode and gate electrode be greater than design and the difference of drain voltage, and across certain distance, conductive-type impurity is injected to the gate electrode gate insulating film from the border between gate insulating film and LOCOS dielectric film to the middle section of gate electrode, the neighboring area of this gate electrode is the end of the channel width dimension of this gate electrode.
According to the present invention, can provide the generation of the leakage current that inhibit between source region and drain region, the semiconductor device of LOCOS isolating construction and the manufacture method of semiconductor device.
Accompanying drawing explanation
Fig. 1 is the profile of the signal of the structure of the semiconductor device representing the 1st execution mode of the present invention.
Fig. 2 is the vertical view of the signal of the structure of the semiconductor device representing the 1st execution mode of the present invention.
Fig. 3 is the profile in the III-III direction along Fig. 2.
Fig. 4 is the curve chart representing the semiconductor device of the 1st execution mode of the present invention and the current-voltage characteristic of comparative example.
Fig. 5 is the process profile (one) of the manufacture method of semiconductor device for illustration of the 1st execution mode of the present invention.
Fig. 6 is the process profile (its two) of the manufacture method of semiconductor device for illustration of the 1st execution mode of the present invention.
Fig. 7 is the process profile (its three) of the manufacture method of semiconductor device for illustration of the 1st execution mode of the present invention.
Fig. 8 is the process profile (its four) of the manufacture method of semiconductor device for illustration of the 1st execution mode of the present invention.
Fig. 9 is the process profile (its five) of the manufacture method of semiconductor device for illustration of the 1st execution mode of the present invention.
Figure 10 is the process profile (its six) of the manufacture method of semiconductor device for illustration of the 1st execution mode of the present invention.
Figure 11 is the process profile (its seven) of the manufacture method of semiconductor device for illustration of the 1st execution mode of the present invention.
Figure 12 is the process profile (its eight) of the manufacture method of semiconductor device for illustration of the 1st execution mode of the present invention.
Figure 13 is the profile of the signal of the structure of the semiconductor device representing the 2nd execution mode of the present invention.
Figure 14 is the vertical view of the signal of the structure of the semiconductor device representing the 2nd execution mode of the present invention.
Figure 15 is the profile in the XV-XV direction along Figure 14.
Figure 16 is the vertical view of the signal of the structure of the semiconductor device of the variation representing the 2nd execution mode of the present invention.
Figure 17 is the process profile (one) of the manufacture method of semiconductor device for illustration of the 2nd execution mode of the present invention.
Figure 18 is the process profile (its two) of the manufacture method of semiconductor device for illustration of the 2nd execution mode of the present invention.
Figure 19 is the process profile (its three) of the manufacture method of semiconductor device for illustration of the 2nd execution mode of the present invention.
Symbol description
1 ... semiconductor device; 10 ... Semiconductor substrate; 11 ... silicon substrate; 12 ... epitaxial loayer; 13 ... well area; 20 ... source region; 21 ... low concentration source region; 22 ... high concentration source region; 30 ... drain region; 31 ... low concentration drain region; 32 ... high concentration drain region; 40 ... gate insulating film; 50 ... gate electrode; 51 ... sidewall; 60 ... LOCOS dielectric film.
Embodiment
Then, with reference to accompanying drawing, the of the present invention 1st and the 2nd execution mode is described.In the record of following accompanying drawing, same or similar symbol is enclosed to same or similar part.But accompanying drawing is the figure of signal, it should be noted that the ratio of the thickness of the relation between thickness from planar dimension, each layer etc. is different with reality.Therefore, concrete thickness and size, should judge with reference to the following description.In addition, even if accompanying drawing each other, also comprises the part that mutual size relationship is different with ratio certainly.
In addition, shown below the 1st and the 2nd execution mode, be the example exemplified with the apparatus and method for specializing technological thought of the present invention, in embodiments of the present invention, the material, shape, structure, configuration etc. of structure member be not specific to following record.Within the scope of the claims, various change can be implemented to embodiments of the present invention.
(the 1st execution mode)
Fig. 1 ~ Fig. 3 represents the semiconductor device 1 of the 1st execution mode of the present invention.Fig. 1 is the profile in the I-I direction along Fig. 2, represents along the truncation surface in the channel region in the grid width direction of semiconductor device 1.Fig. 3 is the profile in the III-III direction along Fig. 2, represents the truncation surface of the middle section of the gate electrode 50 of the grid length direction along semiconductor device 1.In the vertical view of Fig. 2, eliminate gate insulating film 40.
As shown in FIG. 1 to 3, semiconductor device 1 has: Semiconductor substrate 10; The part on the top of Semiconductor substrate 10 is separated from each other and the source region 20 of the 1st conductivity type formed and drain region 30; Comprise the region clipped by source region 20 and drain region 30 and the gate insulating film 40 configured over the semiconductor substrate 10; The LOCOS dielectric film 60 that Film Thickness Ratio gate insulating film 40 is thick; And in the region clipped by source region 20 and drain region 30, at the gate electrode 50 be made up of polysilicon film across the 1st conductivity type that the LOCOS dielectric film 60 on gate insulating film 40 and around gate insulating film 40 configures continuously.LOCOS dielectric film 60 is centered around around the channel region that formed between source region 20 and drain region 30, configures continuously over the semiconductor substrate 10 with gate insulating film 40.In addition, the 1st conductivity type and the 2nd conductivity type are mutually opposite conduction types.If namely the 1st conductivity type is N-shaped, then the 2nd conductivity type is p-type, and semiconductor device 1 is N-shaped channel MOS transistor.In addition, if the 1st conductivity type is p-type, then the 2nd conductivity type is N-shaped, and semiconductor device 1 is p-type channel MOS transistor.
Semiconductor device 1 is the MOS transistor that the gate threshold voltage on the end of the channel width dimension of gate electrode 50 and neighboring area S is higher than the gate threshold voltage in the middle section of gate electrode 50.In addition, using the region except neighboring area S as the middle section of gate electrode 50.Herein, gate threshold voltage in order to make needed for semiconductor device 1 conducting, be applied to voltage between gate electrode 50 and source region 20.In Fig. 1 and Fig. 2, with thick line by the neighboring area S of gate electrode 50 around representing (following identical.)。Neighboring area S comprises region as described below: region that be w from the border T between gate insulating film 40 and LOCOS dielectric film 60 to the middle section distance towards gate electrode 50, the gate electrode 50 be configured in gate insulating film 40.In addition, in fig. 2, the end of the LOCOS dielectric film 60 below gate electrode 50 represented by dashed line.
In semiconductor device 1, although can describe in detail below, the middle section being formed as the concentration ratio gate electrode 50 of the impurity of the 1st electric conductor of the neighboring area S of gate electrode 50 is low.
As shown in FIG. 1 to 3, semiconductor device 1 is the LOCOS isolating construction with LOCOS dielectric film 60.Owing to forming LOCOS dielectric film 60 by LOCOS method, therefore the bottom of LOCOS dielectric film 60 is embedded in the part above Semiconductor substrate 10.
In addition, as shown in Figure 1, the both ends in the grid width direction of gate electrode 50 are configured on LOCOS dielectric film 60.In addition, connect with the side of gate electrode 50 and be formed with sidewall 51.
The source region 20 of semiconductor device 1 has LDS (the lightly Doped Source) structure be formed by connecting by the high concentration source region 22 that the concentration ratio low concentration source region 21 of the low concentration source region 21 of the 1st conductivity type formed in the region close to gate electrode 50 and the impurity of the 1st conductivity type is high.Drain region 30 has LDD (the lightly Doped Drain) structure be formed by connecting by the high concentration drain region 32 that the concentration ratio low concentration drain region 31 of the low concentration drain region 31 of the 1st conductivity type formed in the region close to gate electrode 50 and the impurity of the 1st conductivity type is high.
As shown in FIG. 1 to 3, Semiconductor substrate 10 is structures as described below: the epitaxial loayer 12 of the 1st conductivity type is grown up on the silicon substrate 11 of the 2nd conductivity type, epitaxial loayer 12 defines the well area 13 of the 2nd conductivity type.Well area 13 by LOCOS dielectric film 60 around region in be formed with the what is called " active area " of semiconductor device 1.
When forming LOCOS dielectric film 60, the impurity being diffused in the well area 13 below LOCOS dielectric film 60 is absorbed into the end of LOCOS dielectric film 60.Thus, the impurity concentration of the well area 13 near the end of LOCOS dielectric film 60 declines.Its result, on the end of LOCOS dielectric film 60, between the gate/source lower than gate threshold voltage during design, voltage is (hereinafter referred to as " drain voltage V (leak) ".) in, between source region 20 and drain region 30, flow through leakage current." gate threshold voltage during design " be LOCOS dielectric film 60 end near in the impurity concentration of well area 13 when not declining, the gate threshold voltage of regulation determined by the impurity concentration preset.
The generation of above-mentioned leakage current, situation about particularly observing in N-shaped channel MOS transistor is in the majority.Therefore, following, to the 1st conductivity type be N-shaped, the 2nd conductivity type is the situation of p-type, be described by way of illustration.
In semiconductor device 1, near the border T between gate insulating film 40 and LOCOS dielectric film 60, namely the N-shaped impurity concentration of the neighboring area S of gate electrode 50 is lower than the N-shaped impurity concentration of the middle section of gate electrode 50.Therefore, being positioned at the end of the LOCOS dielectric film 60 below the neighboring area S of gate electrode 50, compared with the middle section of gate electrode 50, be difficult to cause channel inversion.That is, on the neighboring area S of gate electrode 50, gate threshold voltage partly rises.
As mentioned above, in semiconductor device 1, gate threshold voltage in the neighboring area S of gate electrode 50 is (hereinafter referred to as " periphery gate threshold voltage V (th) 2 ".) than the gate threshold voltage in the middle section of gate electrode 50 (hereinafter referred to as " central gate threshold voltage V (th) 1 ".) high.In region beyond the neighboring area S of gate electrode 50, gate threshold voltage is central gate threshold voltage V (th) 1.In addition, gate threshold voltage when central gate threshold voltage V (th) 1 is design.
In addition, gate threshold voltage when being preferably greater than design with central gate threshold voltage V (th) 1 and the difference of periphery gate threshold voltage V (th) 2 and the mode of the difference of drain voltage V (leak), set the difference of the N-shaped impurity concentration of neighboring area S of gate electrode 50 and the N-shaped impurity concentration of the middle section of gate electrode 50.
Therefore, in semiconductor device 1, between than the low gate/source of gate threshold voltage during design in voltage, can not leakage current between the generation source region, end 20 of LOCOS dielectric film 60 and drain region 30.
In addition, the conductivity type that also can make the neighboring area S of gate electrode 50 is p-type, makes the conductivity type in the region beyond the S of neighboring area be N-shaped.Even if in the semiconductor device 1 of this structure, the periphery gate threshold voltage V (th) 2 of semiconductor device 1 also can be made higher than central gate threshold voltage V (th) 1.
Characteristic A shown in Fig. 4 be the semiconductor device 1 representing the 1st execution mode gate/source between the current-voltage characteristic of relation between voltage Vgs and drain current Ids, characteristic B ~ characteristic C is the current-voltage characteristic of comparative example.
Namely, characteristic A is the current-voltage characteristic of semiconductor device 1 as described below: the concentration of the N-shaped impurity in the middle section of the concentration ratio gate electrode 50 of the N-shaped impurity of the gate electrode 50 of middle section across certain distance w gate insulating film 40 from the border T between gate insulating film 40 and LOCOS dielectric film 60 to gate electrode 50 is low.
Characteristic B is, about the gate electrode 50 on LOCOS dielectric film 60, in the region to the border T between gate insulating film 40 and LOCOS dielectric film 60, and the current-voltage characteristic of the comparative example B of ion implantation p-type impurity.That is, comparative example B is the semiconductor device that the concentration of N-shaped impurity in the middle section of the concentration ratio gate electrode 50 of N-shaped impurity to the gate electrode 50 on the LOCOS dielectric film 60 of border T is low.
Characteristic C does not have ion implantation p-type impurity on gate electrode 50, and the current-voltage characteristic of the comparative example C the same in whole region of the concentration of the N-shaped impurity of gate electrode 50.
As shown in Figure 4, compared with characteristic B, C, in the characteristic A region that voltage Vgs is low between gate/source, drain current Ids is little.That is, the concentration of the N-shaped impurity in the middle section of the concentration ratio gate electrode 50 of the N-shaped impurity of the gate electrode 50 on the known gate insulating film 40 by making in the S of neighboring area is low, can suppress the generation of leakage current.
As shown in characteristic B, in the neighboring area S of gate electrode 50, implanted with p-type impurity in gate electrode 50 only on LOCOS dielectric film 60, when there is no the comparative example B of implanted with p-type impurity in the gate electrode 50 on gate insulating film 40, although how much improve characteristic compared with comparative example C, leakage current can not be suppressed.Therefore, the known certain distance w from the border T between gate insulating film 40 and LOCOS dielectric film 60 to the middle section of gate electrode 50, if do not reduce the impurity concentration of gate electrode 50, then can not realize the semiconductor device 1 that periphery gate threshold voltage V (th) 2 is higher than central gate threshold voltage V (th) 1.Distance w is such as about 0.5 μm.
As described above, in the semiconductor device 1 of the 1st execution mode of the present invention, the N-shaped impurity concentration in the neighboring area S that is neighbouring, i.e. gate electrode 50 of the end of LOCOS dielectric film 60 is lower than the N-shaped impurity concentration of the middle section of gate electrode 50.Therefore, the periphery gate threshold voltage V (th) 2 in the neighboring area S of gate electrode 50 is higher than the central gate threshold voltage V (th) 1 in the middle section of gate electrode 50.Its result, the semiconductor device 1 according to Fig. 1, even if in the MOS transistor of LOCOS isolating construction, also can suppress the generation of the leakage current between source region 20 and drain region 30.
In addition, in above-mentioned, although to the 1st conductivity type be N-shaped, the 2nd conductivity type is that the situation of p-type is illustrated, when the 1st conductivity type be p-type, the 2nd conductivity type be N-shaped, also can obtain identical effect.Namely, on N-shaped well area 13, p-type source region 20 and drain region 30 is formed, be configured in the semiconductor device 1 on gate insulating film 40 and LOCOS dielectric film 60 about the gate electrode 50 be made up of p-type polysilicon film, make the p-type impurity concentration in the neighboring area S of gate electrode 50 lower than the p-type impurity concentration in the middle section of gate electrode 50.Thereby, it is possible to make the gate threshold voltage in the neighboring area S of gate electrode 50 higher than the gate threshold voltage in the middle section of gate electrode 50.In addition, in the above-described embodiment, in order to obtain the characteristic expected, conductivity type and the impurity concentration of gate electrode can suitably be changed.
Below, with reference to Fig. 5 ~ Figure 12, the example of the manufacture method of the semiconductor device 1 that N-shaped impurity concentration in the neighboring area S of gate electrode 50 is lower than the N-shaped impurity concentration of the middle section of gate electrode 50 is described.The manufacture method of the semiconductor device of the following stated is an example, certainly can comprise this variation, and be realized by various manufacture method other than the above.In addition, in each figure of Fig. 5 ~ Figure 12, figure (a) is the profile in the I-I direction along Fig. 2, and figure (b) is the profile along III-III direction.
(A) as shown in Figure 5, on p-type silicon substrate 11 epitaxial growth N-shaped epitaxial loayer 12 in, form p-type well area 13.Thus, Semiconductor substrate 10 is prepared.Well area 13 is such as after the position of regulation by ion implantation, p-type foreign ion being injected into epitaxial loayer 12, is formed by making the thermal diffusion of p-type impurity.
(B) as shown in Figure 6, the part on the surface of epitaxial loayer 12 and well area 13 forms LOCOS dielectric film 60.Such as, on the surface integral of epitaxial loayer 12 and well area 13, after forming silicon nitride (SiN) film, the removings such as photoetching technique are used to form the silicon nitride film in the region of LOCOS dielectric films 60.Further, to the silicon nitride film of composition as mask, LOCOS dielectric film 60 is optionally formed by LOCOS method.The thickness of LOCOS dielectric film 60 is such as about 300nm ~ 600nm.
(C) after the silicon nitride film in removing Semiconductor substrate 10, by thermal oxidation method etc., the surface of exposed well area 13 is oxidized, forms the gate insulating film 40 that Film Thickness Ratio LOCOS dielectric film 60 is thin.The thickness of gate insulating film 40 is such as about 40nm ~ 60nm.Thus, as shown in Figure 7, in the remaining region in region forming LOCOS dielectric film 60, be formed and LOCOS dielectric film 60 continuous print gate insulating film 40.
(D) by chemical vapour deposition (CVD) (CVD) method etc., whole forms N-shaped polysilicon film.Then, use photoetching technique etc. to carry out composition to N-shaped polysilicon film, as shown in Figure 8, form gate electrode 50.That is, across the LOCOS dielectric film 60 on gate insulating film 40 and around gate insulating film 40 being formed continuously the gate electrode 50 be made up of N-shaped polysilicon film.In addition, also after formation undoped polycrystalline silicon film, gate electrode 50 can be formed by ion implantation N-shaped impurity.
(E) using gate electrode 50 as mask, the N-shaped foreign ion of phosphorus (P) or arsenic (As) etc. is injected in well area 13, as shown in Figure 9, forms low concentration source region 21 and low concentration drain region 31.The surface impurity concentration in low concentration source region 21 and low concentration drain region 31 is such as 1 × 10
17cm
-3left and right.
(F), form silicon nitride film on whole after, by reactive ion etching (RIE) method etc., anisotropic etching is carried out to this silicon nitride film.Its result, as shown in Figure 10, connects with the side of gate electrode 50 and forms sidewall 51.Also silicon oxide film etc. can be used on sidewall 51.
(G) will the photoresist film of photoetching technique composition and gate electrode 50 and sidewall 51 be used as mask, in the region of the regulation of well area 13, the N-shaped impurity of ion implantation phosphorus or arsenic etc., as shown in figure 11, forms high concentration source region 22 and high concentration drain region 32.The surface impurity concentration in high concentration source region 22 and high concentration drain region 32 is such as 2 × 10
19cm
-3left and right.As shown in figure 11, low concentration source region 21 is connected with high concentration source region 22, and low concentration drain region 31 is connected with high concentration drain region 32.
(H) on whole after painting photoresist film 90, as shown in figure 12, above the T region, border between gate insulating film 40 and LOCOS dielectric film 60, the mode exposed with gate electrode 50, carries out composition to photoresist film 90.Now, in the end of the channel width dimension of gate electrode 50, be exposed at least from the border T between gate insulating film 40 and LOCOS dielectric film 60 to the mode of the middle section of gate electrode 50 across distance w with gate electrode 50, composition is carried out to photoresist film 90.Then, using photoresist film 90 as mask, the p-type foreign ion of boron (B) etc. is injected into gate electrode 50.Thus, in the neighboring area S of gate electrode 50, p-type impurity is injected with.The injection rate of p-type impurity is such as 1 × 10
15cm
-2left and right.Its result, the N-shaped impurity concentration of the neighboring area S of gate electrode 50 becomes lower than the N-shaped impurity concentration of the middle section of gate electrode 50.Removing photoresist film 90, and complete the semiconductor device 1 shown in Fig. 1.
In above-mentioned, illustratively describe the situation forming LDS region and LDD region.But semiconductor device 1 also can be the structure without LDS region and LDD region.
In addition, the operation of implanted with p-type impurity in the neighboring area S of gate electrode 50, can carry out as independent operation, also can carry out with the manufacturing process of other semiconductor element simultaneously.Such as, illustrated p-type channel MOS transistor will omitted, when being formed over the semiconductor substrate 10 with semiconductor device simultaneously, also can in the ion injecting process in the source region or drain region that form p-type channel MOS transistor, implanted with p-type impurity in the neighboring area S of gate electrode 50.
In addition, by improving the concentration being injected into the p-type impurity of the neighboring area S of gate electrode 50, the conductivity type of the middle section of gate electrode 50 also can be made to maintain N-shaped, make the conductivity type of the neighboring area S of gate electrode 50 become p-type.
As described above, according to the manufacture method of the semiconductor device 1 of the 1st execution mode of the present invention, the N-shaped impurity concentration of the neighboring area S of gate electrode 50 can be made lower than the N-shaped impurity concentration of the middle section of gate electrode 50.Its result, can set higher than the central gate threshold voltage V (th) 1 in the middle section of gate electrode 50 by the periphery gate threshold voltage V (th) 2 near the borderline region between the gate insulating film 40 of semiconductor device 1 and LOCOS dielectric film 60.Therefore, it is possible to provide the generation of the leakage current that inhibit between source region 20 and drain region 30, the semiconductor device 1 of LOCOS isolating construction.
(the 2nd execution mode)
As shown in figure 13, the semiconductor device 1 of the 2nd execution mode of the present invention is with the difference of the semiconductor device 1 shown in Fig. 1: be not only the periphery at well area 13, on low concentration source region 21 and on low concentration drain region 31, be also formed with LOCOS dielectric film 60.Gate electrode 50 shown in Figure 13, is configuring from gate insulating film 40 continuously across on low concentration source region 21 and on the LOCOS dielectric film 60 of low concentration drain region 31 formation.
Figure 14 illustrates the vertical view of the semiconductor device 1 shown in Figure 13.Figure 13 illustrates along the XIII-XIII direction of Figure 14, i.e. the truncation surface of the middle section of the gate electrode 50 of the grid length direction of semiconductor device 1.In fig. 14, the end of the LOCOS dielectric film 60 below gate electrode 50 represented by dashed line, omits gate insulating film 40.
As shown in figure 14, the surrounding on high concentration source region 22 and high concentration drain region 32 is surrounded by LOCOS dielectric film 60.By forming LOCOS dielectric film 60 on low concentration drain region 31, there is the withstand voltage effect improved between gate electrode 50 and drain region 30.
Figure 15 illustrates along the truncation surface in the channel region in the grid width direction in the XV-XV direction of Figure 14, i.e. semiconductor device 1.Truncation surface shown in Figure 15 represents identical structure with the truncation surface shown in Fig. 1.
In the semiconductor device 1 shown in Figure 13 ~ Figure 15, the concentration of the N-shaped impurity in neighboring area S near the border between gate insulating film 40 and the LOCOS dielectric film 60 formed on low concentration source region 21 and on low concentration drain region 31, gate electrode 50 is formed lower than the concentration of the N-shaped impurity in the middle section of gate electrode 50.Therefore, the end of the LOCOS dielectric film 60 below the neighboring area S of gate electrode 50, compared with the middle section of gate electrode 50, is difficult to cause channel inversion.That is, in the neighboring area S of gate electrode 50, threshold voltage partly rises.
Therefore, according to the semiconductor device 1 of the 2nd execution mode of the present invention, the periphery gate threshold voltage V (th) 2 in the neighboring area S of gate electrode 50 sets higher than the central gate threshold voltage V (th) 1 in the middle section of gate electrode 50.Its result, according to the semiconductor device 1 of the 2nd execution mode, even if in the MOS transistor of LOCOS off-set construction, also can suppress the generation of the leakage current between source region 20 and drain region 30.Other are identical with the 1st execution mode reality, omit the record repeated.
Figure 16 illustrates other example of the semiconductor device 1 of the 2nd execution mode.In the semiconductor device 1 shown in Figure 13 ~ Figure 15, in all borderline regions between the LOCOS dielectric film 60 formed on low concentration source region 21 and on low concentration drain region 31 and gate insulating film 40, the concentration of the N-shaped impurity in the concentration ratio middle section of the N-shaped impurity of gate electrode 50 is low.But, as shown in figure 16, also can only in the end of the channel width dimension of gate electrode 50, from the border T between gate insulating film 40 and LOCOS dielectric film 60 to the middle section of gate electrode 50 across distance w, the concentration of the N-shaped impurity in the concentration ratio middle section of the N-shaped impurity of gate electrode 50 is low.
When manufacturing the semiconductor device 1 shown in Figure 13 ~ Figure 15, manufacture method such as described below can be adopted.Namely, as shown in figure 17, well area 13 forms low concentration source region 21 and low concentration drain region 31.The photoresist film such as formed using photoetching technique, as mask, forms low concentration source region 21 and low concentration drain region 31 by ion implantation.
Then, as shown in figure 18, when forming LOCOS dielectric film 60, on low concentration source region 21 and on low concentration drain region 31, LOCOS dielectric film 60 is formed.
Afterwards, as illustrated with reference to Fig. 7 ~ Fig. 8, gate insulating film 40, gate electrode 50 is formed.Then, as illustrated with reference to Figure 10 ~ Figure 11, sidewall 51, high concentration source region 22 and high concentration drain region 32 is formed.
And then, on whole after painting photoresist film 91, as shown in figure 19, be exposed to the mode above the borderline region between LOCOS dielectric film 60 and gate insulating film 40 formed on low concentration source region 21 and on low concentration drain region 31 with gate electrode 50, composition is carried out to photoresist film 91.Now, in the end of the channel width dimension of gate electrode 50, be at least exposed to the mode of the middle section from the border T between gate insulating film 40 and LOCOS dielectric film 60 to gate electrode 50 across distance w with gate electrode 50, composition is carried out to photoresist film 91.
Then, using photoresist film 91 as mask, the p-type foreign ion of boron (B) etc. is injected into gate electrode 50.Thus, implanted with p-type impurity in the neighboring area S of gate electrode 50.Its result, the N-shaped impurity concentration of the neighboring area S of gate electrode 50 becomes lower than the N-shaped impurity concentration of the middle section of gate electrode 50.Removing photoresist film 91, completes the semiconductor device 1 shown in Figure 13 ~ Figure 15.
According to the manufacture method of the semiconductor device 1 of the 2nd execution mode described above, can by near the borderline region between the gate insulating film 40 of semiconductor device 1 and the LOCOS dielectric film 60 formed on low concentration source region 21 and on low concentration drain region 31, periphery gate threshold voltage V (th) 2 sets higher than the central gate threshold voltage V (th) 1 in the middle section of gate electrode 50.Therefore, it is possible to provide the generation of the leakage current that inhibit between source region 20 and drain region 30, the semiconductor device 1 of LOCOS off-set construction.
(other execution mode)
As mentioned above, although describe the present invention by the 1st and the 2nd execution mode, should not be construed as description and the accompanying drawing of the part forming the disclosure, limit the present invention.Those skilled in the art, can from the clearly various replacement execution mode of the disclosure, embodiment and application technology.
Such as, also as Semiconductor substrate 10, the silicon substrate not being formed with epitaxial loayer 12 and well area 13 can be adopted, this silicon substrate formed source region 20 and drain region 30.
As mentioned above, the present invention comprises the various execution modes etc. do not recorded herein certainly.Therefore, technical scope of the present invention is from above-mentioned explanation, is determined by the specific item of the invention in corresponding claim.
Claims (9)
1. a semiconductor device, is characterized in that comprising:
Semiconductor substrate;
The source region of the 1st conductivity type and drain region, it is separated from each other and is formed in the part on the top of described Semiconductor substrate;
Gate insulating film, it comprises the region clipped by described source region and described drain region, and configuration is on the semiconductor substrate;
LOCOS dielectric film, it is centered around the surrounding of the channel region formed between described source region and described drain region and configures continuously with described gate insulating film on the semiconductor substrate, gate insulation thickness described in Film Thickness Ratio; And
Gate electrode, it is made up of polysilicon film, and configures continuously across on the described LOCOS dielectric film on described gate insulating film and around described gate insulating film in the region clipped by described source region and described drain region,
Gate threshold voltage in the neighboring area of described gate electrode is higher than the gate threshold voltage in the middle section of described gate electrode, the gate threshold voltage when difference of the gate threshold voltage in the middle section of the gate threshold voltage in the neighboring area of described gate electrode and described gate electrode is greater than design and the difference of drain voltage, wherein, the neighboring area of this gate electrode is the end of the channel width dimension of this gate electrode.
2. semiconductor device according to claim 1, is characterized in that,
Different across the conductive-type impurity concentration in the conductive-type impurity concentration of the described gate electrode certain distance, described gate insulating film and the middle section of described gate electrode to the middle section of described gate electrode from the border between described gate insulating film from described LOCOS dielectric film.
3. semiconductor device according to claim 2, is characterized in that,
Be the 2nd conductivity type from described border across the conduction type of the described gate electrode described certain distance, described gate insulating film, the conduction type in the middle section of described gate electrode is the 1st conductivity type.
4. the semiconductor device according to any one in claims 1 to 3, is characterized in that,
Described source region is the structure be formed by connecting by the low concentration source region of the 1st conductivity type formed in the region close to described gate electrode and the impurity concentration of the 1st conductivity type high concentration source region higher than described low concentration source region,
Described drain region is the structure be formed by connecting by the low concentration drain region of the 1st conductivity type formed in the region close to described gate electrode and the impurity concentration of the 1st conductivity type high concentration drain region higher than described low concentration drain region.
5. semiconductor device according to claim 4, is characterized in that,
Described low concentration source region and described low concentration drain region are configured with described LOCOS dielectric film.
6. a manufacture method for semiconductor device, is characterized in that comprising the steps:
By LOCOS method, the part on the surface of Semiconductor substrate forms LOCOS dielectric film;
In the remaining region in region defining described LOCOS dielectric film, with described LOCOS dielectric film continuous print mode, the surface of described Semiconductor substrate forms the gate insulating film that described in Film Thickness Ratio, LOCOS dielectric film is thin;
The gate electrode be made up of polysilicon film is formed continuously across on the described LOCOS dielectric film on described gate insulating film and around described gate insulating film;
Clip the region that defines described gate electrode and form source region and the drain region of the 1st conductivity type on the top of described Semiconductor substrate; And
Make the gate threshold voltage in the neighboring area of described gate electrode higher than the gate threshold voltage in the middle section of described gate electrode, gate threshold voltage when making the difference of the gate threshold voltage in the middle section of the gate threshold voltage in the neighboring area of described gate electrode and described gate electrode be greater than design and the difference of drain voltage, and across certain distance, conductive-type impurity is injected to the described gate electrode described gate insulating film from the border between described gate insulating film and described LOCOS dielectric film to the middle section of described gate electrode, wherein, the neighboring area of this gate electrode is the end of the channel width dimension of this gate electrode.
7. the manufacture method of semiconductor device according to claim 6, is characterized in that,
The step forming described source region comprises the steps: the low concentration source region forming the 1st conductivity type in the region close to described gate electrode; And the high concentration source region making the impurity concentration of the 1st conductivity type higher than described low concentration source region is connected with described low concentration source region and forms described source region,
The step forming described drain region comprises the steps: the low concentration drain region forming the 1st conductivity type in the region close to described gate electrode; And the high concentration drain region making the impurity concentration of the 1st conductivity type higher than described low concentration drain region is connected with described low concentration drain region and forms described drain region.
8. the manufacture method of semiconductor device according to claim 7, is characterized in that,
Described LOCOS dielectric film is formed on described low concentration source region He on described low concentration drain region.
9. the manufacture method of the semiconductor device according to any one in claim 6 to 8, is characterized in that,
By injecting the step of the impurity of the 2nd conductivity type to described gate electrode, the described neighboring area of described gate electrode is made to become the 2nd conductivity type.
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| CN106024899B (en) * | 2016-07-15 | 2019-05-21 | 中国科学院微电子研究所 | Semiconductor field effect transistor and manufacturing method thereof |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6103562A (en) * | 1998-01-14 | 2000-08-15 | Lg Semicon Co., Ltd. | Method of making semiconductor device with decreased channel width and constant threshold voltage |
| CN1359156A (en) * | 2000-09-01 | 2002-07-17 | 精工电子有限公司 | CMOS semiconductor device and making method |
| CN101771078A (en) * | 2008-12-30 | 2010-07-07 | 联发科技股份有限公司 | Metal-oxide semiconductor transistor construction |
| CN101800244A (en) * | 2009-02-06 | 2010-08-11 | 精工电子有限公司 | Semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
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| JPH09312399A (en) * | 1995-07-14 | 1997-12-02 | Seiko Instr Inc | Semiconductor device and manufacture thereof |
| US5998848A (en) * | 1998-09-18 | 1999-12-07 | International Business Machines Corporation | Depleted poly-silicon edged MOSFET structure and method |
| JP2001156290A (en) * | 1999-11-30 | 2001-06-08 | Nec Corp | Semiconductor device |
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| JP4623294B2 (en) * | 2005-09-12 | 2011-02-02 | セイコーエプソン株式会社 | Manufacturing method of semiconductor device |
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| JP2010087436A (en) * | 2008-10-03 | 2010-04-15 | Nec Electronics Corp | Semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6103562A (en) * | 1998-01-14 | 2000-08-15 | Lg Semicon Co., Ltd. | Method of making semiconductor device with decreased channel width and constant threshold voltage |
| CN1359156A (en) * | 2000-09-01 | 2002-07-17 | 精工电子有限公司 | CMOS semiconductor device and making method |
| CN101771078A (en) * | 2008-12-30 | 2010-07-07 | 联发科技股份有限公司 | Metal-oxide semiconductor transistor construction |
| CN101800244A (en) * | 2009-02-06 | 2010-08-11 | 精工电子有限公司 | Semiconductor device |
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