CN102446559A - Fault injection method based on dual-port SRAM - Google Patents
Fault injection method based on dual-port SRAM Download PDFInfo
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- CN102446559A CN102446559A CN2011102612954A CN201110261295A CN102446559A CN 102446559 A CN102446559 A CN 102446559A CN 2011102612954 A CN2011102612954 A CN 2011102612954A CN 201110261295 A CN201110261295 A CN 201110261295A CN 102446559 A CN102446559 A CN 102446559A
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- 238000002347 injection Methods 0.000 title abstract description 12
- 239000007924 injection Substances 0.000 title abstract description 12
- 238000012360 testing method Methods 0.000 claims abstract description 35
- 230000000694 effects Effects 0.000 abstract description 5
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Abstract
The invention discloses a fault injection method based on a dual-port SRAM (static random access memory), which comprises the following steps: a first encoding selector is arranged behind an encoder of a first port of the SRAM; a second coding selector is arranged behind the coder of the second port; and globally setting an external control signal TEST in the SRAM to be applied to the first coding selector and the second coding selector. The method for realizing the fault injection in the chip provided by the invention has the advantages that only one control signal is needed to control outside the chip, other external injection signals are not needed to be introduced, only a small internal chip area is occupied, and the fault injection test can be quickly realized. Meanwhile, because the method only injects logic equivalent faults and does not directly inject errors, the test power consumption is reduced. In addition, the method is simple and quick in test operation, and has the effects of low cost and high test coverage rate.
Description
Technical field
The present invention relates to SRAM (SRAM) technical field, relate in particular to the fault filling method of a kind of dual-port SRAM, be used to adopt the SRAM of Hamming code decoding method design reinforcement.
Background technology
To fault-tolerant design SRAM, on accelerator, carry out single particle effect test before, chip all can be simulated under conventional environment usually, and Design of Reinforcement is verified.The method of now generally taking fault to inject is simulated the single-particle inversion effect.Fault injection system is the instrument to its validity of evaluation of fault-tolerant design exploitation.It is a kind of technology that produces fault of simulating that fault is injected, and it is to inject among by verification system or fault hardware or software is set through artificial means. make the inefficacy of system be able to take place, thereby can verify validity to the fault-tolerant design of fault.Mainly contain two kinds of schemes at present, i.e. software injection method and hardware injection method.
Software fault injects through deletion, increase or change lag characteristic to program statement or data and comes simulated failure, mainly is through the content in the reprogramming core image, or utilizes the method for program mutation to inject fault.The software fault injection method is flexible, but needs to increase additional hardware circuit.
It generally is from the IC chip pin, to apply external signal by force that hardware fault is injected, and wherein is divided into two kinds of forms that superpotential and excess current are injected again.Hardware fault is injected the goal systems effect, the normal hardware effort environment of goal systems is affected, thereby produces instantaneous or permanent fault, this goal systems is moved under this failure environment, thereby tested its fault freedom.The hardware fault injected system needs special equipment that test specific voltage (electric current) is provided, and might cause the hardware damage, so cost is bigger.
Because the method cost that hardware fault is injected is bigger, therefore at present modes that adopt software to inject more.Software fault injects often need design a special fault injection system at chip internal.To SRAM, can carry out the fault implant operation to each of every group of data.But like this, spending of hardware is bigger, and can bring many extra power consumptions.
Summary of the invention
The technical matters that (one) will solve
In order to reach the standard grade and to carry out fault simulation before the test carrying out accelerator, Design of Reinforcement is verified, simultaneously take into account cost and construction cycle again, the invention provides a kind of software fault method for implanting based on dual-port SRAM.
(2) technical scheme
For achieving the above object, the invention provides a kind of fault filling method based on dual-port SRAM, this method comprises: one first coding selector switch 11 is set behind the scrambler of SRAM first port; One second coding selector switch 12 is set behind the scrambler of second port; And in the SRAM overall situation external control signal TEST is set and is applied to the first coding selector switch 11 and second and encodes on the selector switch 12.
In the such scheme, the input end of the said first coding selector switch 11 connects the first coding selector switch 11 and the second coding selector switch 12 respectively, and its output terminal connects the redundancy unit of storage first port coding among the dual-port SRAM.
In the such scheme, the input end of the said second coding selector switch 12 connects the second coding selector switch 12 and the first coding selector switch 11 respectively, and its output terminal connects the redundancy unit of storage second port coding among the dual-port SRAM.
In the such scheme, saidly in the SRAM overall situation external control signal TEST is set and is applied to the first coding selector switch 11 and second and encodes on the selector switch 12, comprising:
The TEST signal is controlled the first coding selector switch 11 and the second coding selector switch 12 simultaneously; When the TEST signal when low; The first coding selector switch 11 is selected the coding from 11 outputs of the first coding selector switch, and the second coding selector switch 12 is selected the coding from 12 outputs of the second coding selector switch; When TEST signal when being high, the first coding selector switch 11 is selected the coding from 12 outputs of the second coding selector switch, and the second coding selector switch 12 is selected the coding from 11 outputs of the first coding selector switch.
(3) beneficial effect
The present invention is directed to dual-port SRAM and designed a kind of new fault filling method, outer of sheet needs a control signal control to get final product, and need not to introduce other outsides and injects signal, and only take inside chip area seldom, can realize fault injection test quickly.Simultaneously, injecting because this method is the logically equivalent fault, is not direct injection mistake, has therefore reduced testing power consumption.This method test operation is simple, fast, has low cost, the effect of high test coverage.
Description of drawings
Fig. 1 is the method synoptic diagram that injects based on dual-port SRAM fault according to the embodiment of the invention.
Embodiment
For making the object of the invention, technical scheme and advantage clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, to further explain of the present invention.
Is that example is described principle of the present invention and characteristic below in conjunction with accompanying drawing with the dual-port SRAM based on the Hamming code encoding and decoding technique, and institute gives an actual example and only is used to explain the present invention, is not to be used to limit scope of the present invention.
Fault filling method based on dual-port SRAM provided by the invention; Be behind the scrambler of original each port, a coding selector switch to be set respectively; The input end of coding selector switch connects the scrambler output terminal of two ports respectively, and the output terminal of selector switch then connects the code storage unit of port separately.The coding selector switch is all controlled by external control signal TEST.When the TEST signal was low level, SRAM got into normal mode of operation, and the coding selector switch is still selected the coding of original port; When the TEST signal was high level, SRAM carried out the fault injection way, and selector switch is selected the coding from the another one port.Through rational data are set at adjacent port, just can obtain the efficient coding that fault is injected, just can see the result who exports after fault is injected in the SRAM decoding end then.
Fig. 1 is the method synoptic diagram that injects based on dual-port SRAM fault according to the embodiment of the invention.In the Hamming code SRAM design of present embodiment based on dual-port; One first coding selector switch 11 is set behind the scrambler of SRAM first port; The input end of this first coding selector switch 11 connects the first coding selector switch 11 and the second coding selector switch 12 respectively, and its output terminal connects the redundancy unit of storage first port coding among the dual-port SRAM.One second coding selector switch 12 is set behind the scrambler of second port; The input end of this second coding selector switch 12 connects the second coding selector switch 12 and the first coding selector switch 11 respectively, and its output terminal connects the redundancy unit of storage second port coding among the dual-port SRAM.In the SRAM overall situation external control signal TEST being set then is applied on the first coding selector switch 11 and the second coding selector switch 12; The TEST signal is controlled the first coding selector switch 11 and the second coding selector switch 12 simultaneously; When the TEST signal when low; The first coding selector switch 11 is selected the coding from 11 outputs of the first coding selector switch, and the second coding selector switch 12 is selected the coding from 12 outputs of the second coding selector switch; When TEST signal when being high, the first coding selector switch 11 is selected the coding from 12 outputs of the second coding selector switch, and the second coding selector switch 12 is selected the coding from 11 outputs of the first coding selector switch.
In order to understand conveniently, be the A port with first port definition, second port definition is the B port, and the first coding selector switch 11 is defined as the coding selector switch of A port, and the second coding selector switch 12 is defined as the coding selector switch of B port.Wherein, the coding selector switch of an A port is set behind A port scrambler, the input end of the coding selector switch of this A port connects respectively from the scrambler of A port and the scrambler of B port, and the redundancy unit of storage A port coding in the memory cell array is received in its output.Equally; The coding selector switch of a B port is set behind B port scrambler; The input end of the coding selector switch of this B port connects respectively from the scrambler of B port and the scrambler of A port, and the redundancy unit of storage B port coding in the memory cell array is then received in its output.Be provided with on the SRAM overall situation on the coding selector switch of coding selector switch and B port that an external control signal TEST is applied to the A port then, the TEST signal is controlled the coding selector switch of A port and the coding selector switch of B port simultaneously.When the TEST signal when low; The coding selector switch of A port or the coding selector switch of B port can be selected the coding of oneself originally; The coding selector switch that is the A port can be selected the coding from the output of A port scrambler, and the coding selector switch of same B port can be selected the coding from the output of B port scrambler; When TEST signal when being high, the coding selector switch of A port or the coding selector switch of B port then can be selected the coding of the scrambler output of another port.The coding selector switch that is the A port can be selected the coding from the output of B port scrambler, and the coding selector switch of same B port can be selected the coding from the output of A port scrambler.During test,, rational data just can obtain the efficient coding that fault is injected through being set at the another one port.Just can see the result after fault is injected in the output of decoding end data then.
This method can be succinct fast all data units of simulation, dibit the situation of upset takes place, and inject signal without any need for unnecessary fault, both reduced the IO pin, reduced testing power consumption again.
Above-described specific embodiment; The object of the invention, technical scheme and beneficial effect have been carried out further explain, and institute it should be understood that the above is merely specific embodiment of the present invention; Be not limited to the present invention; All within spirit of the present invention and principle, any modification of being made, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (4)
1. the fault filling method based on dual-port SRAM is characterized in that, this method comprises:
One first coding selector switch (11) is set behind the scrambler of SRAM first port;
One second coding selector switch (12) is set behind the scrambler of second port; And
In the SRAM overall situation external control signal TEST being set is applied on the first coding selector switch (11) and the second coding selector switch (12).
2. the fault filling method based on dual-port SRAM according to claim 1; It is characterized in that; The input end of the said first coding selector switch (11) connects the first coding selector switch (11) and the second coding selector switch (12) respectively, and its output terminal connects the redundancy unit of storage first port coding among the dual-port SRAM.
3. the fault filling method based on dual-port SRAM according to claim 1; It is characterized in that; The input end of the said second coding selector switch (12) connects the second coding selector switch (12) and the first coding selector switch (11) respectively, and its output terminal connects the redundancy unit of storage second port coding among the dual-port SRAM.
4. the fault filling method based on dual-port SRAM according to claim 1 is characterized in that, saidly in the SRAM overall situation external control signal TEST is set and is applied to the first coding selector switch (11) and second and encodes on the selector switch (12), comprising:
The TEST signal is controlled the first coding selector switch (11) and the second coding selector switch (12) simultaneously; When the TEST signal when low; The first coding selector switch (11) is selected the coding from first coding selector switch (11) output, and the second coding selector switch (12) is selected the coding from second coding selector switch (12) output; When TEST signal when being high, the first coding selector switch (11) is selected the coding from second coding selector switch (12) output, and the second coding selector switch (12) is selected the coding from first coding selector switch (11) output.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100091536A1 (en) * | 2008-10-14 | 2010-04-15 | Mosaid Technologies Incorporated | Composite memory having a bridging device for connecting discrete memory devices to a system |
| CN101964205A (en) * | 2010-09-17 | 2011-02-02 | 记忆科技(深圳)有限公司 | ECC (Error Correction Code) module dynamic multiplexing system and method based on solid state disk |
| CN102164025A (en) * | 2011-04-15 | 2011-08-24 | 北京邮电大学 | Coder based on repeated coding and channel polarization and coding/decoding method thereof |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100091536A1 (en) * | 2008-10-14 | 2010-04-15 | Mosaid Technologies Incorporated | Composite memory having a bridging device for connecting discrete memory devices to a system |
| CN101964205A (en) * | 2010-09-17 | 2011-02-02 | 记忆科技(深圳)有限公司 | ECC (Error Correction Code) module dynamic multiplexing system and method based on solid state disk |
| CN102164025A (en) * | 2011-04-15 | 2011-08-24 | 北京邮电大学 | Coder based on repeated coding and channel polarization and coding/decoding method thereof |
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Application publication date: 20120509 |