CN102414815B - 具有散热器的多管芯半导体封装 - Google Patents
具有散热器的多管芯半导体封装 Download PDFInfo
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Abstract
一种半导体器件包括位于基板上的第一及第二堆迭半导体管芯(die)。在该基板上设置盖体以包覆所述半导体管芯。该盖体具有向下延伸进入开口的多个鳍片。所述鳍片其中至少一些较其它一些长。该盖体附着于该基板,所述较长的鳍片向下延伸至未由该第一管芯占用之该基板区域的上方,所述较短的鳍片向下延伸至未由该第二管芯覆盖之该第一管芯区域的上方。热接口材料填充该开口的剩余部分,并与所述管芯、该基板以及所述鳍片热连通。该盖体可由金属成型。可利用热结合材料将该盖体与最顶端的管芯结合。该热结合材料可为液态金属或类似物。
Description
技术领域
本发明涉及半导体器件,尤其涉及堆迭半导体管芯的半导体封装。
背景技术
当前的半导体器件通常包括管芯、基板、一个或多个金属化层、输入/输出针脚或球脚、散热器(heat spreader),并可选择包括散热件(heat sink)。管芯包含器件的有源电路。管芯通常设于基板上或设于基板的开口中。一个或多个金属化层包括焊垫,其称作焊指,用于互连金属化层与管芯的管芯焊垫。管芯焊垫相应连接管芯的有源电路。金属化层在基板内布设从管芯至输入/输出针脚或球脚的电性连接线路。
利用传统的打线技术,籍由导线连接管芯焊垫与焊指,可电性耦接管芯焊垫与焊指。或者,可设置管芯使其作用面朝向基板。管芯焊垫延伸自有源面,并可利用延伸自管芯的电性导电凸块连接焊指。由于作用面朝下,这样的半导体器件通常被称为“倒装芯片”封装。
在当代的半导体封装中,对更高性能和更小尺寸的不断追求导致更高的操作频率以及更高的封装密度(更多的晶体管)。但是,操作时,在这样一管芯上的电路消耗可观的电能。该能量必然产生热量,而该热量必须自该封装中排出。可使用传统的散热器及散热件排出该管芯产生的热量。但是,由于大多数热量产生于管芯中,因此芯片封装中热能的相对分布往往很不均匀。
最近,为在单个封装中包括更多的晶体管,在单个半导体器件中可能封装有多个管芯。例如,管芯可彼此堆迭,并分别与基板互连。为此,美国专利号7,361,986揭露一半导体器件,其具有两个堆迭管芯,第一管芯以倒装芯片方式设置,另一管芯设于该第一管芯顶部,并打线结合基板。
随着多管芯几何变得更加复杂,以及晶体管数量的增加,电子管芯的散热问题变得愈加严重。
因此,需要提供半导体封装以辅助多管芯的散热。
发明内容
在本发明的一实施例示例中,半导体器件包括位于基板上的第一及第二堆迭半导体管芯。在该基板上设置盖体以包覆所述半导体管芯。该盖体具有向下延伸进入开口的多个鳍片。所述鳍片其中至少一些较其它一些长。该盖体附着于该基板,所述较长的鳍片向下延伸至未由该第一管芯占用之该基板区域的上方,所述较短的鳍片向下延伸至未由该第二管芯覆盖之该第一管芯区域的上方。热接口材料填充该开口的剩余部分,并与所述管芯、该基板以及所述鳍片热连通。该盖体可由金属成型。可利用热结合材料将该盖体与最顶端的管芯结合。该热结合材料可为液态金属或类似物。
依据本发明的一实施态样,提供一半导体器件,包括:基板;第一管芯和第二管芯,其上分别形成有集成电路;该第一管芯由该基板支持;该第二管芯设于该第一管芯顶部;盖体,定义一开口,该盖体包括向下延伸进入该开口的多个鳍片,所述鳍片其中至少一些较其它一些长,该盖体附着至该基板,所述较长的鳍片向下延伸至未由该第一管芯占用之该基板区域的上方,所述较短的鳍片向下延伸至未由该第二管芯覆盖之该第一管芯区域的上方;热接口材料,填充该开口的剩余部分,并与该第一管芯和第二管芯、该基板以及所述鳍片热连通。
依据本发明另一实施态样,提供一种半导体器件,包括:基板;管芯,其上形成有集成电路,并且该管芯设于该基板上;盖体,定义一开口,该盖体包括向下延伸进入该开口的多个鳍片;金属沉积,形成于该管芯的顶部;热绝缘材料,填充该开口的剩余部分,并与该管芯、该金属沉积、该基板以及所述鳍片热连通。
依据本发明一实施态样,提供一种形成半导体器件的方法,包括:形成定义一开口的盖体以及延伸进入该开口的多个鳍片;在基板上以堆迭方式设置第一半导体管芯及第二半导体管芯;使用热接口材料填充该盖体的该开口;设置该盖体,使该热接口材料位于该基板上以包覆该第一半导体管芯及第二半导体管芯,并使该热接口材料接触所述鳍片、所述管芯以及该基板。
下面结合附图阅读本发明特定实施例的说明之后,本发明的其它态样及特征对于本领域的技术人员将显而易见。
附图说明
下面的附图仅例示本发明实施例。
图1例示本发明一实施例的半导体器件的剖视图。
图2为图1之半导体器件的立体图。
图3为图1之半导体器件的散热器的剖视图。
图4为图3之散热器的底部平面视图。
图5A和图5B例示依据本发明一实施例在图1之器件的管芯上的选择性金属沉积。
图6例示本发明另一实施例的半导体器件的剖视图。
图7例示本发明另一实施例的半导体器件的剖视图。
图8例示本发明另一实施例的半导体器件的剖视图。
具体实施方式
图1例示本发明一实施例的半导体器件10的剖视图。如图所示,半导体器件10包括基板12,多个管芯20、22,封装针脚16以及盖体30。将显而易见的是,盖体30充当散热器。
在基板12内,邻近基板12的底部表面形成多个金属化层14。金属化层14可籍由微导孔18彼此连接,并电性互连管芯20、22与封装针脚16。
示例基板12为单侧式:仅邻近基板12的一侧形成金属化层14。方便地,在单侧基板中,可避免在基板之相对两侧的金属化层之间形成贯穿基板之整体高度的电镀通孔。当然,基板12可由双侧基板替代。
封装针脚16可为针脚、球栅阵列型焊球或任意其它已知的电性封装互连。
管芯20由基板12支持。在所示实施例中,管芯20设于基板12的顶部表面上,或者可嵌入基板12中,如美国专利公开号2007/0108595所述,其内容通过参考而纳入本申请。管芯20以作用面朝下的方式设置,管芯焊垫24连接管芯20与金属化层14。标准的微导孔形成用于耦接管芯20的凸块下金属化层(UBM;under bumpmetallization)与基板12的金属化层14。底部填充胶体(未图示)可进一步将管芯20附着至基板12。
管芯22设于管芯20顶部。管芯22可籍由自管芯22周边的管芯触点延伸的打线结合基板12。或者,可籍由形成于管芯20、22中的硅微导孔使管芯彼此直接电性互连。
例如,管芯20可代表通用处理器、图形处理器,或具有一个或多个处理器内核的其它类似器件。管芯22为可由管芯20中的处理器读取的静态或动态存储器(DRAM、SDRAM等)形式的处理器可读存储器。当然,管芯20、22可代表其它电子器件,例如专用集成电路、微控制器、现场可编程门阵列等。可透过基板12实现管芯20与22之间的电性互连。
从上面可看出,基板12之表面的部分区域由管芯20覆盖,另一部分区域(基板12之表面的剩余部分)则未由管芯覆盖。另外,管芯20的部分区域由管芯22覆盖。地形上而言,表面设有管芯20、22的基板12分为具有三种不同高度的区域。
盖体30充当器件10的盖体以及散热器。盖体30籍由其边缘的胶粘剂附着至基板12,如图2详细显示。具体而言,由环氧树脂等形成的胶粘剂接缝38连接盖体30的边缘与基板12。盖体30与基板12之间的区域由热接口材料(TIM;thermal interface material)50填充。在所述实施例中,热接口材料50为粘性、半粘性、液态或类似的热接口材料。构成热接口材料50的合适材料可为无机凝胶、有机凝胶、油脂等。可从日本东京的信越化学(Shin-Etsu Chemicals)获得合适的凝胶,例如,编号为Shin-Etsu MicroSI x23-7809的凝胶。尽管当前可用的许多油脂可自局部热量区域扩散(或被“抽出”),但合适的油脂,例如G751热油脂,将为本领域的技术人员所知。
盖体30的顶部与具有管芯20、22的基板12的间距变化取决于管芯20、22与基板12组合的高度。对于具有大体平坦之顶部表面的盖体,与重迭管芯20、22对应的区域与盖体30最接近。与未重迭管芯22之管芯20对应的区域距离盖体30较远。与未设管芯20/22之基板12对应的区域距离盖体30最远。
图3和图4显示盖体30的详细视图。如图所示,盖体30大体呈圆顶形(dome shaped),具有平坦的顶部40以及向下延伸的外围壁34。顶部40及自顶部40向下延伸的外围壁34定义开口32。显而易见,由盖体30定义的开口32覆盖基板12并容置管芯20、22。
盖体30进一步包括多个鳍片60和62,自盖体30的平坦顶部40向下延伸。鳍片60和62向下延伸进入开口32。在示例盖体30中,鳍片60和62大体呈圆柱体形,具有均匀的圆形水平剖面。通常,鳍片60、62具有1μm2或更大的剖面面积。可实验确定优选的剖面面积。不过,本领域的技术人员将意识到,鳍片60、62的剖面不必均匀或呈圆形。其可具有椭圆形、正方形或长方形的剖面,均匀的、锥形的或任意其它合适的形状。
类似地,顶部40不必平坦,以及可具有另一合适的形状。
如图3和图4进一步所示,鳍片60的长度不同于鳍片62。当盖体30附着于基板12,而在与管芯22对齐的区域中无鳍片时,较短的鳍片62邻近与管芯20(并且非管芯22)对齐的盖体30的区域延伸。最后,较长的鳍片60对齐未由管芯22或20占用的区域或在其中向下延伸。
通常,较短的鳍片自盖体30的表面40延伸一定长度,以使其不会延伸超过管芯22的整体厚度。较长的鳍片60大体延伸至基板12,因此,其长度接近管芯22和20的组合厚度。
盖体30可由模压导热材料形成,例如包括铝、钢等的金属。盖体30(包括鳍片60/62)可例如籍由冲压、模压或使用其它传统的制造技术一体成型。或者,盖体30可由另一导热材料形成,例如合适的陶瓷、合金等。
热接口材料50填充开口32的剩余部分,并且方便地热连接管芯20、22与盖体30的鳍片60、62。另外,热接口材料50热耦接盖体30与基板12,同时增加器件10的总体热容量。方便地,热接口材料50填充由堆迭管芯20和22的几何布局形成的几何角落。
另外,盖体30可直接附着至管芯22。例如,如图1所示,利用例如导热结合材料36,可将管芯22与盖体30结合。例如,可利用液态金属,例如镓、铟或纳米箔结合管芯22与盖体30,该材料可从活性纳米技术公司(Reactive Nanotechnologies Inc.)获得。为促进结合,可在管芯22的顶部表面涂布金属或焊料,以使结合材料36对管芯22更有粘性。
为制造器件22,可使用传统的方式,首先在基板12上设置管芯20、22。在此过程中,可根据需要电性及机械结合管芯20、22彼此以及基板12。结合材料36(以及管芯22上的任意涂层)可附着至管芯22。热接口材料50可填充预先形成的盖体30(包括鳍片60、62)的开口32。可在盖体30的周围设置环氧树脂滴38等。接着,可在基板12顶部设置盖体30。环氧树脂38可固化,从而使盖体30附着于基板12。
可选择使热接口材料50在制造结束后仍保持大体的粘性,阻止其变干。或者,可选择使热接口材料50于盖体位于基板12顶部时即部分或全部固化。
操作中,经由封装针脚16向器件10施加电源及电信号。透过金属化层14向管芯20、22提供信号及电源。藉由结合材料36、热接口材料50以及鳍片60、62将管芯20、22产生的热量传导至盖体30。热接口材料50和鳍片60、62用于在器件10中均匀分配热量。由于热接口材料50与基板12接触,因此热量同样耦接基板12。
最终,由于盖体30及基板12与环境热连通,因此热量经传导或对流而被传送至大气。外部风扇或其它冷却器件(未图示)可辅助传输自器件10散发的热量。
方便地,热接口材料50密封于开口32内,并可在器件10操作时永久保持粘性形式,亦即凝胶或液态。
为进一步促进自管芯20、22的热传递,可进一步使用金属沉积68覆盖管芯20、22朝上之表面的其中部分,如图5A所示。因此,管芯20之未接触管芯22的朝上表面可包括金属沉积68,如图5A或5B所示。类似地,管芯22的顶部表面可由此类沉积覆盖,以替代覆盖管芯22之顶部的任意金属层或附加至该金属层。如图5A所示,金属沉积68可为焊料构成的任意少许薄金属,其自管芯20的顶部表面延伸,进一步辅助热耦接管芯20与热接口材料50。这样形成的沉积充当附着至管芯20的散热件,以允许热量自管芯20向热接口材料50内传导。
可在管芯20的随机位置或特定位置施加少许薄金属例如焊料以形成沉积68。焊料可为本领域技术人员已知的传统锡/铅焊料或无铅焊料、银、金等。沉积68的厚度可在亚微米范围内(亦即小于1微米)。方便地,沉积68还可困住热接口材料50。其对于热接口材料50被抽离较大热量之局部区域的情况尤其有用。
应当了解,沉积68还可用于例如美国专利公开号2007/0108595所揭露之封装中的单管芯半导体上。
或者,沉积68可藉由导线或丝直接与盖体30连接,以进一步传导管芯20、22的热量。
在图6所示的替代实施例,可在盖体30附着另一散热件70,其具有向上延伸的鳍片。热接口材料例如热胶(未图示)可用于将散热件70附着至盖体30的顶部。散热件70可具有基座74、附着至盖体30的顶部表面40。向上延伸的鳍片72延伸自基座74,可将散热件70以及盖体30的热量传输至大气。鳍片72的形状和布局可为传统形式,并可例如为圆柱体形状、长方形或任意其它形状。
在另一替代实施例中,鳍片60/62可由热电冷却器或蒸汽室替代。为此,图7描述另一实施例的半导体10’,其大体与图1的实施例一致(与图1的实施例中的组件类似的组件使用(’)符号标示,并且将不再进行解释)。但是,盖体30’包括多个热电冷却鳍片60’/62’,其包括热电微冷却器(thermoelectric micro-cooler;μTec)92/94,该冷却器依赖于珀尔帖效应。典型的热电模块藉由在两陶瓷薄片之间设置一系列的P掺杂和N掺杂碲化铋半导体材料而制成。在该半导体两侧的陶瓷材料提供刚性及电性绝缘。该N型材料具有多余电子,而该P型材料缺乏电子。当电子自P向N移动时,其跃迁至较高的能状(吸收热能);当电子自N向P移动时,获得较低的能态(释放热能),从而为一侧提供冷却。热电微冷却器(μTEC)为已知技术,且市场上有售。如图7所示,一个或多个热电微冷却器92、94可嵌入盖体30’的表面40’中以及全部或选定鳍片60’、62’中。可选择使嵌有热电微冷却器94的鳍片60’、62’邻近高散热的管芯20’、22’的局部区域。可外部供应直流电源(未图示)以向热电微冷却器92、94供电。又,开口32’可由适当的热接口材料50’填充,以耦接管芯20’、22’与鳍片60’、62’。
盖体30还可选择容置一个或多个蒸汽室。为此,图8显示另一实施例的半导体10”,其大体与图1的实施例一致(与图1之实施例中的组件相同的组件使用(″)符号标示,并且不再进行解释)。但是,盖体30”包括蒸汽室112以及热管114。在盖体30”之顶部的矩形容积槽(室)内引入液体116例如水,以形成蒸汽室112。蒸汽室112通常为盖体30”之顶部内的矩形空腔。管芯20”、22”产生的热量使水分子蒸发。当蒸汽凝结时,在室112的顶壁释放热量,从而获得理想的冷却效果。该过程不断重复。另外,鳍片60”/62”(类似鳍片60/62)还可为中空,并可引入水,以形成热管114。管114连接盖体30”之基座中的蒸汽室112。热量经由管114向上传递至所连接的蒸汽室112。
鳍片之基座的形状及尺寸、鳍片60/62的不同群集以及大体平坦之区域的不同形状的各种变化将对本领域的技术人员显而易见,而不背离权利要求的范围。
应当了解,可方便地修改这里所揭露的实施例以包括两个以上管芯。例如,可堆迭三个或更多管芯。可相应修改盖体30,具有三种或更多不同长度的鳍片。类似地,基板12上可形成有彼此隔开的多个堆迭管芯。可相应在未由管芯占用的区域的上方以及管芯上方的区域中设置盖体30的鳍片。
方便地,盖体30/30’/30”的使用顾及管芯20、22(20’/22’或20”/22”)中的容差。开口32由鳍片60/62、热接口材料50以及结合材料36填充。因此,盖体30可容纳管芯20、22的厚度变化,同时保留管芯20、22至盖体30以及大气的热传递。
当然,上述实施例仅为说明性质,而非意图限制本发明。可对执行本发明的实施例作形式、组件布局、细节以及操作次序的变更。本发明意图在其权利要求定义的范围内包括所有此类变更。
Claims (18)
1.一种半导体器件,包括:
基板;
第一管芯和第二管芯,其上分别形成有集成电路;
该第一管芯由该基板支持;
该第二管芯设于该第一管芯顶部;
盖体,定义一空腔,该盖体包括向下延伸进入该空腔的多个鳍片,该盖体附着至该基板,所述多个鳍片包括第一组鳍片向下延伸至未由该第一管芯占用的该基板区域的上方以及第二组鳍片向下延伸至未由该第二管芯覆盖的该第一管芯区域的上方,所述第一组鳍片延伸长度远于所述第二组鳍片;
热结合材料,位于该第二管芯与该盖体之间,其热连接该第二管芯与该盖体;以及
热接口材料,填充该空腔的剩余部分,并与该第一管芯和第二管芯、该基板以及所述鳍片热连通。
2.如权利要求1所述的半导体器件,其中,该热结合材料包括液态金属。
3.如权利要求2所述的半导体器件,其中,该液态金属包括镓、铟的其中一者。
4.如权利要求1所述的半导体器件,进一步包括位于该第一管芯与第二管芯的至少其中一者的顶部表面上的金属沉积。
5.如权利要求4所述的半导体器件,其中,该金属沉积包括金、银、锡。
6.如权利要求1所述的半导体器件,进一步包括位于该第一管芯与第二管芯的至少其中一者的顶部表面上的纳米箔。
7.如权利要求4所述的半导体器件,其中,该金属沉积具有1微米的厚度。
8.如权利要求1所述的半导体器件,其中,该基板进一步包括金属化层,以及其中,该第二管芯打线结合该金属化层。
9.如权利要求1所述的半导体器件,其中,该第一管芯以倒装芯片方式设于该基板上。
10.如权利要求8所述的半导体器件,其中,该第一管芯与第二管芯透过该金属化层彼此电性互连。
11.如权利要求9所述的半导体器件,其中,该第一管芯与第二管芯透过硅微导孔彼此电性互连。
12.如权利要求1所述的半导体器件,其中,所述鳍片具有均匀的剖面。
13.如权利要求1所述的半导体器件,其中,该热接口材料包括热油脂与热凝胶的至少其中一者。
14.如权利要求1所述的半导体器件,进一步包括多个向上延伸的鳍片,其延伸自该盖体。
15.如权利要求1所述的半导体器件,进一步包括形成于该盖体中的至少一热电冷却器。
16.如权利要求15所述的半导体器件,其中,该至少一热电冷却器位于该多个鳍片的其中一者中。
17.如权利要求1所述的半导体器件,进一步包括形成于该盖体中的充满液体的蒸汽室。
18.如权利要求17所述的半导体器件,其中,所述鳍片其中至少一些定义中空热管,其与该充满液体的蒸汽室连通。
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Application Number | Priority Date | Filing Date | Title |
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US12/404,819 US7964951B2 (en) | 2009-03-16 | 2009-03-16 | Multi-die semiconductor package with heat spreader |
US12/404,819 | 2009-03-16 | ||
PCT/CA2010/000378 WO2010105346A1 (en) | 2009-03-16 | 2010-03-15 | Multi-die semiconductor package with heat spreader |
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CN102414815B true CN102414815B (zh) | 2015-07-29 |
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US (1) | US7964951B2 (zh) |
EP (1) | EP2409328A4 (zh) |
JP (1) | JP5661095B2 (zh) |
KR (1) | KR101550847B1 (zh) |
CN (1) | CN102414815B (zh) |
WO (1) | WO2010105346A1 (zh) |
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CN102414815A (zh) | 2012-04-11 |
JP2012520575A (ja) | 2012-09-06 |
EP2409328A1 (en) | 2012-01-25 |
KR20110139265A (ko) | 2011-12-28 |
EP2409328A4 (en) | 2014-01-15 |
WO2010105346A1 (en) | 2010-09-23 |
KR101550847B1 (ko) | 2015-09-07 |
US20100230805A1 (en) | 2010-09-16 |
US7964951B2 (en) | 2011-06-21 |
JP5661095B2 (ja) | 2015-01-28 |
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