CN102386285B

CN102386285B - Low-cost solar cells and methods for fabricating low cost substrates for solar cells

Info

Publication number: CN102386285B
Application number: CN201110253422.6A
Authority: CN
Inventors: 阿肖克·辛哈; 马雯
Original assignee: Sunpreme Ltd
Current assignee: Sunpreme Ltd
Priority date: 2010-08-24
Filing date: 2011-08-24
Publication date: 2014-12-10
Anticipated expiration: 2031-08-24
Also published as: CN102386285A

Abstract

The invention discloses low-cost solar cells and methods for fabricating low cost substrates for solar cells. Substrates for solar cells are prepared by etching a plurality of metallurgical grade wafers; depositing aluminum layer on backside of each wafer; depositing a layer of hydrogenated silicon nitride on front surface of each wafer; annealing the wafers at elevated temperature; removing the hydrogenated silicon nitride without disturbing the aluminum layer. A solar cell is then fabricated on the front surface of the wafer while the aluminum remains to serve as the back contact of the cell.

Description

The method of substrate for low-cost solar battery and manufacture low-cost solar battery

Technical field

The present invention relates to solar-energy photo-voltaic cell, relate more specifically to for the manufacture method of the low cost basis material of the battery for such and for the manufacture of the method for low cost battery and the battery device structure obtaining.

Background technology

Conventional has played the part of the biggest threat to earth peacefulness since glacial epoch last time by the fossil fuel generation energy.In all alternative energy sources, except energy-conservation, compare as ethanol, water power and wind energy with other approach, can to prove solar-energy photo-voltaic cell be the cleanest, ubiquitous and may be to select the most reliably.Principle is the simple solid-state p-n junction that light is converted to little direct voltage.Can be by battery stack to change input electrical network to Vehicular battery charging or by DC/AC.Can be used in the various semi-conducting materials of this object, silicon occupies 99% of photovoltaic solar cell output.Compared with the solar cell of other based compound semiconductor, although it has higher conversion efficiency, particularly in small size battery, but silicon is much abundant in the earth's crust, and the reliability being proven up to 30 years is provided under the various weathers in the whole world on weather-beaten roof.In addition, utilize the large-scale commercial applications manufacturing technology of silicon to use many decades and development well and be convenient to understand.Therefore, silicon probably remains the dominant basis material for solar cell.

But although through the development of 30 years, silica-based solar cell has not also been given play to its potential for extensive generating.The cost relevant with manufacturing solar cell to the major obstacle of its accreditation, in particular for manufacturing the raw material of solar cell, the cost of basis material (substrate).With in the situation of semiconductor microactuator chip only approximately compared with 10%, material accounts for the half that exceedes of solar cell total manufacturing cost.Sarcastically, because huge demand and high production cost, in fact synchronously increase with oil price for the price of the silicon materials of solar cell.For example, in the past few years, significantly increase for the production of the cost of the every kg of polycrystalline silicon material of solar energy silicon crystal chip, for thin film solar cell, for deposit this film silane gas cost and after deposition the NF of cleaning reaction device ₃the cost of gas similarly increases.On the contrary, semiconductor chip price (, the storage of every unit or logic function) reducing exponentially according to Moore's Law for 30 years in the past.This difference of learning curve may relate to the technical and material main difference with respect to the proportion (than technique and the design of the per unit area device density day by day improving) of cost.

According to the current state of this area, the manufacture of solar cells based on polysilicon is undertaken by three Main Stage.The first, for more moderate 25MW capacity plant produced is for a large amount of silicon wafers of substrate---typically 1,000,000 wafers monthly.The second, by forming p-n junction and metallizing, these wafer process are become to solar cell.The 3rd, then these wafers " encapsulation " are become for the module of installing and using in user facility.

Contain Si-H-Cl by thermal decomposition and produce ultra-pure polysilicon as the hazardous gas of dichlorosilane and trichlorosilane, be often referred to nine nine, i.e. 99.9999999% purity, manufactures the basic silicon wafer for solar cell.These gases are very easily to fire and poisonous.But, owing to endangering environment and health in the gasification of silicon, only there is in the world little factory in running, thereby cause the bottleneck of semiconductor and solar cell industry.The silicon gasification factory of new plan faces from local community based on environment and safety resistance deeply concerned.These factories also need a large amount of capital inputs and longer construction period.Therefore, between the demand and supply of naked silicon wafer, there is all the time imbalance.

Conventionally provide pure silicon (being called polysilicon, after the gasification and decomposition of silane-based compound) by the graininess that is applicable to semiconductor and solar cell application.Then make particle fusion and utilize crystal seed pulling single crystal rod or polycrystalline band.Or, polysilicon is cast to column.By the cylinder sawing, the moulding that lift and be polished to the circular wafer of 5～6 inches, can be cut to thereafter square wafer.Then for example in KOH, carry out wet chemical etching with texture at alkaline chemical.Utilize POCl ₃furnace diffusion forms p-n junction.Then utilize PECVD SiON to carry out anti-reflective film passivation.The silver muddle of silk screen printing is layed onto to n-profile and aluminium muddle is layed onto to p-profile.Then sintering this stick with paste to form and electrically contact.Finally, test battery classifying as their I-V curve according to their characteristic.

Above-mentioned technique is well-known and has implemented for many years in the industry.But, although most of cost (in semiconductor, be worth) be the silicon wafer of polishing to be converted to the process of functional integrated circuit, but in solar cell is manufactured, the process that the wafer after polishing is changed into functional solar cell is lower than the process cost of producing polished wafer self.That is to say, on commercial significance, the process that silicon wafer is transformed into solar cell is not the step of high additive value in whole solar panel manufacture chain.Therefore, can make the price of final solar panel significantly reduce with battery manufacture technology is mutually trans-in any improvement aspect the cost of manufacture initial wafer or reduction.

In order to overcome the problem for the silicon raw material of solar cell, be devoted to energetically to reduce the silicon amount of every watt of consumption of solar cell along two main approach.These are:

By wafer thickness from 500 μ m of standard be reduced to～below 200 μ m.This approach is subject to the restriction of die strength, and during high speed is by process equipment, wafer trend is broken.

2. adopt the various solar cell materials for example films of silicon, CdTe, CuInGaSe, typically on glass and on other more cheap substrate.In order to make irradiation on solar cell, electrode it-for example, by the transparent oxide conducting electricity (CTO) InSnO _xor ZnO ₂form.

In various thin film solar cell materials, silicon is the material of most cost effective equally.In this solar structure body, wafer thickness is reduced to approximately 1～10 μ m from 300～500 μ m.In this 1～10 μ m, the thickness of the film of most of deposition is typically made up of unadulterated Si-H polymer intrinsic amorphous layer, is abbreviated as ia-Si:H layer.Being clipped in this i aSi:H layer between n-type a-Si:H and the p-type a-Si:H film of doping provides and is absorbed into the required volume of shining sun light, thereby produces therein electron hole pair.Then these carrier diffusions produce the photovoltaic voltage and current for generating electricity to n-and the p-electrode of solar cell.But, because the Infrared wavelength of solar spectrum has the long transmission depth by silicon, thus a large amount of solar radiations lost, thus reduce the efficiency of photovoltaic conversion.That is to say, lost the quantum efficiency of conversion, special in the longer wavelength in infra-red range.Another inherent limitation of membrane structure is that the thickness limits of the diffusion length tunicle of minority carrier arrives much smaller than 10 μ m.This is the quality factor of the solar battery efficiency of prediction finished product.For pure crystalline silicon based solar battery, diffusion length typically is approximately 80 μ m.

There is the limitation of other essence in thin-film solar cell structure, with the solar cell based on silicon wafer exceed total solar panel market 80% compared with, so far these limitation by thin film solar cell production restriction approximately 5%.In these limitation, part is as follows:

1. due to identical with the price of polysilicon, for depositing silane gas underproduce of a-Si:H film, the cost fast rise of this gas very easily firing.Except silane, need a large amount of special NF for the production of the plasma-enhanced CVD reactor of solar energy film ₃the original position plasma that gas is carried out PECVD reactor purifies to guarantee that the normal operating time of production equipment is long.

2. the photovoltaic conversion efficiency of thin film silicon solar cell is low, is sometimes less than the half of the solar cell based on silicon wafer.

3. set up the required permanent plant of thin film solar cell factory and be the solar cell factory based on silicon wafer suitable for energy output nearly 10 times.Basic charge is mainly promoted by the plasma CVD reactor based on vacuum for depositing a-Si:H and SiN passivating film and for the PVD reactor based on vacuum that deposits CTO film.

As can be by above-mentioned understood, line of solar cells is already through being divided into Liang Ge camp: manage to utilize HIGH-PURITY SILICON wafer to obtain the solar cell camp based on silicon wafer of high battery efficiency, and in order to reduce costs the film camp that avoids using silicon wafer.Therefore, the camp based on silicon wafer is subject to the restriction of pure silicon wafer availability, and film camp is subject to the restriction of the conversion efficiency causing mainly due to the incomplete absorption of light in glass substrate, and is subject to producing the thicker required SiH of intrinsic silicon hydride absorbed layer ₄the restriction of the cost of gas.

Summary of the invention

For basic comprehension and the feature of aspects more of the present invention are provided, comprise following summary of the invention.This general introduction is not extensive overview of the present invention, because of instead of intention is special distinguishes key of the present invention or important key element or describe scope of the present invention.Its unique object is that the form of simplifying provides principles more of the present invention, as prelude in greater detail given below.

Various execution mode of the present invention provides the method for manufacturing silicon substrate without the gasification of carrying out silicon.Therefore, avoided the cost and health and the environmental hazard that relate in the silicon of nine nine grades manufacturing.The solar cell that this substrate can quite even exceed for the manufacture of efficiency and thin film solar cell.

Feature of the present invention has solved the above following major issue that solar cell industry faces:

A) for availability and the cost of " thering is (the solar capable) of solar energy ability " silicon materials of wafer and film

B) for the investment cost of solar cell factory

C) every watt of following solar cell required cost.

D) for the scale of the production technology of large volume

E) reliability of environmental suitability and 25 years

Feature of the present invention makes it possible to obtain the productive solution to the problems referred to above, especially makes an investment in the solar battery structure of the conversion efficiency of body silicon wafer and the benefit of hull cell structure by manufacture.According to aspects of the present invention, by utilizing the silicon wafer of being made by the extremely low metallurgical grade silicon of cost to manufacture thin film solar cell as substrate and on this substrate, manufacture solar cell.According to feature of the present invention, much thin that (for example, 10%) film is manufactured battery by the thin film solar cell of deposition rate routine.Except reducing the cost of substrate and membrane material, the structure of suggestion allows the conversion efficiency of the raising that exceedes conventional thin film solar cell.That is to say, by utilizing metallurgical grade silicon wafer, the manufacture of substrate becomes the less and more environmental protection of harm, also reduces the cost of substrate simultaneously.In addition, utilize metallurgical grade silicon wafer as substrate, and improved conversion efficiency compared with the membrane structure of formation on glass, because described silicon wafer has formed light absorbing medium, instead of the thin i-Si layer of conventional hull cell.

The invention discloses a kind of method of utilizing metallurgical grade silicon to prepare substrate, the method comprises: make metallurgical grade silicon melting in smelting furnace; Make the metallurgical grade silicon after melting be solidified as ingot casting; Ingot casting is cut into slices to obtain multiple wafers; Two surfaces of the each wafer of etching; On the back side of each wafer, deposit aluminium lamination; Depositing hydrogenated silicon nitride layer on the front of each wafer; At high temperature described wafer is annealed; Remove the silicon nitride of hydrogenation and do not disturb described aluminium lamination; And on the front of wafer deposit film structure.In the deposition process of the silicon nitride layer of hydrogenation, in the time that hydrogen enters in substrate, back side aluminium lamination has formed sealing.In annealing process, aluminium lamination has formed the good ohmic contact with described chip back surface, and thus, once form device in the front of this wafer, aluminium lamination just can be used as back side contact layer.

Utilize metallurgical grade silicon to prepare a method for substrate, comprising: obtain the wafer being formed by levels of metal silicon; On described wafer, carry out pre-etching (conditioning etch); Deposition of sacrificial layer on the front of described wafer; Plated metal layer on the back side of described wafer; At high temperature described wafer is annealed; And remove sacrifice layer and do not disturb described metal layer.

Utilize metallurgical grade silicon to prepare a method for substrate used for solar batteries, comprising: obtain the wafer being formed by levels of metal silicon; On described wafer, carry out cutting damage and remove etching (saw damage removal etch); On described wafer, clean etching; Depositing hydrogenated sacrifice layer on the front of described wafer; Under the first high temperature on the back side of described wafer plated metal layer; Under the second high temperature higher than the first high temperature, described wafer is annealed; And remove hydrogenation sacrifice layer and do not disturb described metal layer.

According to a further aspect of the present invention, provide a kind of method of utilizing metallurgical grade silicon to prepare solar cell, the method comprises: the multiple grain wafer that forms metallurgical grade silicon; Make the crystal boundary passivation on the front of each wafer, and collect impurity (getter impurity) from the back side of described wafer; And form solar battery structure on the front of each wafer.Suppress crystal boundary and collect impurity to comprise: the surface of wafer described in etching; Sputtered aluminum layer on the back side of described wafer; On the front of described wafer, deposit Si ₃n ₄; Make described annealing of wafer; And peel off the Si having deposited ₃n ₄layer and do not disturb this aluminium lamination.Before sputtered aluminum layer, can deposit overleaf p-type layer.In addition, at deposition Si ₃n ₄before layer, can also be on front the n-type layer of deposited amorphous.Formation solar cell may further include: deposition intrinsic amorphous silicon layer and deposit n-doped layer in this intrinsic amorphous silicon layer on the front of described wafer.Described intrinsic amorphous silicon layer and n-doped layer can be hydrogenation.

According to a further aspect of the present invention, provide a kind of solar cell, comprising: the metallurgical grade silicon substrate with the back side and texturing front; Be formed at the contact layer of back layer; Be formed at the intrinsic amorphous silicon layer on front; Be formed at the n-type silicon layer on intrinsic amorphous layer; With the ITO being formed on N-shaped layer; And be formed at the front contact layer on ITO.

Brief description of the drawings

According to the detailed description with reference to following accompanying drawing, it is clear that other side of the present invention and feature will become.Should be understood that, the detailed description and the accompanying drawings provide the various nonrestrictive embodiment of the various execution modes of the present invention that are defined by the following claims.

Be attached in this specification and form for example clear embodiments of the present invention of its a part of accompanying drawing, and play the effect of explaining and principle of the present invention being described together with describing.Accompanying drawing intention is with the feature of the execution mode of illustrated mode illustrated example.Accompanying drawing is not that intention is described each feature of actual execution mode or the relative size of the element described, and not drawn on scale.

Fig. 1 is that explanation is according to the flow chart of the technique of one embodiment of the present invention.

Fig. 2 illustrates according to the technique of one embodiment of the present invention.

The technique of Fig. 3 explanation another execution mode according to the present invention.

Fig. 4 illustrates according to the technique of one embodiment of the present invention.

Fig. 5 A illustrates another embodiment of the invention, and Fig. 5 B represents the distortion of present embodiment.

Fig. 6 A illustrates another embodiment of the invention, and Fig. 6 B represents the distortion of present embodiment.

Fig. 7 illustrates another embodiment of the invention.

Fig. 8 illustrates another embodiment of the invention, and it is similar to the execution mode of Fig. 7, except dopant is put upside down.

Fig. 9 A illustrates for the manufacture of being conventionally called SmartSi herein ^tMthe embodiment of technique of substrate ready used for solar batteries (a solar-cell ready substrate).

Fig. 9 B explanation can be used for SmartSi wafer to be converted to the embodiment of the technique of SmartSi PV solar cell.

The complete solar cell that Figure 10 explanation is manufactured according to the embodiment of the present invention.

The execution mode of Figure 11 A and the many knots of 11B explanation SmartSi solar cell.

Figure 12 A and 12B explanation have the execution mode of many knot SmartSi solar cells of diffusion junctions.

Figure 13 A and 13B explanation two sides is clipped in the execution mode of the balanced configuration of the metalluragical silicon substrate between the Si:H film of i-Si/ doping.

Figure 14 A and 14B illustrate according to the alternative metalluragical silicon wafer preparation method of embodiment of the present invention.

Figure 15 explanation utilizes metalluragical silicon wafer to manufacture the alternative method of solar cell according to embodiment of the present invention.

Figure 16 A～16F explanation is carried out texturing and pretreated method according to embodiment of the present invention to substrate surface.

Figure 17 A～17E explanation is carried out texturing and pretreated alternative method to substrate surface according to the embodiment of the present invention.

Embodiment

Embodiments of the present invention are provided for the method for low cost fabrication solar cell, reduce related health and environmental hazard in conventional solar cell manufacture simultaneously.As pointed out on the solar energy website of USDOE: " will be as the semi-conducting material in solar cell, silicon must be purified to 99.9999% purity " (can obtain on http://wwwl.eere.energy.gov/solar/silicon.html).This is commonly called 6N or solar energy level silicon, SoG Si.Contrary with conventional wisdom, the invention provides the method for utilizing the metallurgical grade silicon MG Si of purity 3N～5N to produce substrate and solar cell.Various execution modes disclose benefit in conjunction with silica-based solar cell and thin film based solar cell so that approximately more than 14% battery of conversion efficiency to be provided.

Fig. 1 is that explanation is according to the flow chart of the technique of one embodiment of the present invention.In Fig. 1, this technique starts from step 100, by producing metalluragical silicon particulate material with graphite reduction quartz.The purity level of gained can be 99.9% or 99.999% purity, i.e. the purity of approximately three nine to approximately five nine.It should be noted that quartz easily obtains at low cost.In addition, this technique has been omitted gasification step, thereby has avoided the dangerous process of gasification and production of silane.

At next step in 200, particle fusion in large square or circular mould, for example, is taken advantage of to 1 meter for 1 meter, and made liquid slow solidification become to have the cylinder of large silicon crystal grain.Optionally, by the cylinder remelting of solidifying, then portions is solidified, to impurity is moved on to a cylindrical side.Along continuous straight runs control cooldown rate and temperature gradient in this process, for example, to make impurity move to cylindrical surface and vertically (, lentamente mould be reduced to lower than smelting furnace) to the top of the solid that impurity is concentrated on obtain.In step 200, optionally adulterate this molten silicon to produce containing 1E17～1E18cm with a small amount of boron ^-3the p-Si of boron.In step 300, cutting is solidified cylindrical periphery to remove the layer with a large amount of impurity, and produces square body.In step 400, this square body is cut into ingot casting, for example 16 square body ingot castings.In step 500, with for example diamond or wire saw, each ingot casting being cut into slices is approximately 20 mils, i.e. the Si wafer of 0.020 inch.Can collect waste material reuses in melting.

Fig. 2 illustrates according to the technique of one embodiment of the present invention.This technique starts from by " dirty " silicon, the wafer DSi 200 that the metalluragical silicon of 3～5 nine that for example the technique of the execution mode by Fig. 1 obtains is made.Utilize for example PECVD, on the end face of wafer 210, depositing concentration is 1.0E16 atom/cm ³n-layer.Then on this n-type layer 210, provide SiN layer 220 with plasma chamber.Then utilize the POCl at the temperature higher than 900 DEG C ₃process impurity is extracted molten glass layers 230 from DSi layer 200.This has improved the purity of p-type layer 200, and the knot forming especially before this around.But adopt the etch processes peel ply 230 after for example chemico-mechanical polishing (CMP).This has removed and has contained the layer 230 extracting from the impurity of layer 200.Silver contact 240 is finally set on n-doped layer 220, and aluminium electrode 250 is provided on layer 200.Then make the annealing of total body 700 DEG C of left and right, make silver electrode to n-type layer 210 and make aluminium electrode 250 complete low-resistance ohmic contact to p-type layer 200.

The technique of Fig. 3 explanation another execution mode according to the present invention.This technique starts from step 100, and the thick amorphous silicon layer of 2 μ m distils from contain the crucible of metalluragical silicon.This will carry out lower than at 1000～1200 DEG C of silicon fusing point under the Ar background vacuum pressure in about 10E-6 holder.This step is determined purer active junction layer, because any carbon and metal impurities do not distil at 1200 DEG C.In addition, in argon gas background environment, a small amount of residual oxygen helps to promote distillation by form a small amount of silicon monoxide on crucible surface.In step 200, at O ₂add N ₂or under the environment of Ar, wafer is exposed to containing P gas as POCl ₃or PBr ₃.This step is by Doped n-profile and make B be able to be out-diffusion to the next p-n junction that forms in the silicon layer clean distillation from " dirty " substrate.

But etching or CMP (chemico-mechanical polishing) are carried out to remove the glass of any Doping Phosphorus in the back side of this wafer in step 300.Secondly,, in step 400, plasma is for depositing SiN anti-reflective film in the front of this wafer (n-type).In step 500, form contact, for example, can come for contact boring with laser.In step 600, manufacture conductive electrode, for example, can adopt silk screen or other method to stick with paste to limit electrode at front and back plated metal.Then at 600 DEG C～700 DEG C, sintering wafer contacts to form.Under the contact hole by silk screen, deposition of silver not being had on SiN anti-reflective film through any laser drill of this layer, utilize higher temperature that silver is able to through whole SiN layer.

Fig. 4 illustrates according to the technique of one embodiment of the present invention.This technique is from dirty p-type silicon wafer 400.Then utilize evaporation process on wafer 400, to produce the SiOx layer 410 of evaporation.N-type layer 420 (this can be diffused in this layer 410 and carry out by the Si layer of dopant deposition phosphorus or by other acceptable method part) is provided on SiOx layer 410.Then use layer 430 sealant 410, utilize gettering (gettering) impurity to be drawn to the layer 400 that provides purity to improve to the bottom 440 of wafer 400.Then can before deposition wire, remove this bottom 440.

According to another execution mode, first the dirty silicon wafer of etching to provide texture on its end face.Then at POCl ₃in stove, process this wafer to form the p-n junction of this wafer.Cover the end face of this wafer with the SiN layer of plasma deposition.Then this wafer is exposed to POCl again ₃whole metal impurities are received to (getter) back side, and make this knot sclerosis avoid spilling.Then remove the glass on chip back surface by for example back etched.Then utilize for example laser drilling or contact etch to form contact hole.Then utilize conventional technology to form Metal Contact.If not, the silver that directly forms silk screen on the nitride layer of plasma deposition is stuck with paste, and then annealing at～700 DEG C makes silver be diffused into the layer near the Doping Phosphorus at wafer top, and do not use any contact hole.

Once it should be noted that and form metallurgical Si p-n junction, due to the metal impurities in junction interface, very easily spill.POCl ₃an effect be to form n-layer, impurity is drawn to the near surface that forms knot.Therefore,, in order metal impurities to be moved on to the back side of wafer from positive knot, carry out in this embodiment the 2nd POCl ₃step is protected active front with SiN simultaneously.Can make metal concentrate in the glass of the watery fusion on chip back surface, then remove by chemical etching or CMP.

Replace silicon substrate, people can use by being coated with the stainless steel of distillation Si or the substrate that glass is made, and by being diffused in this substrate and forming p-n junction from centrifugally cast B, P glass.This is different from the amorphous PECVD silicon of deposition for the dull and stereotyped application of thin-film transistor, because the film of distillation does not have any captive hydrogen.Therefore,, in the time of High temperature diffusion step subsequently, they do not decompose.PECVD film lost efficacy in time, may be because the composition relevant with H desorb changes.

Fig. 5 A illustrates another embodiment of the invention.The raw material that is used for the execution mode of Fig. 5 A is by casting, and the purity of Slow cooling manufacture is subsequently approximately three 9 to five 9 i.e. 99.9% to 99.999% low cost polycrystalline metalluragical silicon wafers.Metalluragical silicon is easily by quartz (SiO ₂) manufacture with the chemical reaction of graphite (C) based on smelting furnace, the two is present in mine all over the world.This bi-material is the purer form of sand and coal substantially.Oil accessory substance or organic plant material that graphite can comprise pure C with other replace.Make metallurgical silica flour melting, as required to adding the P of test volume and/or B in melt to produce about 5E17 atom * cm ^-3p-type concentration of dopant.Make melt Slow cooling to produce the cylindrical ingot casting of siliceous poly grains, containing impurity for example Cr, Fe, Ni, Mn and the C of about 10ppm.Regulate cooling procedure to make Impurity Distribution in the sedimentary cluster of what is called.Their electroactive being less than of trend are uniformly distributed atom, and the latter typically occupies the electroactive site replacing on silicon crystal lattice.The impurity replacing plays for the trap of electron-hole recombinations or the effect at center, and this composite quilt is thought and reduced the photovoltaic conversion efficiency of solar cell by reducing the diffusion length of charge carrier in light absorbing zone.The light having functional relation by well-known test and light wavelength is converted to the Physical of the quantum efficiency of electric charge carrier can estimate diffusion length.By the material of casting, ingot casting is processed into less cylinder, is sawn into wafer, is etched with removal surface damage, then operates in polishing on one or both sides according to the industry of standard.The metallurgical grade wafer that this will obtain is as the substrate of producing solar cell.Do not resemble conventional polysilicon solar cell silicon substrate used, this execution mode does not need to use conventionally by gas phase SiH _xcl _yseven 9 or more highly purified polysilicon that compound reduction is manufactured.

Substrate 500 cleans through pre-deposition, typically relates to 100: 1HF removes any natural oxide, uses NH ₄oH/H ₂o ₂remove organic pollution, then remove any metal impurities with HCl.This step can also comprise the cutting damage removal etching described in any position of this paper.Then in the situation that there is no impurity gas, utilize at SiH ₄and H ₂the plasma of middle generation in the PECVD of standard equipment, apply as thin as a wafer ( ), typically lower than the unadulterated amorphous Si:H of intrinsic layer 505.Next, form the active parts of knot by the a-Si:H layer 510 of deposition n-doping, this can carry out easily in same apparatus, but utilizes containing SiH ₄and H ₂and PH ₃plasma.This is transparent for example ZnO of conductive oxide 520 subsequently ₂if, ITO or InSnO and need to be by SiO _xn _ythe pantostrat of the anti-reflective film 515 forming.These form top electrode, daylight can be transferred to silicon absorbed layer body by this electrode.For extra charge collection efficiency, can in this transparent conductive oxide layer 520, form and typically stick with paste by silver a series of electrodes that form.For the low resistance contact at the battery structure back side, apply Al layer 525 containing the paste of Al in the bottom surface of wafer by PVD process deposits or silk screen printing, then sintering is to form low resistance contact.

So the solar cell obtaining comprises at least following new feature.By forming p-n junction by cost Billy with the n-layer of deposited amorphous Si:H film on the conventional silicon wafer light absorption wafer that the p-type polycrystalline metallurgical grade silicon wafer of approximately ten times is made less of solar energy or the manufacture of semiconductor grade polysilicon.The thick metallurgical p-type polysilicon light absorbing zone of 250～500 μ m of being manufactured containing the metallurgical silica flour of B dopant by casting replaces the solar-grade polysilicon that adopts more expensive.Between the metallurgical substrate of p-type and n-Si:H film, insert optional intrinsic (undoped) Si:H film intermediate layer so that because the impurity in polycrystalline character and material typically has the surface passivation of the metalluragical silicon of fracture (suspension) key, thus improvement photovoltaic conversion efficiency.Can omit ARC layer 515 for cost-saving, replace by the surface of etching metallurgical grade silicon in KOH and make it coarse to expose (111) face in the crystal grain that (100) are orientated substantially.This roughening makes light reflection minimized, so that ARC layer can be unnecessary.

On the other hand, Fig. 5 B has illustrated that transparent conductive layer is also as the embodiment of antireflection (ARC) layer.Except having removed the step that forms ARC layer, with the solar cell of the mode shop drawings 5B similar to Fig. 5 A.The substitute is, tco layer is made and made it can also be as the thickness of ARC layer.For example, in one embodiment, ITO is sputtered to thickness, to make ITO form transparent conductive layer and antireflecting coating.The frequency band reflection of the thickness that can regulate ITO to prevent from wanting.What Fig. 5 B also showed is the back layer of amorphous p-type, and it utilized PECVD to deposit before aluminium lamination.

Fig. 6 A illustrates another embodiment of the invention.The execution mode of Fig. 6 A is similar to Fig. 5, except doping is put upside down.That is to say, absorbed layer 600 is fabricated to n-type metalluragical silicon.The amorphous layer 610 of deposition has reversed polarity, i.e. the p-type for tying.Fig. 6 B has simulated the structure of Fig. 5 B, except utilizing n-type wafer that doping is put upside down.

Fig. 7 illustrates another embodiment of the invention.The execution mode of Fig. 7 is similar to Fig. 5.But, in the execution mode of Fig. 7, before the aluminium lamination 725 of manufacturing back side contact, manufacture optional by a-i Si:H film 730 structure that a-n Si:H film 735 forms subsequently, to utilize heterojunction to improve the conversion efficiency higher than absorptive substrate, this heterojunction has the intrinsic passivation layer structure of the Si-H of intrinsic as thin as a wafer layer containing deposition, succeeded by active Si-H thin layer in the electricity of reversed polarity.In this respect, for the execution mode described in Fig. 5～8, the manufacturing sequence with parenthesized letter representation for the layer suggestion of each explanation.Fig. 8 illustrates another embodiment of the invention, and it is similar to the execution mode of Fig. 7, except dopant is put upside down.That is to say, substrate is designated as n-type metallurgical grade silicon, and knot layer 810 is p-types, and layer 835 is n-types.

As can be understood, the execution mode of Fig. 5～8 ties to provide solar cell by build film on metallurgical grade silicon substrate.Due to the performance of metalluragical silicon, compared with having the conventional hull cell of absorbed layer as thin as a wafer, this has the good advantage of light absorption.Therefore, improved conversion efficiency.On the other hand, use metallurgical silicon chip that the cost lower than conventional solar energy or semiconductor grade silicon wafer is provided.In addition, as described herein by using metallurgical grade silicon wafer, reduce health and environmental hazard.

Being intended that of execution mode that relates to Fig. 5～8 distinguished three functions that contact with PV technique, first this technique absorb light to produce electron hole pair in silicon, then by utilizing the band gap of p-n junction to produce minority carrier (electronics) stream, light is converted to electric current.Conventionally,, in the polycrystalline or monocrystalline silicon of p-n junction structure with diffusion, two processes occur simultaneously.In the time of the monocrystalline silicon of the polysilicon from conventional to Czochralsky monocrystalline silicon to zone melting, minority carrierdiffusion length can change to 300 μ m to 100 μ m from 50 μ m.Corresponding PV conversion efficiency is approximately 18%, 22% and 25%.At the other end, it is absorbed layer that the thin film solar cell of deposited amorphous unijunction relies on the middle aSi:H layer that typically approximately 1 μ m is thick.Diffusion length is arrived approximately 1 μ m by the thickness limits of thin layer.Corresponding PV conversion efficiency is reduced to approximately 6～10%.In this execution mode of the present invention, minority carrierdiffusion length is not subject to the restriction of film, but is decided by the characteristic of metalluragical silicon substrate.

Embodiment 1

By the silicon grain of two nine of induction fusings in the graphite crucible of about 1.5m × 1.5m, then become the cylindrical metallurgical grade silicon of producing three nine through 24 hours Slow coolings.Remove the surface crust of rich carbon, and cylinder is pulverized as crystal grain or particle.The material obtaining contains B and P, but normally has the p-type of the resistivity within the scope of 0.1～1ohmcm.Then the material obtaining is cast to former of the metallurgical grade silicon (bole) of about 0.5m × 1m × 1m, be accompanied by and control cooling and dopant adjusting.By described former block ingot casting that cuts into 16 square sectionals, a side is less times greater than 5 ".Smooth periphery, the then thick wafer of sawing 500 μ m from ingot casting.Face of mechanical polishing, two faces of slight etching are to expose the large grainiess of polygon on chip back surface.This produces approximately 500 metallurgical grade silicon wafers of four nine and five nine purity.Utilize 4 point probes to measure wafer is divided into two groups, main group has the resistivity of 0.3～0.5ohmcm, and remaining is at～1ohmcm.The SIMS composition distributional class of 4N and 5N material seemingly, has IE14 atom cm ^-3transition metal impurity concentration.Metal impurities those relevant with metalluragical silicon typically, i.e. Fe, Cr, Mn, Co, Ni, Cu.In addition, there is IE15 atom cm ^-3concentration of carbon.

With the sample manufacture solar cell of wafer.Containing suitable doping gas PH ₃and B ₂h ₆siH ₄, H ₂in utilize rf plasma, with PECVD (plasma reinforced chemical vapour deposition) equipment deposition i type a-Si:H film, p-type a-Si:H and N-shaped a-Si:H film.Adopt PVD (plasma gas-phase deposit) sputtering equipment to deposit approximately in _xsn _yo _z, with the transparent conductive oxide that acts on top electrode and hearth electrode.Adopt silicon tableland (silicon mesas) that etching machines etching approximately 10 μ m are dark to produce and the diode of wafer remainder isolation.Utilize this technique, since 0.1 Ω cm p-type (100) metallurgical grade silicon wafer, produce the single heterojunction with the intrinsic passivation layer structure contacting containing the p+ back of the body of diffusion, and measure the diode I-V of this knot and the quantum efficiency through this spectral region.The curve that utilizes 1/QE contrast λ wavelength, slope provides diffusion length L by μ m.Length L and I _dsatit is the predictive factor of well-known PV conversion efficiency.This structure provides the I of 400mA _dsatwith the length L of 80 μ m, corresponding to approximately 20% PV conversion efficiency.The structure forming on 0.4 Ω cmp-type metallurgical grade silicon wafer is also worked finely, has minority carrier (electronics) the diffusion length L of 7 μ m _e, corresponding to 12～13% PV conversion efficiency, putative structure has the series resistance of good control.The structure forming on 1.0 Ω cm p-type metallurgical grade silicon wafers is also worked finely, has minority carrier (electronics) the diffusion length L of 8 μ m _e, corresponding to 14% PV conversion efficiency, putative structure has the series resistance of good control.

Embodiment 2

By in front being " device " side depositing nano level Si:H film stack the a-Si:H film of " contact " side sedimentary facies contra-doping overleaf, on metallurgical grade substrate, forming the single heterojunction that contains intrinsic passivation layer device architecture cheaply.Metallurgical grade substrate needn't be thinned to 250 μ m from 500 μ m especially by substrate as crystallization Si substrate is done, has exempted loss.Thicker wafer provides more firm operation in automatic assembly line.This material has also been avoided gasification based on polysilicon, has been solidified, cost, cycle and the complexity of melting and czochralski process, because by just being produced this active device by the thin Si:H film outside the metallurgical grade real estate of nanoscale intrinsic a-Si:H film passivation.

Metallurgical grade substrate can form by for example 6 inches, 8 inches, 12 inches of the sizes of standard, can in the semiconductor PECVD of standard process equipment, process.On the contrary, in large area (conventionally, 4 × 6ft or 6 × 7ft) the solar cell of the conventional based thin film of generation on glass, this needs the special large chamber of internal capacity, causes being difficult to be extracted into low pressure and causes being used to form the active gases waste of thin layer.Therefore, these PECVD reactors are bought expensive and are turned round expensive because running stores (, discarded active gases) cost is high.The high internal capacity of these special chambers also causes depreciation difficulty and cost.Otherwise forming film on standard-sized wafer can carry out in the little standard reaction device of internal capacity, so that the problem minimum of running and depreciation.Due to the order of magnitude of minority carrierdiffusion length longer in metalluragical silicon substrate, the structure of thin film device obtaining on metalluragical silicon substrate has the PV efficiency that is greater than the conventional about twice of thin film solar cell.

Embodiment 3

Fig. 9 A explanation is called SmartSi conventionally herein ^tMan embodiment of the technique for the manufacture of ready substrate used for solar batteries.In step 900, in the electrolysis tank of graphitiferous electrode, by the melting of metallurgical grade quartz reduction, then allow it cooling and solidify to provide the metalluragical silicon ingot casting of approximately two nine.Ingot casting is broken into particle, in chemicals, processes to leach surface impurity, then cast ingot casting.Then peel off the shell of ingot casting and be broken into the metallurgical silico briquette of three to five nine.The piece obtaining is according to their resistivity classification.

In step 915, the MG silico briquette of classification is cast.Make melt solidifying become former, in step 920, processing, is cut into ingot casting, and is sliced into for example wafer of 350 micron thick.In addition, also each wafer is etched with and removes also cleaning and the surface for the preparation of the wafer of further processing of cutting damage.In addition, in this step, can also carry out texturing etching (texture etch) so that the positive texturing of each wafer.In step 925, form the front of intrinsic amorphous silicon thin layer i-a-Si:H with passivation MG-Si substrate with PECVD chamber.In step 930, on passivation layer, form n-type floor n-a-Si:H with PECVD chamber.Now, produced " SmartSi ^tM" or wafer 935, makes it possible to anywhere in fact form PV solar cell industry by simple and mechanical and few technological know-how of little investment, small amount in the world.That is to say, as can be understood, for SmartSi wafer is converted to solar cell needed all be to manufacture the contact of front and back.This adopts existing silk screen printing or printing technology easily to carry out.In addition, as shown in mark, can carry out another step 930 of PECVD ' with the back side at substrate form p-type layer 935 ', to improve the contact to conductive layer subsequently.

Fig. 9 B explanation can be used for SmartSi wafer to be converted to an embodiment of the technique of SmartSi PV solar cell.As mentioned above, needed is to contact with formation in front at the back side of SmartSi substrate.As for front, a kind of method is the metal grill that forms conduction.Usual way is the grid that design has the many thin conductive contact that spreads to the each part of battery surface.The contact of grid must be enough wide with good conductive (having low resistance), but want enough narrow in order to avoid block a large amount of incident lights.This grid keeps low resistance loss, only covers approximately 3% to 5% of battery surface simultaneously.End face grid can be made up of for example aluminium, silver or molybdenum, by battery through mask plated metal steam, smear them by reticulated printing method on battery, or with providing the highest performance but the highest photoetching process of cost.

What alternative metal grill contacted is transparent conductive oxide (TCO) layer, for example tin oxide (SnO ₂) or be commonly called the tin indium oxide of ITO.The advantage of TCO is that they are almost sightless to incident light, and they form the good bridge joint from semi-conducting material to external circuit.Execution mode shown in Fig. 9 B utilizes TCO as the contact to battery front side.In step 940, utilize PVD technique to form tco layer.In step 945, adopt silk screen, printing etc. for example on front, to utilize metal paste that trace describes by front contact metallization.In step 950, adopt for example metal paste (for example, silver is stuck with paste) of describing in the utilizations overleaf such as silk screen, printing or make back side contact metallization to form collector electrode by sputtered aluminum on the back side of substrate or other metal.In the time using paste by front contact metallization, as shown in step 955, be desirable in order to form good this wafer of ohmic contact sintering.Then according to conversion efficiency, wafer is classified, to produce SmartSi PV battery 960.

In above-mentioned all execution modes, before forming any layer, can be by for example making its one or two face by texturing at alkaline solution as potassium hydroxide solution makes the etching of MG Si substrate.Then can rinse this substrate, and make it dry by for example heating this substrate.In addition, can reduce the carbon amount on substrate surface with the plasma discharge of hydrogen.Can in PECVD chamber, adopt and hydrogen (H ₂) mix silane gas (SiH ₄) form intrinsic amorphous silicon thin layer.Can in PECVD chamber, adopt silane, hydrogen and phosphine gas (PH ₃) form n-type amorphous silicon thin layer.Can in PECVD chamber, adopt silane, hydrogen and Boroethane gas (B ₂h ₆) form p-type amorphous silicon thin layer.

The complete solar cell that Figure 10 explanation is manufactured according to the embodiment of the present invention.On metallurgical grade silicon substrate 1000, form solar cell, this substrate is the p-type of doping in the present embodiment.Then form intrinsic amorphous silicon layer 1005 at end face, form subsequently n-type amorphous silicon layer 1010.On n-type layer, form tco layer 1020, and for example silver of formation contact contacts 1025 to form good ohmic contact on TCO.Can form back of the body contact with for example aluminium.Now battery completes and is available; But, in order to make it avoid element impact, carry out following further processing.Front is subject to the protection of optional resin film layer 1015, and for example ethene-vinyl acetate copolymer is followed by glass 1045.The back side also can be protected with resin molding 1035, subsequently glass or other protective layer 1040.

As shown in Fig. 9 A and 9B, can manufacture SmartSi wafer with execution mode discussed above, wafer further can be processed to manufacture SmartSi solar cell.According to another aspect of the present invention, in order to improve photovoltaic conversion efficiency, can further process SmartSi solar cell and manufacture many knot SmartSi solar cells with multiple band gap.An execution mode of the many knots of explanation SmartSi solar cell in Figure 11 A.In Figure 11 A, metallurgical grade silicon substrate 1100 is p-types of doping.The end face of this p-type substrate is by 1105 passivation of intrinsic amorphous silicon thin layer, and this amorphous silicon has dispersion wherein and occupies the hydrogen atom of silicon dangling bonds.This is called as silane sometimes.As shown in above-mentioned SmartSi solar cell execution mode, on intrinsic layer 1105, form the thin layer 1110 of n-type amorphous silane, thereby form a p-i-n knot.Originally the n-type of seeking peace layer 1105 and 1110 than the thin layer relative thin of typical conventional thin film solar cell many, in the present embodiment, the first film structure needn't play absorber of light, but absorbs light in metalluragical silicon substrate.

In order to improve the conversion efficiency of SmartSi solar cell, on SmartSi solar cell, form conventional thin film solar cell p-i-n structure now.First, on SmartSi solar cell, form film p-type amorphous layer of hydrogenated 1120.Then on p-type layer 1120, form film intrinsic amorphous layer of hydrogenated 1125, and on this intrinsic layer 1125, form film n-type amorphous layer of hydrogenated 1130.Intrinsic layer 1125 plays another absorber of light and produces electron hole pair, thereby light is converted to electric energy.In order to collect electric energy, on n-type layer 1130, form top transparency electrode ITO 1135, then on ITO 1135, form Metal Contact 1140.Here Metal Contact 1140 is made from silver, for example, adopt silver to stick with paste, and then this structure of sintering is to form good ohmic contact.In addition, form metal electrode 1145 in the bottom of substrate 1100.Here contacting 1145 is formed from aluminium.Figure 11 B illustrates similar multijunction structure, except by the polarity reversal of layer.

Figure 12 A and 12B explanation have the execution mode of many knot SmartSi solar cells of diffusion junctions.The execution mode of Figure 12 A and 12B is substantially the same, except by the polarity reversal of layer.Therefore, only the execution mode of a kind of Figure 12 of the being A in them is described.In Figure 12 A, manufacture metalluragical silicon substrate 1200 according to execution mode as above, and it is the n-type of doping.Then, make the top layer of substrate spread to form p-type diffusion layer 1260.The transition region that this forms p-n junction and solar cell is provided in metalluragical silicon substrate, is similar to the silica-based solar cell of standard.Then on the p-type layer of diffusion, form the thin passivation layer 1205 of intrinsic amorphous silane.On this intrinsic layer 1205, form n-type amorphous layer of hydrogenated 1215, consequently layer 1215,1205 and 1260 forms the p-i-n knot with the band gap that is different from substrate 1200 interior p-n junctions, therefore with different frequency absorption light.Then on layer 1215, form conventional film p-i-n knot by forming p-type amorphous layer of hydrogenated 1220, intrinsic amorphous layer of hydrogenated 1225 and n-type amorphous layer of hydrogenated 1230.In this structure, when the used time of doing of 1225 absorber of light of intrinsic layer, it has the thickness far above intrinsic layer 1205.In addition, this film p-i-n structure has the band gap different from structure under it, therefore with different frequency absorption light.Therefore,, by carefully selecting the thickness of layer, people can " adjust " this structure and absorb light with the frequency range wide.

Figure 13 A and 13B explanation two sides is clipped in the execution mode of the balanced configuration of the metalluragical silicon substrate between the Si:H film of intrinsic Si/ doping.Figure 13 A and 13B are enantiomers each other, except by the polarity reversal of layer.Therefore key-drawing 13A only.In Figure 13 A, p-type metalluragical silicon substrate 700 has as the upper intrinsic layer 705 of passivation layer instead of absorber and lower intrinsic layer 730.Then on intrinsic layer 705, form the thin layer 710 of n-type amorphous silane, and on intrinsic layer 730, form another n-type layer 735.Then as described with respect to other execution mode, form contact 720 and 725.

Figure 14 A illustrates the preparation of alternative according to the embodiment of the present invention metalluragical silicon wafer.At step 1400A, the melting in mould by metalluragical silicon particle or powder, and make it to be frozen into former.Described former can be foursquare, is determined as for example one square metre, and thickness is approximately 25 centimetres.In this technique, can control in the horizontal direction cooling rate and temperature gradient, to make impurity move to the outer surface of former.In addition, can also in heater, mould vertically be reduced, to make impurity concentrate on the end face of former.Optionally, by the former remelting of solidifying, then divide along cross section and solidify, to impurity is moved on to a cylindrical side.At step 1405A, the former sawing of solidifying become to several ingot castings (for example 16 ingot castings) with desirable cylindrical shape (square or dead square cross section).At step 1410A, each ingot casting sawing is become to wafer.At step 1415A, as required each wafer is carried out to polishing and cleaning.At step 1420A, utilize for example PVD technique, the back side by aluminium layer deposition at each wafer.Can be at high temperature, for example 200 DEG C～400 DEG C, by sputtered aluminum to wafer.At step 1425A, utilize for example pecvd process, H:SiN is deposited upon to the front of each wafer.This step can complete at for example 200 DEG C～400 DEG C of high temperature.At step 1430A, at for example 400 DEG C～700 DEG C, wafer is annealed.In this step, a large amount of hydrogen is entered in wafer, and aluminium lamination guarantees hydrogen to be captured in wafer.At step 1435A, utilize for example wet etching to remove H:SiN layer, and in step 1440, also utilize for example wet etching to remove Al layer.

Figure 14 B illustrates the preparation of alternative metalluragical silicon wafer according to the embodiment of the present invention.At step 1400B, the melting in mould by metalluragical silicon particle or powder, and make it to be frozen into former.Described former can be foursquare, is determined as for example one square metre, and thickness is approximately 25 centimetres.In this technique, can control in the horizontal direction cooling rate and temperature gradient, to make impurity move to the outer surface of former.In addition, can also in heater, mould vertically be reduced, so that melt is upwards solidified by bottom, and make thus impurity concentrate on the end face of former., impurity preferentially concentrates on melt instead of solid.So in the time mould being reduced and bottom starts to solidify, impurity tends to stay in liquid, makes thus the bottom of former have less impurity.In addition, boron and former solidifies faster than phosphorus, and this makes the bottom of former be tending towards p-type, and its top is N-shaped.Optionally, by the former remelting of solidifying, then portions is solidified, to impurity is moved on to a cylindrical side.At step 1405B, the former sawing of solidifying become to the ingot casting (for example 16 ingot castings) in several tools cylindrical shape likely (square or dead square cross section).In step 1410B, each ingot casting sawing is become to wafer.

In step 1415B, on each wafer, carry out cutting damage and remove etching.Can utilize such as KOH, HNA etc. to carry out cutting damage and remove etching.For example, according to a kind of method, utilize HNA or KOH to remove 15～30 microns from each side of wafer.Remove technique for HNA cutting damage, can adopt weight ratio is the HF of 1.5: 14.4: 1.9: HNO ₃: acetate mixture.Remove for KOH cutting damage, can adopt 30% the KOH mixture of approximately 60 DEG C～90 DEG C.Can also adopt the cleaning step of semi-conductor industry, for example RC-1, SPM, Piranha, rare HF and various combination thereof, clean wafers is with from surface removal metal and organic material.Any be deposited upon wafer before, adopt Marangoni DI rinse or other dry process.According to a specific embodiment, first each wafer is cleaned and is removed organic material by SPM, and SPM is made up of the mixture at approximately 80 DEG C～100 DEG C of sulfuric acid and peroxide.Then, adopt 30% the KOH mixture of approximately 60 DEG C～90 DEG C to carry out cutting damage removal.Then, in HF and HCl, remove oxide and metal.In rare HF mixture (wherein, rare HF mixture refers to approximately 1～4% HF solution), carry out last hydrophobic etching.After this step, it is Marangoni dry method step.

According to another embodiment, first wafer is cleaned and is removed organic material by SPM, and SPM is made up of the mixture at approximately 80 DEG C～100 DEG C of sulfuric acid and peroxide.Then, adopt 30% the KOH mixture of approximately 60 DEG C～90 DEG C to carry out cutting damage removal.Then, carry out the standard RCA-1 (NH of approximately 10 minutes ₄h/H ₂o ₂/ H ₂o).Afterwards, be in rare HF and subsequently at RCA-2 (HCl/H ₂o ₂/ H ₂o) oxide etching of approximately 10 minutes in.Then, in HF and HCl, remove oxide and metal.In rare HF mixture, carry out last hydrophobic etching.After this step, it is Marangoni dry method step.

At step 1420B, for example evaporation of utilization or PVD technique is the back side at each wafer by aluminium layer deposition.In one embodiment, titanium lamina is PVD, and it was splashed to the back side of wafer before PVD is splashed to aluminium lamination.Titanium layer contributes to aluminium to adhere to the back side of wafer.According to another execution mode, before sputtered titanium or aluminium, utilize for example PECVD for example, to deposit to the back side with the amorphous layer of described wafer phase homotype (, if wafer is p-type, being, p-type amorphous layer).Can be at the temperature lower than approximately 350 DEG C for example 200 DEG C～350 DEG C, deposition p-type amorphous silicon.In one embodiment, for p-type wafer, the structure obtaining is titanium layer on p-type amorphous layer, the p-type layer on the back side and the aluminium lamination on titanium layer.

At step 1425B, form sacrifice layer in the front of wafer.According to an embodiment, sacrifice layer comprises the H:SiN layer that utilizes pecvd process deposition.According to another embodiment, by depositing approximately at front wafer surface amorphous n+ layer and be deposited on the pact on positive n+ layer h:SiN layer, form sacrifice layer.According to an embodiment, when deposition of sacrificial layer, wafer is heated to approximately 200 DEG C～400 DEG C.The order that note that step 1420B and 1425B can be put upside down.

At step 1430B, at for example 400 DEG C～800 DEG C by annealing of wafer approximately 15 minutes to 1 hour.In this step, a large amount of hydrogen enter wafer, and aluminium lamination has guaranteed hydrogen to be captured in wafer.In addition, suppose that some impurity transfer to aluminium lamination by chip back surface, part is received in wafer thus.At step 1435B, for example utilize plasma etching to remove for example n+ layer of sacrifice layer and H:SiN layer and do not disturb back layer.Although original position plasma and long distance plasma all can adopt, in one embodiment, adopt long distance plasma so that " soft " etching that has seldom or there is no example bombardment to be provided.At step 1443B, on the front of wafer, form solar device (i.e. knot).Use the method, in annealing/hydrogenation process, the metal layer at the back side is used for covering wafer.In annealing process, it also packs up wafer for part.In addition, because annealing completes at relatively high temperature, improved with the metallization obtaining at the back side and contacted, obtained lower series resistance.So in this embodiment, aluminium is not removed, but be retained on wafer as the last back side contact of solar cell.

Figure 15 explanation utilizes the metalluragical silicon wafer of embodiments of the present invention alternatively to manufacture solar cell.In step 1500, adopt wet equipment technique to clean metalluragical silicon wafer, the wafer that for example adopts the method shown in Figure 14 to obtain.In optional step 1505, the end face of wafer is carried out to texturing.Can adopt and for example cause, in crystal boundary or the specific crystal orientation (direction that atomic density is lower, for example the etching of (100) face is faster than (111) or (211)) the technique of preferential attack, complete texturing by wet type or dry-etching.Correspondingly, have facet crystal grain, its surface is mainly (111) and depression crystal boundary.This result is lower surface reflectivity, causes more incident light to be absorbed and in metalluragical silicon, produces electron-hole pair.This etching repeatedly that can be then each oxidation step native oxide afterwards by front oxidation repeatedly completes.This technique can cause preferential attack at crystal boundary, makes surface-texturing.The texturing on surface contributes to internal light reflection to strengthen the absorptivity of solar cell.In order to improve the coverage of next sedimentary deposit and to avoid piercing through lower one deck, after optional texturing step, can be soft etching, to remove the sharp edges being caused by texturing.In step 1515, for example utilize pecvd process at front deposition intrinsic silicon layer.If needed, can carry out preprocessing process in step 1510, to remove any native oxide before deposition i-layer.In step 1520, adopt for example pecvd process that n-is deposited upon on i-layer.In step 1525, for example adopt PVD technique by such as ITO of tco layer) be deposited on n-layer.In step 1530, for example adopt contact layer after PVD process deposits.In step 1535, adopt for example typography to form on tco layer before contact layer.

Figure 16 A～16F explanation is carried out texturing and pretreated method to substrate surface according to the embodiment of the present invention.Figure 16 A～16E is the cross section of the amplifier section of substrate, and it is illustrated in the crystal grain of substrate top surface, and Figure 16 F has been the vertical view of texturing and preliminary treatment end face afterwards.The cross section of substrate top surface before Figure 16 A explanation texturing step.This can be after the step 1440 of for example Figure 14.Then, adopt for example wet etch step to make substrate texturing.Technique below can be used as and adopts wet etching to carry out textured example: substrate is immersed to HF+ (nitric acid) HNO ₃solution; Rinse substrate; Substrate is immersed to KOH or NaOH solution; Rinse substrate; Substrate is immersed to HF+HCl solution; Rinse substrate; Dry substrate.Through this wet processing, it is more coarse that end face becomes, and it has more sharp-pointed peak and darker paddy, and this part is the preferential attack due to crystal boundary.This state describes in the cross section of Figure 16 B.Then, substrate can pass through photoetch processing, and for example dry ecthing, to remove surperficial spike.The results are shown in Figure 16 C.Then, deposit from the teeth outwards SiO ₂or the thin layer of Si.As shown in Figure 16 D, deep valley naturally can be by preferential deposition, and this makes deep valley by SiO ₂institute covers.Then, substrate is through another etching process, to remove the SiO of deposition ₂or Si.But as shown in Figure 16 E, the SiO of deposition ₂or Si is retained in crystal grain boundary.The vertical view of Figure 16 F has shown this state.Most of crystal grain of SG substrate have 211 orientations.So, adopt above-mentioned technique substantially to eliminate crystal boundary, obtain substantial 2-dimension " discontinuous " crystal, described crystal forms by having the crystal grain of same orientation in fact, and the defect of crystal boundary is by SiO residual after etch processes ₂layer institute " covers " or suppresses.

Figure 17 A～17E explanation is carried out texturing and pretreated alternative method to substrate surface according to the embodiment of the present invention.The method contributes to the impact of the defect of the crystal grain boundary of offsetting multiple grain substrate.In the time using metallurgical grade silicon for example, to use substrate as device (solar cell or LED), this technique is effective especially.

Figure 17 A～17D is the cross section of the amplifier section of substrate, and it is illustrated in the crystal grain of substrate top surface, and Figure 17 E has been the vertical view of texturing and preliminary treatment end face afterwards.The cross section of substrate top surface before Figure 17 A explanation texturing step.This can be after the step 1440 of for example Figure 14.Then, adopt for example wet etch step to make substrate texturing.Technique below can be used as and adopts wet etching to carry out textured example: substrate is immersed to HF+ (nitric acid) HNO ₃solution; Rinse substrate; Substrate is immersed to KOH or NaOH solution; Rinse substrate; Substrate is immersed to HF+HCl solution; Rinse substrate; Dry substrate.Through this wet processing, it is more coarse that end face becomes, and it has more sharp-pointed peak and darker paddy, and this part is the preferential attack due to crystal boundary.This state describes in the cross section of Figure 17 B.Then, deposit from the teeth outwards SiO ₂or the thin layer of Si.As shown in Figure 17 C, deep valley naturally can be by preferential deposition, and this makes deep valley by SiO ₂or Si covers.Then, substrate is through etching process, to remove the SiO of deposition ₂or Si.This etch processes, for example dry ecthing, has removed the sedimentary deposit on most of surfaces, and has removed some spikes of surface microstructure.But as shown in Figure 17 D, the SiO of deposition ₂or Si is retained in the deep valley of crystal grain boundary.The vertical view of Figure 17 E has shown this state.Most of crystal grain of SG substrate have (211) orientation.So, adopt above-mentioned technique substantially to eliminate crystal boundary, obtain substantial 2-dimension " discontinuous " crystal, described crystal forms by having the crystal grain of same orientation in fact, and the defect of crystal boundary is by SiO residual after etch processes ₂layer institute " covers " or suppresses.

Should understand technique as herein described is not relevant to any device inherently with technology, and can implement by the combination of any applicable assembly.In addition, can adopt various types of common apparatus according to instruction as herein described.Can also prove that it is favourable that structure is carried out the special purpose device of method step as herein described.Describe the present invention with respect to specific embodiment, be intended that illustrative and nonrestrictive from all aspects.The many various combinations that it will be appreciated by those skilled in the art that hardware, software and firmware will be suitable for implementing the present invention.

Describe the present invention with respect to special embodiment, be intended that illustrative and nonrestrictive from all aspects.The many various combinations that it will be appreciated by those skilled in the art that hardware, software and firmware will be suitable for implementing the present invention.In addition, for those skilled in the art, considered explanation of the present invention disclosed herein and enforcement, other enforcement of the present invention will be apparent.It is exemplary that intention is only used as specification and embodiment, shows true scope of the present invention and essence by following claim.

Claims

1. utilize metallurgical grade silicon to prepare a method for substrate, comprising:

Obtain the wafer being formed by metallurgical grade silicon;

On described wafer, carry out pre-etching;

Deposition of sacrificial layer on the front of described wafer;

Plated metal layer on the back side of described wafer;

At high temperature wafer is annealed; And

Remove sacrifice layer and do not disturb described metal layer,

Wherein, deposition of sacrificial layer is included in the hydride layer of deposited silicon nitride on the front of wafer, deposition of sacrificial layer further comprises: before deposited silicon nitride layer by n-type amorphous silicon layer Direct precipitation on the front of described wafer, and by described silicon nitride layer Direct precipitation on described n-type amorphous silicon layer, be p-type by wafer doping, and plated metal layer comprises overleaf: by p-type amorphous silicon layer Direct precipitation on the back side of described wafer, titanium layer is deposited on described p-type amorphous silicon and by aluminium layer deposition on described titanium layer.

2. according to the process of claim 1 wherein, carry out pre-etching and comprise from every side of wafer and remove 15～30 microns.

3. according to the method for claim 2, wherein, carry out pre-etching and be included in HNA or KOH solution wafer described in etching.

4. according to the method for claim 3, wherein, carry out pre-etching and further comprise and remove organic material etching and remove metal etch.

5. according to the method for claim 3, wherein, carry out pre-etching and further comprise: in the solution of sulfuric acid and peroxide, carry out etching, in the solution of HF and HCl, carry out etching and carry out etching in rare HF solution.

6. according to the method for claim 5, wherein, deposition of sacrificial layer further comprises: before deposited silicon nitride layer by n-type amorphous silicon layer Direct precipitation on the front of described wafer, and by silicon nitride layer Direct precipitation on described n-type amorphous silicon layer.

7. according to the method for claim 6, wherein, remove sacrifice layer and comprise described in plasma dry positive to remove described sacrifice layer completely.

8. according to the method for claim 7, wherein, plasma dry comprises utilizes remote plasma source to carry out described etching.

9. method according to Claim 8, wherein, further comprises n-type amorphous silicon layer is deposited on the front of described wafer.

10. according to the method for claim 9, further comprise: before deposition n-type amorphous silicon layer by intrinsic amorphous silicon layer Direct precipitation on the front at described wafer, and by n-type amorphous silicon layer Direct precipitation in described intrinsic amorphous silicon layer.

11. according to the method for claim 10, is further included in Direct precipitation ITO on n-type amorphous silicon layer.

12. according to the method for claim 11, is further included in the upper contact grid that directly form of ITO.

13. 1 kinds of methods of utilizing metallurgical grade silicon to prepare substrate used for solar batteries, it comprises:

Obtain the wafer being formed by metallurgical grade silicon;

On described wafer, remove cutting damage etching;

On described wafer, clean etching;

Depositing hydrogenated sacrifice layer on the front of described wafer;

Under the first high temperature on the back side of described wafer plated metal layer;

Under the second high temperature higher than the first high temperature, described wafer is annealed; And

Remove the sacrifice layer of described hydrogenation and do not disturb described metal layer,

Wherein, be p-type by wafer doping, and go up overleaf plated metal layer and comprise: by p-type amorphous silicon layer Direct precipitation on the back side of described wafer, titanium layer is deposited on described p-type amorphous silicon and under the first high temperature aluminium layer deposition on described titanium layer.

14. according to the method for claim 13, and wherein, described the first high temperature is selected from 200 DEG C～400 DEG C, and the second high temperature is selected from 400 DEG C～700 DEG C.

15. according to the method for claim 14, and wherein, depositing hydrogenated sacrifice layer is included in depositing hydrogenated silicon nitride layer at the temperature that is selected from 200 DEG C～400 DEG C.

16. according to the method for claim 13, wherein, deposits p-type amorphous silicon at the temperature lower than 350 DEG C.

17. according to the method for claim 13, and wherein, depositing hydrogenated sacrifice layer is included in the hydride layer of deposited silicon nitride on the front of wafer.

18. according to the method for claim 17, wherein, depositing hydrogenated sacrifice layer further comprises: before deposited silicon nitride layer by n-type amorphous silicon layer Direct precipitation on the front of described wafer, and by described silicon nitride layer Direct precipitation on described n-type amorphous silicon layer.

19. according to the method for claim 18, and wherein, the sacrifice layer of removing described hydrogenation comprises described in plasma dry positive to remove described sacrifice layer completely.

20. according to the method for claim 19, and wherein, plasma dry comprises utilizes remote plasma source to carry out described etching.

21. according to the method for claim 20, wherein, further comprises n-type amorphous silicon layer is deposited on the front of described wafer.

22. according to the method for claim 21, further comprises: before deposition n-type amorphous silicon layer by intrinsic amorphous silicon layer Direct precipitation on the front at described wafer, and by n-type amorphous silicon layer Direct precipitation in described intrinsic amorphous silicon layer.

23. according to the method for claim 22, is further included in Direct precipitation ITO on n-type amorphous silicon layer.

24. according to the method for claim 23, is further included in the upper contact grid that directly form of ITO.