CN102291196A - Implementation method and device for detecting asymmetrical time delay of 1588 link circuit automatically - Google Patents
Implementation method and device for detecting asymmetrical time delay of 1588 link circuit automatically Download PDFInfo
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- CN102291196A CN102291196A CN2011102364314A CN201110236431A CN102291196A CN 102291196 A CN102291196 A CN 102291196A CN 2011102364314 A CN2011102364314 A CN 2011102364314A CN 201110236431 A CN201110236431 A CN 201110236431A CN 102291196 A CN102291196 A CN 102291196A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/08—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
- H04L43/0852—Delays
- H04L43/0858—One way delays
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/10—Active monitoring, e.g. heartbeat, ping or trace-route
- H04L43/106—Active monitoring, e.g. heartbeat, ping or trace-route using time related information in packets, e.g. by adding timestamps
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
- H04J3/0658—Clock or time synchronisation among packet nodes
- H04J3/0661—Clock or time synchronisation among packet nodes using timestamps
- H04J3/0667—Bidirectional timestamps, e.g. NTP or PTP for compensation of clock drift and for compensation of propagation delays
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
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Abstract
The invention discloses an implementation method and device for detecting asymmetrical time delay of a 1588 link circuit automatically. The implementation method comprises: running a 1588 time synchronization protocol, and calculating the time deviation value; modifying the time of a slave clock and a time stamp for recording the 1588 time synchronization according to the time deviation value, and calculating the time synchronization deviation value according to the time stamp of the time synchronization; determining whether the time synchronization deviation value is greater than the preset time synchronization deviation threshold; and alarming the asymmetrical time delay of the 1588 link circuit if yes. According to the invention, through comparing the time synchronization deviation value after detection deviation modification with the preset time synchronization deviation threshold, the time delay asymmetry of an upper link circuit and a lower link circuit of the 1588 time synchronization can be detected automatically, and the problem that detection is carried out through a special test instrument artificially, and simultaneously when the link circuit changes, the asymmetrical time delay is detected again is solved.
Description
Technical field
The present invention relates to communication field, relate in particular to a kind of implementation method and device of Auto-Sensing 1588 link asymmetry time delays.
Background technology
Along with the high speed development of 3G network, 1588 time synchronization protocols are more and more paid attention in communication network and are used.Domestic and overseas operators constantly uses 1588 agreements to carry out time synchronized, progressively replaces GPS and carries out time synchronized.
In 1588 time synchronization protocols, method for synchronous as shown in Figure 1.The basis of this 1588 time synchronized is a uplink downlink propagation delay time symmetry.If the uplink downlink propagation delay time is asymmetric, the transmission delay that is uplink downlink is unequal, as shown in Figure 2, then use 1588 time synchronization protocol deviations computing time, half error amount of asymmetry does not calculate in the deviate and goes, make time deviation can not get correct correction, reduce the time synchronized quality.Under asymmetry time delay serious situation, even cause the time basically can't be synchronous.
At the situation of asymmetry time delay, all be to use special test equipment to measure the time delay of 1588 uplink downlinks basically at present, so that find the asymmetry of time delay.This method is the labor intensive material resources not only, and when link changed, whether equipment can't go out to have the asymmetry time delay to exist by Auto-Sensing simultaneously.
Summary of the invention
Main purpose of the present invention provides a kind of implementation method of Auto-Sensing 1588 link asymmetry time delays, is intended to not increase the Auto-Sensing of realizing 1588 link asymmetry time delays under the situation of extra cost.
The invention provides a kind of implementation method of Auto-Sensing 1588 link asymmetry time delays, may further comprise the steps:
Move 1588 time synchronization protocols, computing time deviate;
From clock time, write down the timestamp of 1588 time synchronized according to the correction of time deviation value, and according to the timestamp of time synchronized, computing time the synchronism deviation value;
Judge that whether described time synchronized deviate is greater than the time synchronized deviation thresholding that presets; If then carry out the alarm of 1588 link asymmetry time delays.
Preferably, described operation 1588 time synchronization protocols, computing time, the step of deviate specifically comprised:
When master clock sent synchronous Sync message extremely from clock, record sent the time stamp T 1 of described Sync message and receives the time stamp T 2 of Sync message;
From clock forward delay interval request Delay_req message during to master clock, record sends the time stamp T 3 of Delay_req message and receives the time stamp T 4 of Delay_req message;
Computing time deviate, its computing formula is: ((T2-T1)-(T4-T3))/2.
Preferably, described according to the correction of time deviation value from clock time, write down the timestamp of 1588 time synchronized, and according to the timestamp of time synchronized, computing time, the step of synchronism deviation value comprised specifically:
When master clock sends synchronous Sync message extremely from clock, and record sends the time stamp T 1 of described Sync message and the time stamp T 2 of reception Sync message; Comprise the time deviation value in the described synchronous Sync message, so that according to described time deviation value its time is revised from clock;
From clock forward delay interval request Delay_req message during to master clock, and record sends the time stamp T 3 of Delay_req message and receives the time stamp T 4 of Delay_req message;
Computing time the synchronism deviation value, its computing formula is: (T2-T1)-(T4-T3).
Preferably, also comprise after the synchronism deviation value described computing time:
Suspend the correction of 1588 time synchronized and time deviation.
Preferably, described operation 1588 time synchronization protocols, computing time, the step of deviate also comprised before:
Setup time, the synchronism deviation thresholding did not promptly have asymmetric time time-delay, the precision of equipment time synchronized.
The present invention also provides a kind of implement device of Auto-Sensing 1588 link asymmetry time delays, comprising:
1588 protocol process module are used to move 1588 time synchronization protocols, computing time deviate;
Revise the deviation module, be used for according to the correction of time deviation value writing down the timestamp of 1588 time synchronized, and according to the timestamp of time synchronized from clock time, computing time the synchronism deviation value;
The asymmetry detection module is used to judge that whether described time synchronized deviate is greater than the time synchronized deviation thresholding that presets; If then carry out the alarm of 1588 link asymmetry time delays.
Preferably, described 1588 protocol process module specifically are used for:
When master clock sent synchronous Sync message extremely from clock, record sent the time stamp T 1 of described Sync message and receives the time stamp T 2 of Sync message;
From clock forward delay interval request Delay_req message during to master clock, record sends the time stamp T 3 of Delay_req message and receives the time stamp T 4 of Delay_req message;
Computing time deviate, its computing formula is: ((T2-T1)-(T4-T3))/2.
Preferably, described correction deviation module specifically is used for:
When master clock sent synchronous Sync message extremely from clock, record sent the time stamp T 1 of described Sync message and receives the time stamp T 2 of Sync message; Comprise the time deviation value in the described synchronous Sync message, so that according to described time deviation value its time is revised from clock;
From clock forward delay interval request Delay_req message during to master clock, record sends the time stamp T 3 of Delay_req message and receives the time stamp T 4 of Delay_req message;
Computing time the synchronism deviation value, its computing formula is: (T2-T1)-(T4-T3).
Preferably, described correction deviation module also is used for:
Suspend the correction of 1588 time synchronized and time deviation.
Preferably, described device also comprises:
Parameter configuration module is used for synchronism deviation thresholding setup time, is not promptly having asymmetric time time-delay, the precision of equipment time synchronized.
The present invention compares by detecting time synchronized deviate after the drift correction and pre-configured time synchronized deviation thresholding, thereby can detect the asymmetry of chain-circuit time delay up and down of 1588 time synchronized automatically, solved artificial by special tester detection, simultaneously when link changes, the problem of checking again again.
Description of drawings
Fig. 1 is the schematic flow sheet of 1588 agreement deviations computing time related to the present invention in the prior art;
Fig. 2 is that the schematic flow sheet of deviation appears in the asymmetric 1588 agreement time synchronized that influence that are subjected to related to the present invention in the prior art;
Fig. 3 is the schematic flow sheet of implementation method one embodiment of Auto-Sensing 1588 link asymmetry time delays of the present invention;
Fig. 4 is the structural representation of implement device one embodiment of Auto-Sensing 1588 link asymmetry time delays of the present invention.
The realization of the object of the invention, functional characteristics and advantage will be in conjunction with the embodiments, are described further with reference to accompanying drawing.
Embodiment
Further specify technical scheme of the present invention below in conjunction with Figure of description and specific embodiment.Should be appreciated that specific embodiment described herein only in order to explanation the present invention, and be not used in qualification the present invention.
Fig. 3 is the schematic flow sheet of implementation method one embodiment of Auto-Sensing 1588 link asymmetry time delays of the present invention.
With reference to Fig. 3, the implementation method of Auto-Sensing 1588 link asymmetry time delays of the present invention may further comprise the steps:
Step S101, the operation 1588 time synchronization protocols, computing time deviate;
According to 1588 protocol synchronization processes shown in Figure 1, its running is:
When master clock sent synchronous Sync message extremely from clock, record sent the time stamp T 1 of described Sync message and receives the time stamp T 2 of Sync message;
From clock forward delay interval request Delay_req message during to master clock, record sends the time stamp T 3 of Delay_req message and receives the time stamp T 4 of Delay_req message;
Computing time deviate, its computing formula is:
Offset=((T2-T1)-(T4-T3))/2..................................... formula (1)
Step S102, according to the correction of time deviation value from clock time, write down the timestamp of 1588 time synchronized;
From clock time, its makeover process is according to the correction of time deviation value:
When master clock sent synchronous Sync message extremely from clock, record sent the time stamp T 1 of described Sync message and receives the time stamp T 2 of Sync message; Comprise the time deviation value in the described synchronous Sync message, so that according to described time deviation value its time is revised from clock;
From clock forward delay interval request Delay_req message during to master clock, record sends the time stamp T 3 of Delay_req message and receives the time stamp T 4 of Delay_req message.
Before the time deviation correction, also comprise: suspend the correction of 1588 time synchronized and time deviation.
Step S103, according to the timestamp of time synchronized, computing time the synchronism deviation value;
According to the timestamp of the time synchronized that writes down among the step S102, computing time the synchronism deviation value, i.e. (T2-T1)-(T4-T3);
Whether step S104, judgement time synchronism deviation value greater than the time synchronized deviation thresholding that presets, and is execution in step S105 then; Otherwise execution in step S106;
Time synchronized deviate and time synchronized deviation thresholding that step S103 is calculated compare, if this time synchronized deviate greater than time synchronized deviation thresholding, represents that then 1588 chain circuit transmission time delays are asymmetric; Otherwise represent 1588 chain circuit transmission time delay symmetries.This time synchronized deviation thresholding is pre-configured, promptly do not having under the situation of asymmetric time delay, and the precision of equipment time synchronized, unit is nanosecond.
Step S105, to continue for 1588 normal times synchronous, when waiting for next asymmetry sense cycle, and execution in step S101;
In time synchronism deviation value was less than or equal to the time synchronized deviation thresholding that presets, it was synchronous then to continue for 1588 normal times, and waited for when next asymmetric sense cycle arrives execution in step S101.
Step S106, carry out the alarm of 1588 link asymmetry time delays.
When time synchronism deviation value greater than the time synchronized deviation thresholding that presets, then alarm, thereby can notify the attendant in time to detect link, revise the asymmetry time delay, guarantee the quality of 1588 time synchronized.
Because the hypothesis of above-mentioned formula (1) is up link time delay and downlink delay symmetry.And the actual calculation formula is:
Offset=((T2-T1)-(T4-T3))/2+ (D2-D1)/2............................... formula (2)
Wherein D1 is a downlink delay, and D2 is the up link time delay, thus the time deviation that this step S101 calculates few (D2-D1)/2.Therefore, also there is deviation according to this time deviation value correction from clock time.When the lock in time of calculating among the step S103, deviation was greater than the synchronism deviation thresholding that presets, uplink downlink time delay symmetry then; Otherwise the uplink downlink time delay is asymmetric.
The implementation method of Auto-Sensing 1588 link asymmetry time delays of the present invention compares by detecting time synchronized deviate after the drift correction and pre-configured time synchronized deviation thresholding, thereby can detect the asymmetry of chain-circuit time delay up and down of 1588 time synchronized automatically, solved artificial by special tester detection, simultaneously when link changes, the problem of checking again again.
With reference to Fig. 4, Fig. 4 is the structural representation of implement device one embodiment of Auto-Sensing 1588 link asymmetry time delays of the present invention, and this device can be realized said method.
As shown in Figure 4, the implement device of Auto-Sensing 1588 link asymmetry time delays of the present invention comprises:
1588 protocol process module 101 are used to move 1588 time synchronization protocols, computing time deviate;
Revise deviation module 102, be used for according to the correction of time deviation value writing down the timestamp of 1588 time synchronized, and according to the timestamp of time synchronized from clock time, computing time the synchronism deviation value;
Revise time deviation value correction that deviation module 102 calculates according to 1588 protocol process module from clock time, and record send the time stamp T 1 of synchronous Sync message, the time stamp T 2 that receives the Sync message and forward delay interval request Delay_req message time stamp T 3, receive the time stamp T 4 of Delay_req message.
The time synchronized deviation thresholding that presets in the asymmetry detection module 103 is pre-configured by parameter configuration module, promptly do not having under the situation of asymmetric time delay, and the precision of equipment time synchronized, unit is nanosecond.When time synchronism deviation value greater than the time synchronized deviation thresholding that presets, then alarm, thereby can notify the attendant in time to detect link, revise the asymmetry time delay, guarantee the quality of 1588 time synchronized.
The implement device of Auto-Sensing 1588 link asymmetry time delays of the present invention compares by detecting time synchronized deviate after the drift correction and pre-configured time synchronized deviation thresholding, thereby can detect the asymmetry of chain-circuit time delay up and down of 1588 time synchronized automatically, solved artificial by special tester detection, simultaneously when link changes, the problem of checking again again.And, the present invention increases corresponding software programs and realizes on existing hardware device basis, so do not increase extra hardware cost, the cost increase of software is also little, but reach the asymmetry problem that solves 1588 time synchronized effectively, further saved the manpower and materials cost of opening on the 1588 time synchronized engineerings.
The above only is the preferred embodiments of the present invention; be not so limit its claim; every equivalent structure or equivalent flow process conversion that utilizes specification of the present invention and accompanying drawing content to be done; directly or indirectly be used in other relevant technical fields, all in like manner be included in the scope of patent protection of the present invention.
Claims (10)
1. the implementation method of Auto-Sensing 1588 link asymmetry time delays is characterized in that, may further comprise the steps:
Move 1588 time synchronization protocols, computing time deviate;
From clock time, write down the timestamp of 1588 time synchronized according to the correction of described time deviation value, and according to the timestamp of time synchronized, computing time the synchronism deviation value;
Judge that whether described time synchronized deviate is greater than the time synchronized deviation thresholding that presets; If then carry out the alarm of 1588 link asymmetry time delays.
2. method according to claim 1 is characterized in that, described operation 1588 time synchronization protocols, and computing time, the step of deviate specifically comprised:
When master clock sent synchronous Sync message extremely from clock, record sent the time stamp T 1 of described Sync message and receives the time stamp T 2 of Sync message;
From clock forward delay interval request Delay_req message during to master clock, record sends the time stamp T 3 of Delay_req message and receives the time stamp T 4 of Delay_req message;
Computing time deviate, its computing formula is: ((T2-T1)-(T4-T3))/2.
3. method according to claim 1 is characterized in that, described according to the correction of time deviation value from clock time, write down the timestamp of 1588 time synchronized, and according to the timestamp of time synchronized, computing time, the step of synchronism deviation value comprised specifically:
When master clock sent synchronous Sync message extremely from clock, record sent the time stamp T 1 of described Sync message and receives the time stamp T 2 of Sync message; Comprise the time deviation value in the described synchronous Sync message, so that according to described time deviation value its time is revised from clock;
From clock forward delay interval request Delay_req message during to master clock, record sends the time stamp T 3 of Delay_req message and receives the time stamp T 4 of Delay_req message;
Computing time the synchronism deviation value, its computing formula is: (T2-T1)-(T4-T3).
4. method according to claim 3 is characterized in that, also comprises after the synchronism deviation value described computing time:
Suspend the correction of 1588 time synchronized and time deviation.
5. according to each described method in the claim 1 to 4, it is characterized in that, described operation 1588 time synchronization protocols, computing time, the step of deviate also comprised before:
Setup time, the synchronism deviation thresholding did not promptly have asymmetric time time-delay, the precision of equipment time synchronized.
6. the implement device of Auto-Sensing 1588 link asymmetry time delays is characterized in that, comprising:
1588 protocol process module are used to move 1588 time synchronization protocols, computing time deviate;
Revise the deviation module, be used for according to the correction of time deviation value writing down the timestamp of 1588 time synchronized, and according to the timestamp of time synchronized from clock time, computing time the synchronism deviation value;
The asymmetry detection module is used to judge that whether described time synchronized deviate is greater than the time synchronized deviation thresholding that presets; If then carry out the alarm of 1588 link asymmetry time delays.
7. device according to claim 6 is characterized in that, described 1588 protocol process module specifically are used for:
When master clock sent synchronous Sync message extremely from clock, record sent the time stamp T 1 of described Sync message and receives the time stamp T 2 of Sync message;
From clock forward delay interval request Delay_req message during to master clock, record sends the time stamp T 3 of Delay_req message and receives the time stamp T 4 of Delay_req message;
Computing time deviate, its computing formula is: ((T2-T1)-(T4-T3))/2.
8. according to the device of claim 6, it is characterized in that described correction deviation module specifically is used for:
When master clock sent synchronous Sync message extremely from clock, record sent the time stamp T 1 of described Sync message and receives the time stamp T 2 of Sync message; Comprise the time deviation value in the described synchronous Sync message, so that according to described time deviation value its time is revised from clock;
From clock forward delay interval request Delay_req message during to master clock, record sends the time stamp T 3 of Delay_req message and receives the time stamp T 4 of Delay_req message;
Computing time the synchronism deviation value, its computing formula is: (T2-T1)-(T4-T3).
9. device according to claim 8 is characterized in that, described correction deviation module also is used for:
Suspend the correction of 1588 time synchronized and time deviation.
10. according to each described device in the claim 6 to 9, it is characterized in that, also comprise:
Parameter configuration module is used for synchronism deviation thresholding setup time, is not promptly having asymmetric time time-delay, the precision of equipment time synchronized.
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| CN2011102364314A CN102291196A (en) | 2011-08-17 | 2011-08-17 | Implementation method and device for detecting asymmetrical time delay of 1588 link circuit automatically |
| PCT/CN2012/079570 WO2013023530A1 (en) | 2011-08-17 | 2012-08-02 | Implementation method and device for automatically detecting asymmetry time delay of 1588 link |
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| CN102546009A (en) * | 2012-01-17 | 2012-07-04 | 华为技术有限公司 | Optical fiber symmetry detecting method and device |
| CN102629897A (en) * | 2012-03-07 | 2012-08-08 | 华为技术有限公司 | Time efficiency discrimination method, control device and mechanical device |
| CN102769504A (en) * | 2012-07-11 | 2012-11-07 | 中兴通讯股份有限公司 | 1588 system and method thereof for achieving synchronization |
| WO2013023530A1 (en) * | 2011-08-17 | 2013-02-21 | 中兴通讯股份有限公司 | Implementation method and device for automatically detecting asymmetry time delay of 1588 link |
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