CN102279386B - SAR (Synthetic Aperture Radar) imaging signal processing data transposing method based on FPGA (Field Programmable Gata Array) - Google Patents
SAR (Synthetic Aperture Radar) imaging signal processing data transposing method based on FPGA (Field Programmable Gata Array) Download PDFInfo
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Abstract
本发明公开了一种基于FPGA的SAR成像信号处理数据转置方法，主要解决基于DSP实时成像处理CTM功耗高、速度慢、效率低和不能抗辐射的问题。其实现步骤为：将信号处理数据通过FPGA存入到DDRII SDRAM存储器中；将DDRII SDRAM存储器中的矩阵数据进行矩阵分割；依次进行对角模式矩阵块的转置处理和对称非对角模式矩阵块的转置处理；当距离向采样点数和方位向采样点数不相等时，进行非对称非对角模式矩阵块的转置处理；转置完成后进行复位操作；根据要求通过FPGA读出DDRII SDRAM中转置处理完成后的数据。本发明极大地提高了DDRII SDRAM的工作效率，使转置存储器CTM系统运行更稳定、功耗更低、速度更快、效率更高、能抗辐射，可应用于合成孔径雷达成像系统设计。
The invention discloses an FPGA-based SAR imaging signal processing data transposition method, which mainly solves the problems of high power consumption, slow speed, low efficiency and inability to resist radiation in real-time imaging processing CTM based on DSP. The implementation steps are: storing the signal processing data into the DDRII SDRAM memory through the FPGA; performing matrix division on the matrix data in the DDRII SDRAM memory; sequentially performing the transposition processing of the diagonal pattern matrix block and the symmetrical non-diagonal pattern matrix block Transpose processing; when the number of sampling points in the distance direction and the number of sampling points in the azimuth direction are not equal, perform the transposition processing of the asymmetric non-diagonal pattern matrix block; perform the reset operation after the transposition is completed; read the DDRII SDRAM transfer through the FPGA as required Set the processed data. The invention greatly improves the working efficiency of DDRII SDRAM, makes the transposition memory CTM system run more stably, has lower power consumption, faster speed, higher efficiency and radiation resistance, and can be applied to the design of synthetic aperture radar imaging system.
Description
Technical field
The invention belongs to digital signal processing technique field, relate to DDRII SDRAM transpose memory, particularly a kind of FPGA that utilizes realizes SAR imaging signal deal with data transposition method, can be applicable to the synthetic aperture radar image-forming system.
Background technology
Synthetic-aperture radar SAR is as a kind of active microwave sensor, can not be subjected to the restriction of illumination and weather conditions to realize round-the-clock, round-the-clock earth observation, obtain high-resolution ground scene information, can also obtain information under the earth's surface through earth's surface and vegetation, and can survey concealed target.These characteristics make it have unique advantage in application such as military field such as battlefield terrain detection and early warning, civil area such as resource investigation, environmental monitoring, hydrologic observations.The characteristics that the SAR imaging signal is processed are that computing is complicated, and data volume is large, and this just requires system can carry out fast transport and the storage of big data quantity when carrying out quick computing.Transpose memory CTM is an important component part of SAR real-time processor, it is the significant process that realizes from the Raw Data Generation image, by transferring the orientation continuous data to apart from continuous data, or the orientation continuous data transferred to apart from continuous data, realize the SAR imaging processing, up to hundreds of million data throughput speed and the capacity of transpose memory proposed very high requirement around here, the efficient that transposition is realized becomes the principal element that restriction SAR real time imagery is processed.
The development of processing along with the SAR real time imagery makes great progress for the research of CTM, and many practical CTM that succeed in developing are applied in the Real Time Image System.Generally, adopt DSP as the core of imaging processing, cooperate the built-in sdram controller of DSP, use the method for software, utilize SDRAM that data are carried out the transposition computing, specifically by the access mode of address saltus step, be equivalent to " software " transposition.Yet, " software " transposition does not have that " hardware " transposition is low in energy consumption, speed is fast and efficient is high, DSP does not have enough hardware resources to utilize simultaneously, processing speed is fast not, dirigibility is not strong, along with more and more higher to the requirement of SAR handling property, the implementation of employing DSP far can not satisfy the requirement of this trend aspect efficient.
On the other hand, along with the development of Spaceborne SAR System, real time imagery becomes a research hot topic in SAR field on the star in recent years.Process for real time imagery on the star, CTM must satisfy on the star environment to the anti-irradiation requirement of hardware.Because DSP does not have the anti-irradiation products of space flight level at present, adopt DSP to be not suitable with the requirement of On-Star system as the scheme of imaging processing core, real time imagery is processed CTM and must be adopted new scheme realization on the star.
Summary of the invention
The object of the invention is to overcome the deficiency of above-mentioned prior art, a kind of SAR imaging signal deal with data transposition method based on FPGA is provided, realize " hardware " transposition, so that the operation of CTM system is more stable, power consumption is lower, speed is faster, efficient is higher, with the complete requirement that can satisfy the real-time image processing transpose storage.
The technical thought that realizes the object of the invention is, based on " matrix is cut apart " thought, large matrix is divided into minor matrix, respectively for the matrix-block of the matrix-block of diagonal pattern, symmetrical non-diagonal pattern, the matrix-block of asymmetric non-diagonal pattern, utilize the DDRII sdram controller design of FPGA and the RAM resource of FPGA inside, implementation step comprises as follows:
(1) with SAR imaging signal deal with data by distance to importing continuously FPGA into from front end, deposit data in DDRII SDRAM storer by FPGA again, form matrix data;
(2) matrix data in the DDRII SDRAM storer being carried out matrix cuts apart:
(2a) take 64 * 64 minor matrix pieces as unit, the diagonal by square formation marks off the symmetric pattern matrix-block with matrix data;
(2b) take 64 * 64 minor matrix pieces as unit, as axis of symmetry, matrix data is marked off symmetrical non-diagonal pattern matrix-block with the diagonal line of square formation;
(2c) take 64 * 64 minor matrix pieces as unit, mark off asymmetric non-diagonal pattern matrix-block with removing square formation residual matrix data in addition;
(3) the RAM memory resource among the use FPGA, deposit unit diagonal pattern matrix-block data in RAM, utilize the address saltus step to read data among the RAM every 64 addresses, the unit's of finishing diagonal pattern matrix-block Data in Azimuth Direction and distance realize the transpose process of diagonal pattern matrix-block to data-switching;
(4) transpose process of symmetrical non-diagonal pattern matrix-block:
(4a) the symmetrical non-diagonal pattern matrix-block of the unit more than the square formation diagonal line laterally is divided into two equal semi-identity matrix pieces, the more symmetrical non-diagonal pattern matrix-block of the unit below the square formation diagonal line vertically is divided into two equal semi-identity matrix pieces;
(4b) the RAM memory resource among the use FPGA, deposit RAM in horizontal semi-identity matrix blocks of data with vertical semi-identity matrix blocks of data of its symmetry, utilize the address saltus step to read data among the RAM every 32 addresses first, be written in the horizontal semi-identity matrix piece, read data among the RAM every 64 addresses again, be written in vertical semi-identity matrix piece, finish horizontal semi-identity matrix blocks of data and with the vertical semi-identity matrix blocks of data conversion of its symmetry;
(5) when distance is unequal to sampling number to sampling number and orientation, use the RAM memory resource among the FPGA, deposit the asymmetric non-diagonal pattern matrix-block data of unit in RAM, utilize the address saltus step to read data among the RAM every 64 addresses, the asymmetric non-diagonal pattern matrix-block Data in Azimuth Direction of the unit of finishing and distance realize the transpose process of asymmetric non-diagonal pattern matrix-block to data-switching; Otherwise do not need to carry out the transpose process of asymmetric non-diagonal pattern matrix-block;
(6) after transposition is finished, carry out reset operation, in order to again carry out transpose process;
(7) with the data after transposition is finished dealing with in the DDRII SDRAM storer, as requested by FPGA by the orientation to reading.
The present invention compared with prior art has the following advantages:
One, the present invention is owing to passing through, so that the operation of transpose memory CTM system is more stable, power consumption is lower, speed is faster, efficient is higher.
The FPGA of current main-stream together with the powerful fixed-point processing ability of data flow-based, makes FPGA be a dark horse in the signal process field because its inside is integrated with a large amount of multipliers, RAM even processor core.Simultaneously, FPGA has the product of army's grade, the FPGA that can satisfy the extreme environments such as Aero-Space carries out SAR imaging signal deal with data transposition system level and uses, particularly to carry out SAR imaging signal deal with data transposition by DSP, FPGA has more hardware resource and can utilize, and processing speed is faster, and dirigibility is better, improve the real-time of whole system, realized " hardware " transposition.
They are two years old, because the present invention adopts " matrix is cut apart " thought, the front end matrix data is divided into equal-sized minor matrix piece, and carry out transpose process according to diagonal pattern, symmetrical non-diagonal pattern and asymmetric non-diagonal pattern, avoided all continuously DDRII SDRAM storer being carried out the read-write operation of inter-bank at every turn, only have few action need continuously the different rows of same bank to be operated, so with respect to using three-leaf type, improved greatly the work efficiency of DDRIISDRAM storer.
They are three years old, according to the distance of Radar Imaging Processing data to the orientation all be 2 n power to counting, the present invention uses 64 * 64 minor matrix pieces as unit, can both satisfy 64 integral multiple so that the vertical and horizontal of matrix are counted, in all SAR imaging rudimentary algorithms, can both use this module to carry out transpose process like this.
They are four years old, because the present invention has carried out piecemeal and the RAM resource of using among the FPGA to matrix, so that read-write storage and the matrix transpose operation of data all only needed to use one group of DDRII SDRAM storer just can realize, greatly the steering logic of DDRII SDRAM storer is utilized, so that in the SAR Real Time Image System, control simultaneously two groups of DDRII SDRAM storeies by a slice FPGA, for continuous data stream, control in turn receive data and carry out transpose process of two groups of DDRII SDRAM storeies by FPGA, can form line production, to reach the effect of real-time processing.
Description of drawings
Fig. 1 is the realization block diagram that the present invention is based on the SAR imaging signal deal with data transposition method of FPGA;
Fig. 2 is the pattern block diagram before the transposition of the present invention;
Fig. 3 is the pattern block diagram after transposition of the present invention is finished;
Fig. 4 be with the present invention before to transpose process the input data and the functional simulation figure of the output data after the transpose process;
Fig. 5 is the board level test figure with the input data of the present invention before to transpose process.
Fig. 6 is the board level test figure with the output data of the present invention after to transpose process.
Embodiment
The present invention will be further described below in conjunction with accompanying drawing.
The present invention carries out transposition by FPGA to SAR imaging signal deal with data, and employed fpga chip is StratixIII EP3SL340H1152I3, perhaps uses StratixII EP2S90F1020I4 model, but is not limited to these two kinds.
With reference to Fig. 1, implementation step of the present invention is as follows:
Because the throughput of user side and DDRII SDRAM storer end is different, this step mainly is to call that asynchronous FIFO memory carries out caching process to data among the FPGA, realize simultaneously FIFO two ends clock synchronously.
With reference to Fig. 2, being implemented as follows of this step:
(2a) take 64 * 64 minor matrix pieces as unit, the diagonal by square formation marks off the symmetric pattern matrix-block with matrix data;
(2b) take 64 * 64 minor matrix pieces as unit, as axis of symmetry, matrix data is marked off symmetrical non-diagonal pattern matrix-block with the diagonal line of square formation;
(2c) take 64 * 64 minor matrix pieces as unit, mark off asymmetric non-diagonal pattern matrix-block with removing square formation residual matrix data in addition;
The front end matrix data is divided into equal-sized 64 * 64 minor matrix pieces, the distance of SAR imaging signal deal with data is compared to sampling number to sampling number and orientation, consist of square formation with both medium and small counting as the limit, and determine it is to use two kinds of patterns or three kinds of patterns through more resulting result, when distance equates to sampling number to sampling number and orientation, carry out transpose process by diagonal pattern and symmetrical non-diagonal pattern; Unequal to sampling number to sampling number and orientation when distance, carry out transpose process by diagonal pattern, symmetrical non-diagonal pattern and asymmetric non-diagonal pattern.
The RAM resource of this step among the FPGA, the size of RAM is 64 * 64, and the matrix-block of diagonal pattern is processed, and namely the white matrix piece among Fig. 2 is handled as follows:
At first, first 64 * 64 fritter matrix data read in RAM by row from DDRII SDRAM storer;
Then, utilize the address saltus step every 64 addresses RAM being jumped and read, from zero-address, every 64 address read-outing datas, after jumping to address 4032, turn back to address 1, circulation is until read the data of last address successively.The data of reading are deposited in the DDRII SDRAM storer by row again, deposit the position of position for reading this matrix-block before in, namely finish the transpose process to this minor matrix piece;
At last, carry out the transpose process of next diagonal angle minor matrix piece.Except unit diagonal pattern matrix-block data being deposited in RAM and reading the continued operation of data to the address among the RAM, also needing has the following address jump operation during this time:
Forward the start address of next line to from last address of unit matrix piece delegation;
The start address of getting back to this unit matrix piece from last address of unit matrix piece;
Forward the start address of next unit matrix piece to from last address of unit matrix piece.
The transpose process of the symmetrical non-diagonal pattern matrix-block of step 4..
(4a) the symmetrical non-diagonal pattern matrix-block of the unit more than the square formation diagonal line laterally is divided into two equal semi-identity matrix pieces, again the symmetrical non-diagonal pattern matrix-block of the unit below the square formation diagonal line vertically is divided into two equal semi-identity matrix pieces, such as Fig. 2 backslash line matrix-block;
(4b) the RAM memory resource among the use FPGA, deposit RAM in horizontal semi-identity matrix blocks of data with vertical semi-identity matrix blocks of data of its symmetry, utilize the address saltus step to read data among the RAM every 32 addresses first, be written in the horizontal semi-identity matrix piece, read data among the RAM every 64 addresses again, be written in vertical semi-identity matrix piece, finish horizontal semi-identity matrix blocks of data and with the vertical semi-identity matrix blocks of data conversion of its symmetry;
Use the RAM memory resource in the step 3, the matrix-block of the non-diagonal pattern of symmetry processed, namely the backslash line matrix-block among Fig. 2 is handled as follows:
At first, the symmetrical non-diagonal pattern matrix-block of unit more than the square formation diagonal line laterally is divided into two equal semi-identity matrix pieces, again the symmetrical non-diagonal pattern matrix-block of the unit below the square formation diagonal line vertically is divided into two equal semi-identity matrix pieces, the order that reads and writes data under this pattern and position are the data of reading continuously minor matrix piece 1 by row first, the data of reading continuously minor matrix piece 4 by row again;
Then, the data of utilizing the address saltus step to read the medium and small matrix-block 4 of RAM every 32 addresses first are written in the horizontal minor matrix piece 1 data of reading the medium and small matrix-block 1 of RAM every 64 addresses again, be written in vertical minor matrix piece 4, namely finish the transpose process to minor matrix piece 1 and minor matrix piece 4;
Then, by going the data of reading continuously minor matrix piece 2, the data of reading continuously minor matrix piece 5 by row again, with the first data of reading the medium and small matrix-block 5 of RAM every 32 addresses of address saltus step, be written in the horizontal minor matrix piece 2, the data of reading the medium and small matrix-block 2 of RAM every 64 addresses again are written in vertical minor matrix piece 5, finish the transpose process to minor matrix piece 2 and minor matrix piece 5; Finish the transpose process of minor matrix piece 3 and minor matrix piece 6 with same operation;
Then, by going the data of reading continuously minor matrix piece 1a, the data of reading continuously minor matrix piece 4a by row again, with the first data of reading the medium and small matrix-block 4a of RAM every 32 addresses of address saltus step, be written among the horizontal minor matrix piece 1a, the data of reading the medium and small matrix-block 1a of RAM every 64 addresses again are written among vertical minor matrix piece 4a, finish the transpose process to minor matrix piece 1a and minor matrix piece 4a; Finish again the transpose process of minor matrix piece 2b and minor matrix piece 5b according to aforesaid operations, the transpose process of minor matrix piece 3c and minor matrix piece 6c; Finish the transpose process of symmetrical non-all minor matrix pieces of diagonal pattern matrix-block with same operation, as shown in Figure 3.
This step is identical with step 3, has also called the RAM resource among the FPGA, and the size of RAM is 64 * 64, and the matrix-block of asymmetric non-diagonal pattern is processed, and namely the twill matrix-block among Fig. 2 is handled as follows:
At first, first 64 * 64 fritter matrix data read in RAM by row from DDRII SDRAM storer;
Then, utilizing the address saltus step every 64 addresses RAM being jumped reads, the data of reading are deposited in the DDRII SDRAM storer by row again, deposit the position in for reading this matrix-block by the matrix-block position of diagonal line symmetry before, namely finish the transpose process to this minor matrix piece;
At last, carry out the transpose process of next asymmetric non-diagonal angle minor matrix piece.
After step 6. transposition is finished, the component register sum counter is carried out the software reset, so that can correctly finish based on the SAR imaging signal deal with data transposition of FPGA next time.
Step 7. is the data after transposition is finished dealing with in the DDRII SDRAM storer, as requested by FPGA by the orientation to reading.
Because the throughput of user side and DDRII SDRAM storer end is different, this step mainly is to call that asynchronous FIFO memory carries out caching process to data among the FPGA, realize simultaneously FIFO two ends clock synchronously.
Effect of the present invention can further specify by following actual measurement
1. verify and the actual measurement condition
When functional simulation, because testing efficiency is excessively low during the excessive so that emulation of data volume, be 128 so adopt during emulation the orientation of input data to count to sampled data, it is 192 that distance is counted to sampled data, namely the input data matrix piece is 192 * 128 matrix.Design input data is: the data of the first row are that the data of 128 1, the second row are 128 2, produce by that analogy 192 row data, and the data of last column are 128 192.
Input partial data when board level test, counting to sampled data in the orientation is 4096, and it is 512 that distance is counted to sampled data, and namely the input data matrix piece is 512 * 4096 matrix.Design input data is: the data of the first row are 1～4096 4096 continuous number, and the data of the second row also are 1～4096 4096 continuous numbers, and each provisional capital is 1～4096 4096 continuous number, altogether 512 row by that analogy.
2. verify and measured result
2A) checking input data matrix 192 * 128 is 128 * 192 through resulting data matrix behind the transposition, the result as shown in Figure 4, wherein Fig. 4 (a) is the input data before the transpose process, the data that explanation writes from FPGA in every delegation of DDRIISDRAM are identical, and the data of every delegation all increase progressively; Fig. 4 (b) is the first row input data before the transpose process; Fig. 4 (c) is the data of exporting from DDRII SDRAM storer after the transpose process, the output data are that the data of the first row are 1～192 192 continuous number after the transpose process, the second row also is 1～192 192 continuous number, each provisional capital is 1～192 192 continuous number by that analogy, 128 row altogether, data in the every delegation of data that explanation is exported in the DDRII SDRAM storer all increase progressively, namely after the transpose process the data matrix be 128 * 192.By functional simulation, can find out that from this three width of cloth figure this matrix transpose module finished the transposition function of data.
2B) checking input data matrix 512 * 4096 is 4096 * 512 through resulting data matrix behind the transposition, the result as shown in Figure 5 and Figure 6, wherein Fig. 5 (a) is the input data before the transpose process; Fig. 5 (b) is the front end enlarged drawing of Fig. 5 (a), illustrates that the input data are to increase progressively since 1; Fig. 5 (c) is the rear end enlarged drawing of Fig. 5 (a), illustrates that the input data increase progressively until 4096 since 1; Fig. 6 (a) is the data of exporting from DDRII SDRAM storer after the transpose process; Fig. 6 (b) is the first row data of exporting from DDRII SDRAM storer after the transpose process; Fig. 6 (c) be after the transpose process from last column data of DDRII SDRAM storer output, illustrate that exporting data after the transpose process is that the value of the first row is 512 1; 512 2 of the second behaviors produce 4096 row data by that analogy, and last column is 512 4096, and namely getting the data matrix after the transpose process is 4096 * 512.From Fig. 5 and Fig. 6 as seen, the present invention can realize the SAR imaging signal deal with data transposition based on FPGA.
Claims (3)
1. the SAR imaging signal deal with data transposition method based on FPGA comprises the steps:
(1) with SAR imaging signal deal with data by distance to importing continuously FPGA into from front end, deposit data in DDRII SDRAM storer by FPGA again, form matrix data;
(2) matrix data in the DDRII SDRAM storer being carried out matrix cuts apart:
(2a) take 64 * 64 minor matrix pieces as unit, the diagonal by square formation marks off the diagonal pattern matrix-block with matrix data,
Described square formation is that the distance with SAR imaging signal deal with data compares to sampling number to sampling number and orientation, consists of square formation with both medium and small counting as the limit;
(2b) take 64 * 64 minor matrix pieces as unit, as axis of symmetry, matrix data is marked off symmetrical non-diagonal pattern matrix-block with the diagonal line of square formation;
(2c) take 64 * 64 minor matrix pieces as unit, mark off asymmetric non-diagonal pattern matrix-block with removing square formation residual matrix data in addition;
(3) the RAM memory resource among the use FPGA, deposit unit diagonal pattern matrix-block data in RAM, utilize the address saltus step to read data among the RAM every 64 addresses, the unit's of finishing diagonal pattern matrix-block Data in Azimuth Direction and distance realize the transpose process of diagonal pattern matrix-block to data-switching;
(4) transpose process of symmetrical non-diagonal pattern matrix-block:
(4a) the symmetrical non-diagonal pattern matrix-block of the unit more than the square formation diagonal line laterally is divided into two equal semi-identity matrix pieces, the more symmetrical non-diagonal pattern matrix-block of the unit below the square formation diagonal line vertically is divided into two equal semi-identity matrix pieces;
(4b) the RAM memory resource among the use FPGA, deposit RAM in horizontal semi-identity matrix blocks of data with vertical semi-identity matrix blocks of data of its symmetry, utilize the address saltus step to read data among the RAM every 32 addresses first, be written in the horizontal semi-identity matrix piece, read data among the RAM every 64 addresses again, be written in vertical semi-identity matrix piece, finish horizontal semi-identity matrix blocks of data and with the vertical semi-identity matrix blocks of data conversion of its symmetry;
(5) when distance is unequal to sampling number to sampling number and orientation, use the RAM memory resource among the FPGA, deposit the asymmetric non-diagonal pattern matrix-block data of unit in RAM, utilize the address saltus step to read data among the RAM every 64 addresses, the asymmetric non-diagonal pattern matrix-block Data in Azimuth Direction of the unit of finishing and distance realize the transpose process of asymmetric non-diagonal pattern matrix-block to data-switching; Otherwise do not need to carry out the transpose process of asymmetric non-diagonal pattern matrix-block;
(6) after transposition is finished, carry out reset operation, in order to again carry out transpose process;
(7) with the data after transposition is finished dealing with in the DDRII SDRAM storer, as requested by FPGA by the orientation to reading.
2. the SAR imaging signal deal with data transposition method based on FPGA according to claim 1, it is characterized in that: read data among the RAM every 64 addresses described in the step (3), from zero-address, every 64 address read-outing datas, after jumping to address 4032, turn back to address 1, circulation is until read the data of last address successively.
3. the SAR imaging signal deal with data transposition method based on FPGA according to claim 1 is characterized in that: the reset operation described in the step (6) refers to the software reset of component register sum counter.
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