CN102244067A - Fuse wire structure - Google Patents
Fuse wire structure Download PDFInfo
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- CN102244067A CN102244067A CN2011102135090A CN201110213509A CN102244067A CN 102244067 A CN102244067 A CN 102244067A CN 2011102135090 A CN2011102135090 A CN 2011102135090A CN 201110213509 A CN201110213509 A CN 201110213509A CN 102244067 A CN102244067 A CN 102244067A
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- fuse
- lead
- weld pad
- chip
- cutting road
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Abstract
The invention discloses a fuse wire structure which comprises fuse wires and solder pads, wherein the solder pads are electrically connected with the fuse wires; the fuse wires are positioned in a chip; the chip is positioned on a silicon wafer; and the solder pads are positioned on a cutting channel between two adjacent chips on the silicon wafer. The number of the solder pads in the chip can be reduced through the technical scheme, which is good for reducing the chip area.
Description
Technical field
The present invention relates to technical field of semiconductors, relate in particular to a kind of fuse-wires structure.
Background technology
In semiconductor applications, if desired circuit is calibrated, for example repair and transfer resistance, electric capacity, electric current etc., can wait and realize the circuit calibration by electric current fuse, Zener breakdown pipe or laser-adjusting fuse and circuit programming such as EEPROM, EPROM, OTP.
Yet Zener breakdown pipe, circuit programming, laser-adjusting fuse only are suitable for special process.The advantage of electric current fuse is: testing cost is low, and each technology is all supported.The two ends of electric current fuse need be electrically connected with weld pad (pad), and fuse is formed on chip internal, is electrically connected with weld pad by metal interconnecting wires.Wherein, in the prior art, weld pad is formed on chip internal, the two ends of each fuse all are electrically connected with two weld pads usually, the shared area of weld pad is bigger, and for example for the chip of a 400*400, the area of the weld pad that is electrically connected with fuse needs 80*80, therefore weld pad has taken the chip additional areas, be unfavorable for dwindling area of chip like this, therefore, very low for a profit own, the chip of race amount, owing to will do the electric current fuse, put several weld pads more, the quantity of chip that can output is reduced, the original meagre profit of chip becomes does not make money, even loss of capital, thereby may abandon former present design.
Prior art all is based on weld pad and inserts that chip internal goes to consider, so can't thoroughly solve the problem that area that weld pad brings increases.
Many patent and patent applications about fuse-wires structure are arranged in the prior art, and for example the application number of on July 9th, 2004 application is that 200480020282.6 Chinese patent discloses a kind of fuse-wires structure, yet does not all solve above-described technical problem.
Summary of the invention
The problem that the present invention solves is to use the electric current fuse to introduce the problem that weld pad brings chip area to increase.
For addressing the above problem, the specific embodiment of the invention provides a kind of fuse-wires structure, comprises fuse and the weld pad that is electrically connected with fuse, and described fuse is positioned at chip, and described chip is positioned on the wafer, and described weld pad is at the Cutting Road between adjacent two chips on the wafer.
Optionally, described Cutting Road comprises first Cutting Road and second Cutting Road, and described first Cutting Road is vertical mutually with second Cutting Road;
Described weld pad is positioned at first Cutting Road and/or second Cutting Road.
Optionally, described fuse and weld pad are electrically connected by lead, and described lead passes through the cutting position of adjacent two chips.
Optionally, described lead comprises first lead and second lead;
Described first lead is parallel with described second Cutting Road, described second lead is parallel with described first Cutting Road, one end of described first lead is electrically connected with fuse, one end of described second lead is electrically connected with described weld pad, and the link position of described first lead and described second lead is on the extended line of weld pad away from the edge of fuse.
Optionally, described lead is a metal wire.
Compared with prior art, the technical program has the following advantages:
The fuse-wires structure of the technical program, fuse is located in the chip, the weld pad that connects fuse is on the Cutting Road between adjacent two chips on the wafer, can reduce the quantity of the weld pad in chip like this, help reducing chip area, thereby also just can increase on the wafer quantity of chip that can output, save cost.
Description of drawings
Fig. 1 is the schematic diagram of the fuse-wires structure of the present invention's first specific embodiment;
Fig. 2 is the schematic diagram of the fuse-wires structure of the present invention's second specific embodiment.
Embodiment
In the prior art, the welding that connects the electric current fuse all is positioned on the chip, and the area of each weld pad that is connected with fuse is all bigger, has so just caused area of chip to be difficult to dwindle.Take the technical problem that causes chip area to increase than large tracts of land in order to solve weld pad, the weld pad that fuse-wires structure of the present invention will connect fuse is located on the Cutting Road between the adjacent chips, can reduce the chip area that the weld pad that connects fuse takies like this, also just help dwindling area of chip.
Usually have a plurality of chips on the wafer, be formed with fuse in the chip, weld pad is formed on the chip and is electrically connected with fuse, after the chip process is detected, pass through as required to the weld pad making alive, come to make fuse opening or do not blow, thereby the electric current of adjusting circuit reaches desired value, weld pad is just ineffective after this, thereby the connection between weld pad and the fuse can be disconnected, but in the prior art, usually weld pad is made in the chip, therefore blowing or can not becoming single chip to the chip cutting that wafer cutting will be positioned on the wafer after the blown fuse, after chip formed, weld pad is the not effect of reality in chip.The inventor finds that the area of the Cutting Road between the adjacent chips is bigger, and this area can be used for forming weld pad, weld pad can be formed on like this on the Cutting Road between adjacent two chips, avoids weld pad to be formed on chip internal and takies area of chip.
For those skilled in the art be can better understand the present invention, describe the fuse-wires structure of the specific embodiment of the invention in detail below in conjunction with accompanying drawing.
Fig. 1 is the fuse-wires structure schematic diagram of the present invention's first specific embodiment, with reference to figure 1, have a plurality of chips 20 on the wafer 10, the fuse-wires structure of the specific embodiment of the invention, comprise fuse 21 and the weld pad 22 that is electrically connected with fuse 21, described fuse 21 is positioned at chip 20, and described chip 20 is positioned on the wafer 10, and described weld pad 22 is on the Cutting Road between adjacent two chips 20 on the wafer 10.
Therefore chip 20 on the wafer 10 is normally arranged according to the mode of array, and the Cutting Road between adjacent two chips 20 comprises that first Cutting Road 231 and second Cutting Road, 232, the first Cutting Roads 231 are vertical mutually with second Cutting Road 232.In first embodiment shown in Figure 1, weld pad 22 is positioned on first Cutting Road 231, and described fuse 21 and weld pad 22 are electrically connected by lead, and described lead passes through the cutting position of adjacent two chips.Because weld pad 22 is exposed in the external environment usually, so weld pad 22 is subjected to the steam in the environment, the influence of contaminant particles etc. may be corroded, oxidation etc., if when cutting crystal wafer is divided into single chip with the chip on the wafer, weld pad 22 still is electrically connected with fuse by lead, be corroded, the weld pad of oxidation etc. is owing to be electrically connected with fuse, can influence the performance of chip like this, in order to prevent that weld pad is corroded, oxidations etc. influence the performance of chip, therefore lead passes through the cutting position of adjacent two chips, when guaranteeing cutting crystal wafer, lead is cut, thereby makes the disconnection that is electrically connected of fuse 21 and weld pad 22.In order to realize this purpose, in the first embodiment of the invention, described lead comprises first lead 241 and second lead 242; Described first lead 241 is parallel with described second Cutting Road 232, described second lead 242 is parallel with described first Cutting Road 231, one end of described first lead 241 is electrically connected with fuse 21, one end of described second lead 242 is electrically connected with described weld pad 22, and the link position 25 of described first lead 241 and described second lead 242 is on the extended line of weld pad 22 away from the edge of fuse 21.That is to say that the lead that connects fuse 21 and weld pad 22 extends to weld pad 22 and extends to weld pad 22 in the turning again away from the edge of fuse 21.Need to prove that edge herein is not strict finger weld pad 22 away from beyond the fuse 21, all can as long as when weld pad 22 guarantees cutting crystal wafer in away from the certain width scope beyond the fuse 21, can cut to first lead 241.
In the specific embodiment of the invention, the material of fuse 21 can be determined according to the application of reality.Lead is a metal wire, and the material of this metal wire can well known to a person skilled in the art material for copper, aluminium, tungsten etc.Certainly, this lead is not limited to metal wire, and it also can be electrically connected fuse 21 as long as satisfy to play for well known to a person skilled in the art other leads with weld pad 22.
In the specific embodiment of the invention, the effect of fuse can be used for regulating electric current and also can be used for regulating resistance and voltage and well known to a person skilled in the art other purposes.
Fig. 2 is the fuse-wires structure schematic diagram of the present invention's second specific embodiment, with reference to figure 2, in the fuse-wires structure of this second specific embodiment, because the quantity of weld pad 22 is more, first Cutting Road 231 is not enough to place all weld pads 22, therefore weld pad was arranged in 22 minutes, is positioned on first Cutting Road 231 and second Cutting Road 232.
Other details of second specific embodiment are identical with first specific embodiment, do not do at this and give unnecessary details.
In the 3rd specific embodiment of the present invention, weld pad 22 also can only be positioned on second Cutting Road 232, and other are identical with first embodiment, do not do at this and give unnecessary details.
Need to prove the quantity of the chip 20 on the wafer 10 that goes out illustrated in figures 1 and 2 of the present invention and arrange and only play example, the quantity of actual chips 20 and arrange and to determine according to actual conditions.
The fuse-wires structure of the technical program, fuse is located in the chip, the weld pad that connects fuse is on the Cutting Road between adjacent two chips on the wafer, can reduce the quantity of the weld pad in chip like this, help reducing chip area, thereby also just can increase on the wafer quantity of chip that can output, save cost.
The above only is specific embodiments of the invention; in order to make those skilled in the art better understand spirit of the present invention; yet protection scope of the present invention is not a limited range with the specific descriptions of this specific embodiment; any those skilled in the art is in the scope that does not break away from spirit of the present invention; can make an amendment specific embodiments of the invention, and not break away from protection scope of the present invention.
Claims (5)
1. a fuse-wires structure comprises fuse and the weld pad that is electrically connected with fuse, and described fuse is positioned at chip, and described chip is positioned on the wafer, it is characterized in that, described weld pad is at the Cutting Road between adjacent two chips on the wafer.
2. fuse-wires structure as claimed in claim 1 is characterized in that, described Cutting Road comprises first Cutting Road and second Cutting Road, and described first Cutting Road is vertical mutually with second Cutting Road;
Described weld pad is positioned at first Cutting Road and/or second Cutting Road.
3. fuse-wires structure as claimed in claim 1 or 2 is characterized in that described fuse and weld pad are electrically connected by lead, and described lead passes through the cutting position of adjacent two chips.
4. fuse-wires structure as claimed in claim 3 is characterized in that, described lead comprises first lead and second lead;
Described first lead is parallel with described second Cutting Road, described second lead is parallel with described first Cutting Road, one end of described first lead is electrically connected with fuse, one end of described second lead is electrically connected with described weld pad, and the link position of described first lead and described second lead is on the extended line of weld pad away from the edge of fuse.
5. fuse-wires structure as claimed in claim 3 is characterized in that, described lead is a metal wire.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011102135090A CN102244067A (en) | 2011-07-28 | 2011-07-28 | Fuse wire structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011102135090A CN102244067A (en) | 2011-07-28 | 2011-07-28 | Fuse wire structure |
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| CN102244067A true CN102244067A (en) | 2011-11-16 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN2011102135090A Pending CN102244067A (en) | 2011-07-28 | 2011-07-28 | Fuse wire structure |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103426848A (en) * | 2012-05-25 | 2013-12-04 | 北大方正集团有限公司 | Chip and manufacturing method thereof |
| CN104112730A (en) * | 2013-06-09 | 2014-10-22 | 广东美的制冷设备有限公司 | Intelligent power module and manufacturing method thereof |
| CN108598064A (en) * | 2018-05-09 | 2018-09-28 | 北京智芯微电子科技有限公司 | Connect the metal wire of conventional die and test special chip in wafer |
| US10491233B1 (en) | 2018-05-31 | 2019-11-26 | Shenzhen GOODIX Technology Co., Ltd. | SAR ADC having accurate split capacitor |
| CN113363240A (en) * | 2021-04-27 | 2021-09-07 | 北京智芯微电子科技有限公司 | Chip metal wire, manufacturing method thereof and wafer |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000040792A (en) * | 1998-07-22 | 2000-02-08 | Toshiba Corp | Semiconductor device |
| US6215169B1 (en) * | 1998-05-15 | 2001-04-10 | Nec Corporation | Semiconductor device with adhesive tape not overlapping an opening in the uppermost surface of the semiconductor element surface |
| TW550785B (en) * | 2002-07-25 | 2003-09-01 | Richtek Technology Corp | Manufacturing method of integrated circuit |
| CN1458678A (en) * | 2002-05-15 | 2003-11-26 | 三星电子株式会社 | Integrated circuit chip and wafer and its producing and detecting method |
| CN101174607A (en) * | 2006-11-03 | 2008-05-07 | 台湾积体电路制造股份有限公司 | Fuse structures and integrated circuit devices |
| CN101322244A (en) * | 2005-11-30 | 2008-12-10 | 国际商业机器公司 | Laser fuse structures for high power applications |
| CN101330066A (en) * | 2007-06-19 | 2008-12-24 | 佑华微电子股份有限公司 | Wafer structure for reducing occupation crystal particle volume and fine adjustment method thereof |
-
2011
- 2011-07-28 CN CN2011102135090A patent/CN102244067A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6215169B1 (en) * | 1998-05-15 | 2001-04-10 | Nec Corporation | Semiconductor device with adhesive tape not overlapping an opening in the uppermost surface of the semiconductor element surface |
| JP2000040792A (en) * | 1998-07-22 | 2000-02-08 | Toshiba Corp | Semiconductor device |
| CN1458678A (en) * | 2002-05-15 | 2003-11-26 | 三星电子株式会社 | Integrated circuit chip and wafer and its producing and detecting method |
| TW550785B (en) * | 2002-07-25 | 2003-09-01 | Richtek Technology Corp | Manufacturing method of integrated circuit |
| CN101322244A (en) * | 2005-11-30 | 2008-12-10 | 国际商业机器公司 | Laser fuse structures for high power applications |
| CN101174607A (en) * | 2006-11-03 | 2008-05-07 | 台湾积体电路制造股份有限公司 | Fuse structures and integrated circuit devices |
| CN101330066A (en) * | 2007-06-19 | 2008-12-24 | 佑华微电子股份有限公司 | Wafer structure for reducing occupation crystal particle volume and fine adjustment method thereof |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103426848A (en) * | 2012-05-25 | 2013-12-04 | 北大方正集团有限公司 | Chip and manufacturing method thereof |
| CN104112730A (en) * | 2013-06-09 | 2014-10-22 | 广东美的制冷设备有限公司 | Intelligent power module and manufacturing method thereof |
| CN108598064A (en) * | 2018-05-09 | 2018-09-28 | 北京智芯微电子科技有限公司 | Connect the metal wire of conventional die and test special chip in wafer |
| US10491233B1 (en) | 2018-05-31 | 2019-11-26 | Shenzhen GOODIX Technology Co., Ltd. | SAR ADC having accurate split capacitor |
| WO2019227874A1 (en) * | 2018-05-31 | 2019-12-05 | Shenzhen GOODIX Technology Co., Ltd. | Sar adc having accurate split capacitor |
| CN113363240A (en) * | 2021-04-27 | 2021-09-07 | 北京智芯微电子科技有限公司 | Chip metal wire, manufacturing method thereof and wafer |
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Application publication date: 20111116 |