CN102208973B - Data stream transmitting method and device - Google Patents
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Abstract
The invention discloses a data stream transmitting method comprising the steps of dividing every byte data holding time t into a bigit integral part X and a bigit decimal part Y, accumulating a numerical value of Y by an accumulator after one datum is sent out, and determining a clock interval of sending the next data according to the highest carry bit indentifier S accumulated by the accumulator. The invention also correspondingly discloses a data stream transmitting device. Through the invention, the decimal part can be maintained to control the data stream transmission when every byte data holding time is a nonnegative integer, thus the constant speed transmitting precision can be enhanced. Only one counter is needed in the invention, therefore, fewer resources on hardware are occupied.
Description
Technical field
The present invention relates to technical field of data transmission, relate in particular to a kind of method and apparatus of data stream transmitting.
Background technology
At present, synchronous transmission is applied more extensive in transfer of data, Fig. 1 is the principle schematic of Synchronous Transfer Mode, as shown in Figure 1, the interface signal of transmitting terminal and receiving terminal has clock, data are write and data-signal, data-signal can have many also can only have one, other signals only have one, all signals are all to be sent by transmitting terminal, synchronous transmission interface sequence as shown in Figure 2, receiving terminal is at the trailing edge sampled data write signal of each clock, if data are written as higher position and receive current data, in Fig. 2, data 1 and data 2 are valid data, other data are not valid data.
For some occasion, as flowing constant code rate (CBR), audio video transmission transmits, require transmission code stream according to specifying code check at the uniform velocity to transmit, for example, given clock frequency is 27MHz, and data wire is 8bit, and transmission code rate is the code stream of 1M byte/s, because clock is 27MHz, every 27 clock cycle of transmitting terminal send a byte data, just can at the uniform velocity transmit the code stream of 1M byte/s, and the code stream sequential of 1M byte/s as shown in Figure 3.
For any given code check, according to clock frequency, can calculate each byte data holding time, concrete as shown in formula (1):
T=clock frequency/code check (1)
Wherein, t represents each byte data holding time, take the clock cycle as unit, and code check is transmission rate, and because code check can be arbitrary value (but being necessarily less than clock frequency), the t therefore obtaining can be integer, can be also decimal.
Synchronous transmission requires transmission data in the transmission of integer clock cycle, but will reach the error between each data transmitting time and t that just requires that high accuracy at the uniform velocity transmits, is less than or equal to for 0.5 clock cycle.
For example, given clock frequency is 27MHz, and data wire is 8bit, and transmission code rate is the code stream of 4M byte/s, according to formula (1), t=clock frequency/code check=27M/4M=6.75.
The code stream sequential of 4M byte/s as shown in Figure 4, after supposing that transmission starts, in the clock cycle 6, send data 1, because the accurate transmitting time of data 2, data 3, data 4, data 5 should be respectively 12.75,19.5,26.25,33 clock cycle, so, in the clock cycle 13,20,26,33, send respectively data 2, data 3, data 4, data 5.The error that guarantees like this transmitting time was less than or equal to for 0.5 clock cycle, and other data are transmission in such a manner all.It should be noted that, in formula (1), because code check can be for being less than the arbitrary value of clock frequency, the t obtaining can be irregular decimal, is even circulating decimal.
Existing typical transmission means mainly contains two kinds:
Typical transmission means 1:
The high accuracy at the uniform velocity error of each data transmitting time of transmission requirement was less than or equal to for 0.5 clock cycle.Typical transmission means is first according to the code check of current setting and clock frequency computing formula (1), to obtain t, then calculate the time that each byte data sends, last round, as the transmitting time (clock) of these data, concrete as shown in formula (2):
time i＝INT(t*i+0.5) (2)
Wherein, time i represents the moment of i data of actual transmissions, take the clock cycle as unit, is integer, and i specifically represents data sequence number, general, and 0 is first data sequence number, and 1 is second data sequence number ..., n is n+1 data sequence number.
Because high accuracy is at the uniform velocity transmitted conventionally and is realized at FPGA/ASIC, and FPGA/ASIC is not suitable for calculating floating multiplication division arithmetic, therefore generally by DSP or CPU computing formula (1) and formula (2), obtain look-up table, the input of table is data sequence number i, be output as time i, then FPGA/ASIC tables look-up successively and obtains sending the data break clock cycle.
Typical transmission means 2:
By DSP or CPU computing formula (1), then result is transformed to the form of formula (3):
t＝N0*[(...((((1+1/N1)-1/N2)+1/N3)-1/N4)....)] (3)
Wherein, N0, N1, N2, N3... are integer, in formula, use enough minute several to guarantee enough precision, and these numbers are passed to FPGA/ASIC and use as controlling parameter.
Then in corresponding each parameter of FPGA/ASIC, generate a counter, the initial value of counter is designated as respectively N0-1, N1-1, N2-1, N3-1..., is respectively counter N0, counter N1, counter N2, counter N3.......
During work according to following steps work:
Step 1: transmission data 1 start counter N0 simultaneously, and each clock of counter N0 subtracts 1, send data 2 initialize of laying equal stress on when counter N0 reduces to 0, and unison counter N1 subtracts 1; When counter N0 reduces to 0, send data 3 initialize of laying equal stress on, unison counter N1 subtracts 1 more again.
Step 2: step 1 transmits that data are until counter N0 sum counter N1 reduces at 0 o'clock simultaneously below, and counter N0 keeps a clock, the heavy initialize of counter N1, unison counter N2 subtracts 1, then at next clock, sends data again, and the heavy initialize of counter N0.
Step 3: step 1, step 2 are transmitted below data until when counter N0, N1, N2 remember 0 simultaneously, counter N0 sends the data initialize of laying equal stress on, and counter N1, N2 be heavy initialize simultaneously, and unison counter N3 subtracts 1.
Step 4: step 1, step 2, step 3 are transmitted below data until when counter N0, N1, N2, N3 remember 0 simultaneously, counter N0 keeps a clock, counter N1, N2, the heavy initialize of N3, unison counter N4 subtracts 1, and then next clock sends data again, the counter N0 initialize of laying equal stress on.
Step 5: step 1, step 2, step 3, step 4 are transmitted below data until when counter N0, N1, N2, N3 remember 0 simultaneously, counter N0 sends the data initialize of laying equal stress on, counter N1, N2, N3, N4 be heavy initialize simultaneously, and unison counter N5 subtracts 1.
Until all counter N0, N1, N2, N3...... remember 0 simultaneously, initialize again then, and again perform step 1 to step 5.
Can find out, although typical transmission means 1 and typical transmission means 2 can realize at the uniform velocity transmission, but, typical transmission means 1 adopts the mode rounding up when calculating the time of each data transmission, can affect the at the uniform velocity precision of transmission, and typical transmission means 2 is being obtained after parameter by DSP or CPU computing formula (1), (3), FPGA/ASIC will generate more counter (number of counter is different along with the difference of transmission code rate), takies hardware resource more.
Summary of the invention
In view of this, main purpose of the present invention is to provide a kind of method and apparatus of data stream transmitting, can improve the at the uniform velocity precision of transmission, and it is less to take hardware resource.
For achieving the above object, technical scheme of the present invention is achieved in that
A method for data stream transmitting, comprising:
A, each byte data holding time t is divided into bigit part X and binary fraction part Y;
B, send data, accumulator accumulates once the numerical value of Y;
The highest order carry sign S of c, the cumulative rear accumulator of basis determines the clock interval that next data send, and sends next data according to described definite clock interval, returns to step b.
Before described step a, also comprise step: calculate each byte data holding time t, t=clock frequency/transmission rate.
It is 1 that the initial value of described accumulator is set to the highest-order bit, and all the other bits are 0.
After described basis is cumulative, the highest order carry sign S of accumulator determines that the clock interval that next data send is: after cumulative, the highest order carry of accumulator sign S is effective, determines that the clock interval that next data send is X; After cumulative, the highest order carry of accumulator sign S is invalid, determines that the clock interval that next data send is X-1.
A device for data stream transmitting, comprising: the first register, the second register, the 3rd register, gate, counter and accumulator; Wherein,
Described the first register, for the value of storing X-1, X is the bigit part of each byte data holding time;
Described the second register, for the value of storing X;
Described the 3rd register, for storing the value of Y, Y is the binary fraction part of each byte data holding time;
Described gate, for identifying gating the first register or the second register according to the highest order carry of accumulator;
Described counter, for before device is started working or when data write signal is effective, using the register value of gate gating as initial value, then each the clock cycle Counter Value when sending the free time subtracts 1, when the value of counter reduces to 0, the initial value of reloading, and export data write signal and cumulative latch signal;
Described accumulator, for when cumulative latch signal is effective, the value phase adduction of accumulator value and the 3rd register is latched as new accumulator value, the value of accumulator value and the 3rd register is added to the highest order carry producing simultaneously and is latched into highest order carry sign.
This device also comprises computing unit, for calculating each byte data holding time t, t=clock frequency/transmission rate.
Under initial condition, the highest order of described accumulator is 1, and all the other positions are 0.
Described gate according to highest order carry sign gating the first register or second register of accumulator is: the highest order carry of accumulator identifies when effective, gate gating the second register; The highest order carry of accumulator identifies when invalid, gate gating the first register.
The method and apparatus of data stream transmitting of the present invention, is divided into bigit part X and binary fraction part Y by each byte data holding time t; Data of every transmission, accumulator accumulates once the numerical value of Y, according to the highest order carry sign S of accumulator after cumulative, determines the clock interval that next data send.By the present invention, when each byte data holding time is non-integer, retains fractional part and carry out data stream transmitting control, thus can improve the at the uniform velocity precision of transmission, and the present invention only needs a counter, thus it is less to take hardware resource.
Accompanying drawing explanation
Fig. 1 is the principle schematic of Synchronous Transfer Mode;
Fig. 2 is synchronous transmission interface sequence schematic diagram;
Fig. 3 is the code stream sequential schematic diagram of 1M byte/s;
Fig. 4 is the code stream sequential schematic diagram of 4M byte/s;
Fig. 5 is the method flow schematic diagram of data stream transmitting of the present invention;
Fig. 6 is the apparatus structure schematic diagram of data stream transmitting of the present invention;
Fig. 7 is the embodiment of the present invention 1 signal sequence schematic diagram.
Embodiment
Basic thought of the present invention is: each byte data holding time t is divided into bigit part X and binary fraction part Y; Data of every transmission, accumulator accumulates once the numerical value of Y, according to the highest order carry sign S of accumulator after cumulative, determines the clock interval that next data send.
The data flow transmission method that the present invention proposes adopts Synchronous Transfer Mode, and message transmission rate is constant and can set, the method flow schematic diagram that Fig. 5 is data stream transmitting of the present invention, and as shown in Figure 5, the method comprises:
Step 501: calculate each byte data holding time t according to transmission rate and the clock frequency set.
High accuracy is at the uniform velocity transmitted mainly and is realized at FPGA/ASIC, can and set transmission rate according to clock frequency, by DSP or CPU computing formula (1), obtains each byte data holding time t, and the value of t be take the clock cycle as unit.
Step 502: t is divided into bigit part X and two parts of binary fraction part Y.
Suppose that the binary form that t is corresponding is shown: Xm.......X5 X4 X3 X2 X1.Y1 Y2 Y3Y4......Yn, be designated as X.Y, Xm ... .X5, X4, X3, X2, X1, Y1, Y2, Y3, Y4 ... Yn only gets 0 or 1, wherein Xm.......X5 X4 X3 X2 X1 represents that bigit is partly designated as X, and Y1 Y2 Y3 Y4......Yn represents that fractional part is designated as Y.
In addition Xm.......X5 X4 X3 X2 X1 is subtracted to 1 binary number obtaining and be designated as X-1.
X.Y has shown the accurate interval of each data, but because transmission data actual interval can only round numbers, so actual interval can only get X-1 or X, and X-1 has determined basic interval, and fractional part Y determines whether-1.
Step 503: send data, accumulator accumulates once the numerical value of Y, here, the figure place of accumulator is identical with the figure place of Y, and it is 1 that the initial value of accumulator is set to the highest-order bit, and all the other bits are 0.
Step 504: determine according to the highest order carry sign S of accumulator after cumulative the clock interval that next data send, and send next data according to described definite clock interval, return to step 503.The clock interval that next data send determines that mode is: if S is 0, the clock interval that next data send is X-1, if S is 1, the clock interval that next data send is X, wherein, S is that 1 expression highest order has carry, and S is 0 expression highest order no-carry.
Based on said method, can realize a hardware digital circuit at FPGA/ASIC, the present invention correspondingly proposes a kind of data stream transmitting device, and as shown in Figure 6, this device comprises structure: the first register, the second register, the 3rd register, gate, counter and accumulator; Wherein,
The first register, for the value of storing X-1, X is the bigit part of each byte data holding time;
The second register, for the value of storing X;
The 3rd register, for storing the value of Y, Y is the binary fraction part of each byte data holding time;
Gate, for according to highest order carry sign gating the first register or second register of accumulator, thereby makes counter using the value of register-stored of gating as initial value, concrete, and the highest order carry of accumulator identifies when effective, gating the second register; The highest order carry of accumulator identifies when invalid, gating the first register;
Counter, for before device is started working or when data write signal is effective, using the register value of gate gating as initial value, then each the clock cycle Counter Value when sending the free time subtracts 1, when the value of counter reduces to 0, the initial value of reloading, and export data write signal and cumulative latch signal, in other clock cycle data write signal and cumulative latch signal be set to invalid;
Accumulator, for when cumulative latch signal is effective, latchs the value phase adduction of accumulator value and the 3rd register as new accumulator value, the value of accumulator value and the 3rd register is added to the highest order carry producing simultaneously and is latched into highest order carry sign.Preferably, under initial condition, the highest order of accumulator is 1, and all the other positions are 0, accumulate once the value of the 3rd register after data of every transmission, and highest order carry sign is as the control end of gate, gating the first register or the second register.
This device can also comprise computing unit, for calculating each byte data holding time t, t=clock frequency/transmission rate.
Giving an example in corresponding step 502, the figure place of accumulator is n position, and the figure place of counter is m position, and the first register, the second register, the 3rd register are deposited respectively the value of X-1, X, Y, and figure place is respectively m, m, n position.Clock and the reset signal of circuit do not mark in the drawings.Highest order carry flag be the 3rd register and accumulator and at the highest order sign of carry whether.Work enables when invalid, and system is in wait state, and accumulator initial value highest order is that 1 other position is 0, and the value of counter is initial value.During work when rolling counters forward is to 0 time, the initial value of reloading, and send data write signal and cumulative latch signal, otherwise each clock cycle subtracts 1.Accumulator latchs the value phase adduction of accumulator value and the 3rd register as new accumulator value after cumulative latch signal is effective, the highest order carry of accumulator value (currency) and the 3rd register addition generation is latched into highest order carry flag simultaneously.
When circuit is from wait state enters into operating state, highest order carry flag initial value equals 0, afterwards, after cumulative latch signal is effective, latch the highest carry that accumulator initial value and the addition of the 3rd register produce, this highest order carry is controlled gate gating the first register or the second register, and counter loads the register value of gate gating as counter initial value.Counter loads after initial value, each clock count value subtracts 1, until count value is 0, again send data write signal and cumulative latch signal, the next clock cycle loads the register value of gate gating as counter initial value, general, if highest order carry flag is 1 (effectively), gating the second register is as the initial value next time of counter; Otherwise highest order carry flag is 0 (invalid), will gating the first register as the initial value next time of counter.This step constantly repeats, and just writes out the data of a byte when data write signal is effective, so just can realize and transmit accurately uniform rate data.
Below in conjunction with specific embodiment, technical scheme of the present invention is described in further detail.
The present embodiment supposes that given clock frequency is 27MHz, and data wire is 8bit, and transmission code rate is the code stream of 4.8M byte/s.Suppose the precision m=16 of integer part X, the precision n=16 of fractional part Y.
According to formula (1), calculate t=27M/4.8M=5.625;
Becoming binary system obtains:
X＝0b 0000_0000_0000_0101，Y＝0b 1010_0000_0000_0000
In formula, 0b represents binary number, and " _ " there is no particular meaning, just in order conveniently to check, as identical with 0b 0000000000000101 in 0b0000_0000_0000_0101.
For the ease of statement, the clock that wait state is entered into after operating state is numbered, and present clock period is designated as Clk0, and the 1st clock cycle is designated as Clk1 thereafter, and the 2nd clock cycle is designated as Clk1 .... i clock cycle is designated as Clki.
Under wait state:
Counter Value is 0b 0000_0000_0000_0000;
Accumulator value is 0b 1000_0000_0000_0000;
The first register value is 0b 0000_0000_0000_0100;
The 3rd register value is 0b 1010_0000_0000_0000;
The second register value is 0b 0000_0000_0000_0101;
At Clk0:
Because highest order carry flag initial value is 0, therefore the first register is strobed.Counter initial value is 0b0000_0000_0000_0100.Because Clk0 is the clock cycle that enters operating state, send cumulative latch signal again, but not send count signal.Accumulator latch cumulative sum 0b 0010_0000_0000_0000 and highest order carry flag 1, therefore the second register is strobed.
At Clk1:
Counter Value subtracts 1, accumulator latch cumulative sum 0b 0010_0000_0000_0000 and highest order carry flag 1, and therefore the second register is strobed.
At Clk2, Clk3:
Except Counter Value subtracts 1, other is constant.
At Clk4:
Counter Value is 0, sends data write signal and cumulative latch signal.Because highest order carry flag becomes 1 at Clk1, keep always, therefore the second register is strobed.
At Clk5:
Counter Value initialize 0b 0000_0000_0000_0101, data write signal and cumulative latch signal lost efficacy.Accumulator latch cumulative sum 0b 1100_0000_0000_0000 and highest order carry flag 0, therefore the first register is strobed.
Digital circuit repeats above-mentioned steps Clk1 to Clk5 and works, and signal sequence as shown in Figure 7.
The present embodiment supposes that given clock frequency is 27MHz, and data wire is 8bit, and transmission code rate is the code stream of 8.9M byte/s.Suppose the precision m=16 of integer part X, the precision n=16 of fractional part Y.
According to formula (1), calculate
t＝27M/8.9M＝3.0337078651685393258426966292135
Because integer is 3 and m=16,
So X=0b 0000_0000_0000_0011,
Because decimal is 0.0337078651685393258426966292135 and m=16
Therefore will be by little 16 bits that transfer to:
0.0337078651685393258426966292135*2
16＝2209.0786516853932584269662921348
Round up to such an extent that 2209 be converted into Binary Zero b 0000_1000_1010_0001
Y＝0b 0000_1000_1010_0001
According to X and Y, can obtain other parameter, before computational methods, illustrate, according to 2 clock cycle of interval at least between known each data of result of calculation, when accumulator has the highest carry during in data such as transmission the 9th, 25,41, can 3 clock cycle of interval while therefore transmitting these data.
The above, be only preferred embodiment of the present invention, is not intended to limit protection scope of the present invention.
Claims (3)
1. a device for data stream transmitting, is characterized in that, this device comprises: computing unit, the first register, the second register, the 3rd register, gate, counter and accumulator; Wherein,
Described computing unit, for calculating each byte data holding time t, t=clock frequency/transmission rate;
Described the first register, for the value of storing X-1, X is the bigit part of each byte data holding time;
Described the second register, for the value of storing X;
Described the 3rd register, for storing the value of Y, Y is the binary fraction part of each byte data holding time;
Described gate, for identifying gating the first register or the second register according to the highest order carry of accumulator;
Described counter, for before device is started working or when data write signal is effective, using the register value of gate gating as initial value, then each the clock cycle Counter Value when sending the free time subtracts 1, when the value of counter reduces to 0, the initial value of reloading, and export data write signal and cumulative latch signal;
Described accumulator, for when cumulative latch signal is effective, the value phase adduction of accumulator value and the 3rd register is latched as new accumulator value, the value of accumulator value and the 3rd register is added to the highest order carry producing simultaneously and is latched into highest order carry sign.
2. device according to claim 1, is characterized in that, under initial condition, the highest order of described accumulator is 1, and all the other positions are 0.
3. device according to claim 1, is characterized in that, described gate according to highest order carry sign gating the first register or second register of accumulator is: the highest order carry of accumulator identifies when effective, gate gating the second register; The highest order carry of accumulator identifies when invalid, gate gating the first register.
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| CN101783676A (en) * | 2009-12-29 | 2010-07-21 | 中兴通讯股份有限公司 | Method and device for clock division |
| CN101789781A (en) * | 2010-01-08 | 2010-07-28 | 盐城师范学院 | Realizing method of frequency divider with arbitrary value based on FPGA (Field Programmable Gate Array) |
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| CN101783676A (en) * | 2009-12-29 | 2010-07-21 | 中兴通讯股份有限公司 | Method and device for clock division |
| CN101789781A (en) * | 2010-01-08 | 2010-07-28 | 盐城师范学院 | Realizing method of frequency divider with arbitrary value based on FPGA (Field Programmable Gate Array) |
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Inventor after: Wang Wanting Inventor after: Xu Xin Inventor after: Shao Dongying Inventor after: Hu Daming Inventor after: Zheng Haiou Inventor after: Yu Tiange Inventor after: Late Voyager Inventor after: Wang Yanling Inventor before: Wang Wanting Inventor before: Xu Xin Inventor before: Shao Dongying Inventor before: Hu Daming Inventor before: Zheng Haiou Inventor before: Yu Tiange |
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