CN102194736B - Making method of semiconductor device - Google Patents
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- CN102194736B CN102194736B CN201010131820.6A CN201010131820A CN102194736B CN 102194736 B CN102194736 B CN 102194736B CN 201010131820 A CN201010131820 A CN 201010131820A CN 102194736 B CN102194736 B CN 102194736B
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Abstract
The invention discloses a making method of a semiconductor device, which comprises the steps of: a, sequentially forming a stop layer, a high-stress cover layer, a first dielectric layer, a second dielectric layer, a silicon-containing bottom anti-reflection coating and a photoetching glue layer with patterns on a front-end device layer; b, etching the silicon-containing bottom anti-reflection coating and the second dielectric layer by using the photoetching glue layer as a mask, exposing the upper surface of the first dielectric layer; c, carrying out dry-process etching on the first dielectric layer and the high-stress cover layer by using the silicon-containing bottom anti-reflection coating and the second dielectric layer as masks, and stopping at the stop layer; d, introducing reaction gases including fluorohydrocarbon gas and oxygen for removing silicon-containing residues; and e, stripping the second dielectric layer to form the semiconductor device. According to the method disclosed by the invention, the residues on the surface of the device subjected to contact hole or through hole etching can be effectively removed so that the surface of a wafer becomes flat, long-term reliability of the device is improved, and yield of the device is increased.
Description
Technical field
The present invention relates to process for fabrication of semiconductor device, particularly a kind of method that covers the residue of semiconductor device surface of removing after etching.
Background technology
Along with the live width of integrated circuit is constantly dwindled, the microminiaturization of semiconductor element has entered into deep-submicron and nano-scale, and the interval between the larger expression element of the density of the semiconductor element on one chip is also just less, this makes the making of contact hole and through hole more and more difficult.Especially when the live width of semiconductor element reaches the even less technology node of 65nm node, produce the opening as openings, particularly high-aspect-ratio (aspect ratio) such as contact hole, through hole and grooves, difficulty raises day by day.
Opening for high-aspect-ratio, focus on the depth of field (depth of focus in order to increase photoresist, DOF) margin, must shift pattern with very thin photoresist, but the thinner meeting of photoresist makes in etching process photoresist consumption serious, thereby cause the final pattern generation moderate finite deformation formed.The problem caused for fear of photoresist thickness deficiency usually replaces traditional photoresist mask technique by the tri-layer masking technology in etching technics.Figure 1A-1B is that prior art is used tri-layer masking to form the cutaway view of each step in the technological process of contact hole structure.At first, as shown in Figure 1A, provide a substrate 100 of having manufactured semiconductor device.Form stop-layer 101 in modes such as chemical vapour deposition (CVD)s on the surface of substrate 100.Form heavily stressed cover layer 102 on the surface of stop-layer 101, the material of this layer is silicon nitride.Form the first dielectric layer 103 on heavily stressed cover layer 102.Then, form the second dielectric layer 104 on the first dielectric layer 103.Form siliceous bottom antireflective coating 105 on the second dielectric layer 104.Then, apply the figuratum photoresist layer 106 of one deck tool on siliceous bottom antireflective coating 105.As shown in Figure 1B, take photoresist layer 106 as mask, adopt dry etching, siliceous bottom antireflective coating 105 and the second dielectric layer 104 are carried out to etching, expose the surface of the first dielectric layer 103.Then, the figuratum siliceous bottom antireflective coating 105 of the tool of take and the second dielectric layer 104 are mask, the first dielectric layer 103 and heavily stressed cover layer 102 are carried out to dry etching, and make etching stopping at stop-layer 101.Then, by stripping technology, remove the second dielectric layer 104, siliceous bottom antireflective coating 105 and photoresist layer 106, form contact hole.
But, be different from the technology of direct employing photoresist as mask, in order to form the hole with larger depth-to-width ratio, need to pass into the gas that can form number of polymers in the etching process of tri-layer masking technology, will introduce a large amount of small residues at device surface like this after etching technics completes.Fig. 2 is that prior art is used tri-layer masking to form the TEM plane graph of contact hole.As shown in Figure 2, the remained on surface at contact hole or through hole has many small residues.By the EDX energy spectrum, the composition of residue is analyzed, testing result shows that the main component of residue is Si and O, and size is less than 30nm.Owing to also wanting subsequently the deposit multilayer film, so these residues can make the wafer surface out-of-flatness that becomes.Further, the impact due to the mask aligner depth of focus in photoetching, make and can't make circuit pattern in wafer surface.In addition, the wafer surface out-of-flatness also can affect the long-term reliability of device, reduces yields.
So, need at present a kind of method that can effectively remove device surface residue after contact hole or via etch, in order to make wafer surface become smooth, and improve long-term reliability and the yields of device.
Summary of the invention
Introduced the concept of a series of reduced forms in the summary of the invention part, this will further describe in the embodiment part.Summary of the invention part of the present invention does not also mean that key feature and the essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range of attempting to determine technical scheme required for protection.
The present invention proposes a kind of method of making semiconductor device, and described method comprises the following steps: a) to form successively on the front end device layer stop-layer, heavily stressed cover layer, the first dielectric layer, the second dielectric layer, siliceous bottom antireflective coating and is with figuratum photoresist layer; B) using described photoresist layer as mask, the described siliceous bottom antireflective coating of etching and described the second dielectric layer, expose the upper surface of described the first dielectric layer; C) take described siliceous bottom antireflective coating and described the second dielectric layer is mask, the first dielectric layer and heavily stressed cover layer is carried out to dry etching, and stop at described stop-layer; D) pass into the reacting gas that comprises the fluorohydrocarbon G&O, to remove siliceous residue; And e) described the second dielectric layer is peeled off, formed semiconductor device.
According to an aspect of the present invention, it is characterized in that, described fluorohydrocarbon gas is that the carbon fluorine is than the perfluor fluorohydrocarbon gas (C that is more than or equal to 0.5
xf
y, x>3) at least one.
According to an aspect of the present invention, it is characterized in that, described fluorohydrocarbon gas is selected from C
4f
8, C
4f
6or C
5f
6.
According to an aspect of the present invention, it is characterized in that, described fluorohydrocarbon gas is C
4f
8.
According to an aspect of the present invention, it is characterized in that, the flow velocity of described fluorohydrocarbon gas is 5-20sccm, and the flow velocity of described oxygen is 20-100sccm.
According to an aspect of the present invention, it is characterized in that, the air pressure in described d step in reaction chamber is the 100-500 millitorr.
According to an aspect of the present invention, it is characterized in that, in described d step, do not apply bias voltage.
According to an aspect of the present invention, it is characterized in that, in described d step, the time that passes into of gas is 5-50 second.
The method according to this invention can effectively be removed device surface residue after contact hole or via etch, makes wafer surface become smooth, and improves long-term reliability and the yields of device.
The accompanying drawing explanation
Following accompanying drawing of the present invention is used for understanding the present invention in this as a part of the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.In the accompanying drawings,
Figure 1A-1B is that prior art is used tri-layer masking to form the cutaway view of each step in the technological process of contact hole structure;
Fig. 2 is that prior art is used tri-layer masking to form the TEM plane graph of contact hole;
Fig. 3 A-3E is the cutaway view according to each step in the fabrication processing of the inventive method making contact hole;
Fig. 4 is the TEM plane graph according to the contact hole of the inventive method formation;
Fig. 5 is the TEM cutaway view according to the contact hole of prior art and method of the present invention formation;
Fig. 6 A-6E is the cutaway view according to each step in the fabrication processing of the inventive method making through hole;
Fig. 7 makes the flow chart of the manufacturing process of contact hole/through hole according to the embodiment of the present invention.
Embodiment
In the following description, a large amount of concrete details have been provided in order to more thorough understanding of the invention is provided.Yet, it will be apparent to one skilled in the art that the present invention can be implemented without one or more these details.In other example, for fear of obscuring with the present invention, for technical characterictics more well known in the art, be not described.
In order thoroughly to understand the present invention, detailed step will be proposed in following description, so that how explanation the present invention removes contact hole/via etch afterwards at the residue of device surface.Obviously, execution of the present invention is not limited to the specific details that the technical staff of semiconductor applications has the knack of.Preferred embodiment of the present invention is described in detail as follows, yet, except these are described in detail, the present invention can also have other execution modes.
In order to overcome in prior art the problems referred to above of utilizing tri-layer masking fabrication techniques contact hole/through hole to bring, the present invention proposes a kind of technique that passes into fluoro-gas after contact hole/via etch and before mask is peeled off, remove the residue of device surface, so that wafer surface is smooth, and long-term reliability and the yields of raising device.With reference to Fig. 3 A to Fig. 3 E, the cutaway view according to each step in the fabrication processing of the inventive method making contact hole is shown.
At first, as shown in Figure 3A, one substrate 300 of having manufactured semiconductor device is provided, wherein substrate 300 can include but not limited to following mentioned material, silicon for example, silicon-on-insulator (siliconon insulator, SOI), (the stacked silicon on insulator of stacked silicon on insulator, SSOI), (the stacked SiGe on insulator of stacked SiGe on insulator, S-SiGeOI), germanium on insulator SiClx (SiGe on insulator, SiGeOI) and germanium on insulator (Ge on insulator, GeOI) at least one material in.Form stop-layer 301 in modes such as chemical vapour deposition (CVD)s on the surface of substrate 300, stop-layer 301 can be Ni doped Si layer, can be doping platinum (Pt) particularly.Form heavily stressed cover layer 302 on the surface of stop-layer 301, the material of this layer can be silicon nitride.Form the first dielectric layer 303 with chemical vapour deposition technique (CVD) or method of spin coating (SOC) on heavily stressed cover layer 302.The material of the first dielectric layer 303 can be doped silicon glass, silicon dioxide or advanced low-k materials etc.This layer plays the purposes of insulation, the metal interconnecting layer that is used for isolating device and forms afterwards.Then, form the second dielectric layer 304 on the first dielectric layer 303, the thickness of this layer is about the 2000-4000 dust, and material can be organic dielectric materials.Form siliceous bottom antireflective coating 305 on the second dielectric layer 304, its material is siliceous organic high molecular polymer or poly-silicon thing, and thickness is about the 500-1000 dust.This layer has good antireflection ability.Then, apply the figuratum photoresist layer 306 of one deck tool on siliceous bottom antireflective coating 305.The thickness of photoresist layer 306 is about the 1000-3000 dust.
As shown in Figure 3 B, take photoresist layer 306 as mask, adopt dry etching, siliceous bottom antireflective coating 305 and the second dielectric layer 304 are carried out to etching, the upper surface that exposes the first dielectric layer 303, with the design transfer by photoresist layer 306 to siliceous bottom antireflective coating 305 and the second dielectric layer 304.Because the contact hole size formed is less, the photoresist of coating is thinner, and therefore in the process of above-mentioned transfer pattern, photoresist layer 306 has been consumed totally substantially.
As shown in Figure 3 C, the figuratum siliceous bottom antireflective coating 305 of the tool of take and the second dielectric layer 304 are mask, the first dielectric layer 303 and heavily stressed cover layer 302 are carried out to dry etching, and make etching stopping in stop-layer 301, thereby complete the etching of contact hole.According to embodiments of the invention, the etching gas used in above-mentioned dry etch process at least comprises fluorohydrocarbon gas, for example, and CF
4, C
2f
6, C
4f
8deng, and oxygen.In addition, can also pass into the argon gas that plays diluting effect and bombardment effect.The flow velocity of fluorohydrocarbon gas can be 50-500sccm, and the flow velocity of oxygen can be 5-50sccm, and the flow velocity of argon gas can be 100-500sccm, and wherein, sccm is under standard state, namely 1 cubic centimetre of (1cm per minute under 1 atmospheric pressure, 25 degrees centigrade
3/ min) flow.Etching forms in the process of contact hole, and siliceous bottom antireflective coating 305 also is consumed, but can leave residue containing silicon at device surface, and these residues can't remove by stripping technology.
As shown in Figure 3 D, pass into the reacting gas that comprises the fluorohydrocarbon G&O, to remove siliceous residue.Wherein, fluorohydrocarbon gas is that the carbon fluorine is than the perfluor fluorohydrocarbon gas (C that is more than or equal to 0.5
xf
y, x>3), C for example
4f
8, C
4f
6or C
5f
6deng at least one.Fluorohydrocarbon can react with siliceous residue and generate SiF
4gas is taken away by air pump.Yet, because the higher fluorohydrocarbon gas of phosphorus content can form the polymer that stops etching to be carried out, oxygen is peeled off effect to these polymer, therefore need pass into oxygen to increase reaction rate.In this step, for fear of the loss to stop-layer 301, the reaction chamber domestic demand keeps higher air pressure, and does not apply bias voltage, and wherein the air pressure in reaction chamber need remain on the 100-500 millitorr.According to a preferred embodiment of the present invention, pass into C
4f
8the experiment condition of gas is as follows: air pressure is about the 100-300 millitorr, is more preferably 200 millitorrs; C
4f
8the flow velocity of gas is about 5-20sccm, is preferably 10sccm; The flow velocity of oxygen is about 20-100sccm, is preferably 50sccm.The time that passes into of fluorohydrocarbon G&O is 5-50 second, and the preferred time is 10 seconds.
As shown in Fig. 3 E, the second dielectric layer 304 is peeled off, form contact hole.
As shown in Figure 4, be the TEM plane graph of the contact hole that forms according to the inventive method.With Fig. 2, compare, the device surface that the method according to this invention forms is smooth, and there is no residue.Fig. 5 is the TEM cutaway view according to the contact hole of prior art and method of the present invention formation.From photo, can measure, after two kinds of methods form contact hole, contact hole all enters into following approximately 115 dust places, stop-layer surface.Although the present invention has increased the step that passes into of fluorohydrocarbon G&O, etching stop layer is not impacted, therefore can the conductive region be connected with contact hole on substrate not impacted.
The method according to this invention can also be used to remove in the process that adopts the tri-layer masking technology to form through hole and remains in surperficial residue containing silicon.With reference to Fig. 6 A to Fig. 6 E, the cutaway view according to each step in the fabrication processing of the inventive method making through hole is shown.
At first, as shown in Figure 6A, at the front end device layer 600 of having manufactured semiconductor device, in modes such as chemical vapour deposition (CVD)s, form stop-layer 601, stop-layer 601 can be Ni doped Si layer, can be doping platinum (Pt) particularly.Form heavily stressed cover layer 602 on the surface of stop-layer 601, the material of this layer can be silicon nitride.Form the first dielectric layer 603 with chemical vapour deposition technique (CVD) or method of spin coating (SOC) on heavily stressed cover layer 602, wherein the first dielectric layer 603 is for example doped silicon glass, silicon dioxide or advanced low-k materials etc.This layer plays the purposes of insulation, the metal interconnecting layer that is used for isolating device and forms afterwards.Then, form the second dielectric layer 604 on the first dielectric layer 603, the thickness of this layer is about the 2000-4000 dust, and material can be organic dielectric materials.Form siliceous bottom antireflective coating 605 on the second dielectric layer 604, its material is siliceous organic high molecular polymer or poly-silicon thing, and thickness is about the 500-1000 dust.This layer has good antireflection ability.Then, apply the figuratum photoresist layer 606 of one deck tool on siliceous bottom antireflective coating 605.The thickness of photoresist layer 606 is about the 1000-3000 dust.
As shown in Figure 6B, take photoresist layer 606 as mask, adopt dry etching, siliceous bottom antireflective coating 605 and the second dielectric layer 604 are carried out to etching, the upper surface that exposes the first dielectric layer 603, with the design transfer by photoresist layer 606 to siliceous bottom antireflective coating 605 and the second dielectric layer 604.Because the contact hole size formed is less, the photoresist of coating is thinner, and therefore in the process of above-mentioned transfer pattern, photoresist layer 606 has been consumed totally substantially.
As shown in Figure 6 C, the figuratum siliceous bottom antireflective coating 605 of the tool of take and the second dielectric layer 604 are mask, the first dielectric layer 603 and heavily stressed cover layer 602 are carried out to dry etching, and make etching stopping in stop-layer 601, thereby complete the etching of contact hole.According to embodiments of the invention, the etching gas used in above-mentioned dry etch process at least comprises fluorohydrocarbon gas, for example, and CF
4, C
2f
6, C
4f
8deng, and oxygen.In addition, can also pass into the argon gas that plays diluting effect and bombardment effect.The flow velocity of fluorohydrocarbon gas can be 50-500sccm, and the flow velocity of oxygen can be 5-50sccm, and the flow velocity of argon gas can be 100-500sccm.Etching forms in the process of contact hole, and siliceous bottom antireflective coating 605 also is consumed, but can leave residue containing silicon at device surface, and these residues can't remove by stripping technology.
As shown in Figure 6 D, pass into the reacting gas that comprises the fluorohydrocarbon G&O, to remove siliceous residue.Wherein, fluorohydrocarbon gas is that the carbon fluorine is than the perfluor fluorohydrocarbon gas (C that is more than or equal to 0.5
xf
y, x>3), C for example
4f
8, C
4f
6or C
5f
6deng at least one.Fluorine in fluorohydrocarbon can react with siliceous residue and generate SiF
4gas is taken away by air pump.Yet the fluorohydrocarbon gas that phosphorus content is higher can form the polymer that stops etching to be carried out, oxygen is peeled off effect to these polymer, therefore need pass into oxygen to increase reaction rate.In this step, for fear of the loss to stop-layer 301, the reaction chamber domestic demand keeps higher air pressure, and does not apply bias voltage, and wherein the air pressure in reaction chamber need remain on the 100-500 millitorr.According to a preferred embodiment of the present invention, pass into C
4f
8the experiment condition of gas is as follows: air pressure is about the 100-300 millitorr, is more preferably 200 millitorrs; C
4f
8the flow velocity of gas is about 5-20sccm, is preferably 10sccm; The flow velocity of oxygen is about 20-100sccm, is preferably 50sccm.The time that passes into of fluorohydrocarbon G&O is 5-50 second, and the preferred time is 10 seconds.
As shown in Fig. 6 E, the second dielectric layer 604 is peeled off, form contact hole.
The method according to this invention is by passing into the perfluor fluorohydrocarbon gas (C that phosphorus content is higher
xf
y, x>3) and oxygen, remove the residue containing silicon existed at device surface after etching completes.Therefore, the present invention can be applied to the process for fabrication of semiconductor device of any removal surface residue containing silicon.
The flow chart of Fig. 7 shows the manufacturing process of making contact hole/through hole according to the embodiment of the present invention.In step 701, form stop-layer having manufactured the substrate of semiconductor device/front end device layer.Form heavily stressed cover layer on the surface of stop-layer, the material of this layer can be silicon nitride.Form the first dielectric layer on heavily stressed cover layer.This layer plays the purposes of insulation, the metal interconnecting layer that is used for isolating device and forms afterwards.Then, form the second dielectric layer on the first dielectric layer, the material of this layer can be organic dielectric materials.Form siliceous bottom antireflective coating on the second dielectric layer.Then, apply the figuratum photoresist layer of one deck tool on siliceous bottom antireflective coating.In step 702, take photoresist layer as mask, siliceous bottom antireflective coating and the second dielectric layer are carried out to etching, expose the upper surface of the second dielectric layer.In step 703, the figuratum siliceous bottom antireflective coating of the tool of take and the second dielectric layer are mask, the first dielectric layer and heavily stressed cover layer are carried out to etching, and make etching stopping at stop-layer, thereby complete the etching of contact hole/through hole.In step 704, pass into the reacting gas that comprises the fluorohydrocarbon G&O, to remove siliceous residue.Wherein, fluorohydrocarbon gas is that the carbon fluorine is than the perfluor fluorohydrocarbon gas (C that is more than or equal to 0.5
xf
y, x>3), C for example
4f
8, C
4f
6or C
5f
6deng at least one.The reaction chamber domestic demand keeps higher air pressure, and does not apply bias voltage, and to prevent the loss of stop-layer, wherein air pressure need remain on the 100-500 millitorr.In step 705, the second dielectric layer is peeled off, form contact hole/through hole.
Have according to the semiconductor device of the contact hole/through hole of embodiment manufacture as above and can be applicable in multiple integrated circuit (IC).According to IC of the present invention, be for example memory circuitry, as random access memory (RAM), dynamic ram (DRAM), synchronous dram (SDRAM), static RAM (SRAM) (SRAM) or read-only memory (ROM) etc.According to IC of the present invention, can also be logical device, as programmable logic array (PLA), application-specific integrated circuit (ASIC) (ASIC), combination type DRAM logical integrated circuit (buried type DRAM) or other circuit devcies arbitrarily.IC chip according to the present invention can be used for for example consumer electronic products, in the various electronic products such as personal computer, portable computer, game machine, cellular phone, personal digital assistant, video camera, digital camera, mobile phone, especially in radio frequency products.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment is the purpose for giving an example and illustrating just, but not is intended to the present invention is limited in described scope of embodiments.It will be appreciated by persons skilled in the art that in addition the present invention is not limited to above-described embodiment, according to instruction of the present invention, can also make more kinds of variants and modifications, these variants and modifications all drop in the present invention's scope required for protection.Protection scope of the present invention is defined by the appended claims and equivalent scope thereof.
Claims (8)
1. the manufacture method of a semiconductor device, described method comprises the following steps:
A) form successively stop-layer, heavily stressed cover layer, the first dielectric layer, the second dielectric layer, siliceous bottom antireflective coating on the front end device layer and be with figuratum photoresist layer;
B) using described photoresist layer as mask, the described siliceous bottom antireflective coating of etching and described the second dielectric layer, expose the upper surface of described the first dielectric layer;
C) take described siliceous bottom antireflective coating and described the second dielectric layer is mask, the first dielectric layer and heavily stressed cover layer is carried out to dry etching, and stop at described stop-layer;
D) pass into the reacting gas that comprises the fluorohydrocarbon G&O, to remove siliceous residue; And
E) described the second dielectric layer is peeled off, formed semiconductor device.
2. the method for claim 1, is characterized in that, described fluorohydrocarbon gas is that the carbon fluorine is than the perfluor fluorohydrocarbon gas C that is more than or equal to 0.5
xf
yin at least one, and described perfluor fluorohydrocarbon gas C
xf
yin, x ﹥ 3.
3. method as claimed in claim 2, is characterized in that, described fluorohydrocarbon gas is selected from C
4f
8, C
4f
6or C
5f
6.
4. method as claimed in claim 3, is characterized in that, described fluorohydrocarbon gas is C
4f
8.
5. the method for claim 1, is characterized in that, the flow velocity of described fluorohydrocarbon gas is 5-20sccm, and the flow velocity of described oxygen is 20-100sccm.
6. the method for claim 1, is characterized in that, the air pressure in described d step in reaction chamber is the 100-500 millitorr.
7. the method for claim 1, is characterized in that, in described d step, do not apply bias voltage.
8. the method for claim 1, is characterized in that, in described d step, the time that passes into of gas is 5-50 second.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1445838A (en) * | 2002-03-19 | 2003-10-01 | 株式会社日立制作所 | Semiconductor device and manufacturing method thereof |
| CN1647263A (en) * | 2002-04-02 | 2005-07-27 | 陶氏环球技术公司 | Tri-layer masking architecture for patterning dual damascene interconnects |
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2010
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1445838A (en) * | 2002-03-19 | 2003-10-01 | 株式会社日立制作所 | Semiconductor device and manufacturing method thereof |
| CN1647263A (en) * | 2002-04-02 | 2005-07-27 | 陶氏环球技术公司 | Tri-layer masking architecture for patterning dual damascene interconnects |
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