CN102157497B - The structure of the semiconductor device of Multilayer stack and formation method - Google Patents
The structure of the semiconductor device of Multilayer stack and formation method Download PDFInfo
- Publication number
- CN102157497B CN102157497B CN201110028185.3A CN201110028185A CN102157497B CN 102157497 B CN102157497 B CN 102157497B CN 201110028185 A CN201110028185 A CN 201110028185A CN 102157497 B CN102157497 B CN 102157497B
- Authority
- CN
- China
- Prior art keywords
- semiconductor device
- mark layer
- epitaxial loayer
- multilayer stack
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Abstract
A structure for the semiconductor device of Multilayer stack, comprising: substrate, has marking structure in described substrate; Be positioned at least two-layer epitaxial loayer replaced and at least three layers of mark layer of described substrate surface, described mark layer is germanium silicon, and described mark layer covers described epitaxial loayer.The present invention increases one deck germanium-silicon thin membrane as mark layer between adjacent two epitaxial loayers, because the diffusion rate of germanium in silicon is less, therefore formed germanium silicon mark layer has cross section clearly, adopt the structure of the semiconductor device of Multilayer stack of the present invention to detect the crystal orientation of epitaxial loayer, result is more accurate, improves the positional precision that in semiconductor technology, photoetching or P body inject.Further, if the present invention adopts the method directly forming mark layer in described epi-layer surface, then without the need to cleaning this surface, can form next epitaxial loayer, the formation process of the semiconductor device of described Multilayer stack is simple.
Description
Technical field
The present invention relates to semiconductor applications, particularly relate to a kind of structure and formation method of semiconductor device of Multilayer stack.
Background technology
In order to improve the performance of bipolar device and integrated circuit, usually need at the one or more epitaxial loayer of silicon substrate surface deposit.Before special P body injection process in superjunction technology, need first to put signs in initial epitaxial layer, then carry out alignment mark through multiple epitaxial loayers that described initial epitaxial layer is supreme.
And due to when making epitaxial loayer, because the monocrystalline silicon in described epitaxial loayer has epitaxial characteristic, and the crystal orientation of monocrystalline silicon growing is relevant with technique, if technique is correct, so monocrystalline silicon will grow along correct direction; If technique is incorrect, so monocrystalline silicon just can not grow along correct crystal orientation.But because the material of each epitaxial loayer is identical, therefore judging whether described epitaxial loayer just has difficulties along the growth of correct crystal orientation, if and the monocrystalline silicon in epitaxial loayer does not grow along correct crystal orientation, so for there is the semiconductor device of Multilayer stack structure, accurately judge photoetching position or in superjunction technology time accurately judge that the position that P body injects has difficulties.
Fig. 1 is the position aligning method schematic diagram of the semiconductor device of prior art Multilayer stack.Please refer to Fig. 1, silicon base 101 is provided, form the initial epitaxial layer 103 covering described silicon base 101, in described initial epitaxial layer 103, be formed with marking structure 113, position alignment when described marking structure 113 injects for photoetching or P body.Described initial epitaxial layer 103 surface is formed with the first epitaxial loayer 105, second epitaxial loayer 107, the 3rd epitaxial loayer 109, the 4th epitaxial loayer 111 successively.If described epitaxial loayer 103,105,107,109,111 does not grow along correct crystal orientation, so error will be there is when judging the position of described marking structure 113, please refer to as shown in Figure 1, may occur when judging thinking that described marking structure 113 is positioned at the situation of 115 or other positions.Thus there is deviation in the position causing photoetching or P body to inject, affects the performance of the semiconductor device of described Multilayer stack structure.
For detecting the structure of the semiconductor device of the Multilayer stack in crystal orientation in prior art, be typically employed in arsenic doped in each epitaxial loayer, and under certain process conditions, form the method for the mark layer containing arsenic silicon, judge whether epitaxial loayer grows along correct crystal orientation.But because the arsenic in mark layer easily spreads in epitaxial loayer, be unfavorable for observing crystal orientation, the position at the actual place of mark is observed in impact, thus the positional precision causing photoetching or P body to inject is poor.And after arsenic doped forms mark layer, need to clean this surface, then form next epitaxial loayer, complex process.
Summary of the invention
The problem that the present invention solves there is provided a kind of structure and formation method of semiconductor device of Multilayer stack, utilizes the semiconductor device of Multilayer stack of the present invention to detect crystal orientation, avoids the problem of the poor accuracy judging mark position.
For solving the problem, the invention provides a kind of structure of semiconductor device of Multilayer stack, comprising:
Substrate, has marking structure in described substrate;
Be positioned at least two-layer epitaxial loayer replaced and at least three layers of mark layer of described substrate surface, and described mark layer is germanium silicon.
Alternatively, the material of described epitaxial loayer is silicon.
Alternatively, in described mark layer, the content of germanium is 7% ~ 12%.
The invention provides a kind of formation method of semiconductor device of Multilayer stack, comprising:
Substrate is provided, in described substrate, is formed with marking structure;
Alternately form at least two-layer epitaxial loayer and at least three layers of mark layer successively at described substrate surface, and described mark layer is germanium silicon.
Alternatively, the formation process of described mark layer is ion implantation.
Alternatively, the ion of described ion implantation is germanium ion.
Alternatively, the formation process of described mark layer is chemical vapour deposition (CVD).
Alternatively, the depositing temperature of described chemical vapor deposition method is 600 ~ 800 DEG C, and pressure is 2666Pa ~ 5333Pa, and thickness is 40nm ~ 80nm, and the retention time is 40 ~ 60s.
Alternatively, in described mark layer, the content of germanium is 7% ~ 12%.
Alternatively, the formation process cutting described semiconductor device described in open is chemical etching.
Compared with prior art, the present invention has the following advantages:
The invention provides a kind of structure and formation method of semiconductor device of Multilayer stack, one deck germanium-silicon thin membrane is increased as mark layer between adjacent two epitaxial loayers, because the diffusion rate of germanium in silicon is less, therefore formed mark layer germanium silicon has cross section clearly, adopt the structure of the semiconductor device of Multilayer stack of the present invention to detect the crystal orientation of epitaxial loayer, result is more accurate, improves the positional precision that in semiconductor technology, photoetching or P body inject.
Further, if the present invention adopts the method directly forming mark layer in described epi-layer surface, then without the need to cleaning this surface, can form next epitaxial loayer, the formation process of the semiconductor device of described Multilayer stack is simple.
Accompanying drawing explanation
Fig. 1 is the position aligning method of the semiconductor device of prior art Multilayer stack;
Fig. 2 is the cross-sectional view of the semiconductor device of the Multilayer stack of one embodiment of the invention;
Fig. 3 is the schematic flow sheet of the formation method of the semiconductor device of the Multilayer stack of one embodiment of the invention;
Fig. 4 ~ Fig. 5 is the cross-sectional view of the formation method of the semiconductor device of Multilayer stack in one embodiment of the invention;
Fig. 6 is the cross-sectional view of the semiconductor device of Multilayer stack in one embodiment of the invention;
Fig. 7 is the microstructure schematic diagram of the semiconductor device of Multilayer stack in one embodiment of the invention;
Fig. 8 is the cross-sectional view of the semiconductor device of Multilayer stack in another embodiment of the present invention.
Embodiment
For enabling above-mentioned purpose of the present invention, feature and advantage become apparent more, are described in detail the specific embodiment of the present invention below in conjunction with accompanying drawing.
Set forth a lot of detail in the following description so that fully understand the present invention, but the present invention can also adopt other to be different from alternate manner described here to implement, therefore the present invention is not by the restriction of following public specific embodiment.
Just as described in the background section, the semiconductor device of the Multilayer stack of prior art forms arsenic silicon thin film as mark layer for adopting in arsenic doped to described epitaxial loayer, because the diffusion rate of arsenic in silicon is higher, the profile of the mark layer therefore formed is not clearly, adopt the semiconductor device of this kind of Multilayer stack not high to the accuracy detecting crystal orientation, and complex process, this kind of method existing problems.
For the problems referred to above, the present inventor finds after deliberation, the diffusion rate of germanium in silicon is less, germanium-silicon thin membrane substitute for arsenic silicon thin film can be adopted as mark layer to manufacture the semiconductor device of Multilayer stack, the clear-cut of described mark layer, it is more accurate with described mark layer to be that the semiconductor device of the Multilayer stack of germanium-silicon thin membrane detects crystal orientation, and the formation process of the semiconductor device of described Multilayer stack is simple.
The invention provides a kind of structure of semiconductor device of Multilayer stack, comprising:
Substrate, has marking structure in described substrate;
Be positioned at least two-layer epitaxial loayer replaced and at least three layers of mark layer of described substrate surface, it is characterized in that, described mark layer is germanium silicon.
Wherein, the material of described epitaxial loayer is silicon; In described mark layer, the content of germanium is 7% ~ 12%.
In the specific embodiment of the invention, described epitaxial loayer is preferably three layers, and described mark layer is preferably three layers.
Fig. 2 is the profile of the semiconductor device of the Multilayer stack of the specific embodiment of the invention.Please refer to Fig. 2, the structure of the semiconductor device of the Multilayer stack of the specific embodiment of the invention comprises:
Substrate 201, has marking structure 20 in described substrate 201;
Be positioned at first epitaxial loayer 203 on described substrate 201 surface;
Be positioned at first mark layer 205 on described first epitaxial loayer 203 surface;
Be positioned at second epitaxial loayer 207 on described first mark layer 205 surface;
Be positioned at second mark layer 209 on described second epitaxial loayer 207 surface;
Be positioned at the 3rd epitaxial loayer 211 on described second mark layer 209 surface;
Be positioned at the 3rd mark layer 213 on described 3rd epitaxial loayer 211 surface.
Wherein, described substrate 201 comprises substrate 21 and initial epitaxial layer 22, and described mark structure 20 is positioned at initial epitaxial layer 22.
The material of described first mark layer 205, second mark layer 209, the 3rd mark layer 213 is germanium-silicon thin membrane, and in described germanium-silicon thin membrane, the content of germanium is 7% ~ 12%.
The material of described first epitaxial loayer 203, second epitaxial loayer 207, the 3rd epitaxial loayer 211 is silicon.
The invention provides a kind of formation method of semiconductor device of layer stack, comprising:
Substrate is provided, in described substrate, is formed with marking structure;
Alternately form at least two-layer epitaxial loayer and at least three layers of mark layer successively at described substrate surface, and described mark layer is germanium silicon.
Wherein, described substrate comprises substrate and initial epitaxial layer, and described marking structure is formed in initial epitaxial layer.
The formation process of described mark layer is ion implantation, and the ion of described ion implantation is germanium ion; Or the formation process of described mark layer is chemical vapour deposition (CVD), the depositing temperature of described chemical vapor deposition method is 600 ~ 800 DEG C, and pressure is 2666Pa ~ 5333Pa, and thickness is 40nm ~ 80nm, and the retention time is 40 ~ 60s.
Further, in order to make the profile of described mark layer the most clear, in described mark layer, the content of germanium is 7% ~ 12%.
Fig. 3 is the flow chart of the formation method of the semiconductor device of the Multilayer stack of the specific embodiment of the invention.Please refer to Fig. 3, the formation method of the semiconductor device of Multilayer stack of the present invention, comprising:
Step S31, provides substrate, is formed with marking structure in described substrate;
Step S32, forms the first epitaxial loayer covering described substrate;
Step S33, form the first mark layer covering described first epitaxial loayer, described first mark layer is germanium silicon;
Step S34, forms the second epitaxial loayer covering described first mark layer;
Step S35, form the second mark layer covering described second epitaxial loayer, described second mark layer is germanium silicon;
Step S36, forms the 3rd epitaxial loayer covering described second mark layer;
Step S37, form the 3rd mark layer covering described 3rd epitaxial loayer, described 3rd mark layer is germanium silicon.
After execution of step S31 ~ S37, the semiconductor device of Multilayer stack of the present invention completes.
Fig. 4 to Fig. 5 shows the schematic diagram of the formation method of the semiconductor device of Multilayer stack in the specific embodiment of the invention.
Please refer to Fig. 4, perform step S31, substrate 301 is provided, in described substrate 301, is formed with marking structure 30.
In the specific embodiment of the invention, described substrate 301 comprises substrate 31 and initial epitaxial layer 32, and described marking structure 30 is formed in initial epitaxial layer 32.
The material of described substrate 31 is monocrystalline silicon.Can doped N-type or p type impurity in described substrate 31, with the industrial requirement of satisfied reality.In the specific embodiment of the invention, doped with N-type impurity in described substrate 31, such as: the pentads such as P, As, Sb.
The material of described initial epitaxial layer 32 is silicon, and the formation method of described initial epitaxial layer 32 is chemical vapour deposition (CVD).Adopt the method for etching to form marking structure 30 in initial epitaxial layer 32, described marking structure 30 detects for the crystal orientation in Subsequent semiconductor technique, or carries out alignment mark for the position injected photoetching or P body.
Please refer to Fig. 5, perform step S32 ~ step S37.Specific as follows:
After described substrate is provided, perform step S32, form the first epitaxial loayer 303 covering described substrate.
The material of described first epitaxial loayer 303 is silicon, the formation method of described first epitaxial loayer 303 is chemical vapour deposition (CVD) (chemicalvapordeposition, CVD), because the technique forming described first epitaxial loayer 303 is consistent with existing epitaxial loayer formation process, this is no longer going to repeat them.
In the present embodiment, in order to save time, the thickness of described first epitaxial loayer 303 is preferably 4 ~ 8 μm.
It should be noted that, after described first epitaxial loayer 303 is carried out, place in atmosphere if long-term, and do not carry out next step technique, silicon in so described first epitaxial loayer 303 will be oxidized, or the dust in air will drop on the surface of described first epitaxial loayer 303, affect it and clean, this exerts an adverse impact to next step operation.Therefore, form described first epitaxial loayer 303 and be less than two hours with the time difference forming the first mark layer 305.
Afterwards, perform step S33, form the first mark layer 305 covering described first epitaxial loayer, described first mark layer 305 is germanium silicon.
Described first mark layer 305 for thickness be the germanium-silicon thin membrane of 40nm ~ 80nm, the formation method of described germanium-silicon thin membrane has two kinds:
One is doped germanium in described first epitaxial loayer 303, and germanium combines with the silicon in described first epitaxial loayer 303 and forms germanium silicon, forms described first mark layer 305.If after doped germanium formation has the first mark layer 305 of germanium silicon in described first epitaxial loayer 303 by this kind of method, need to clean described first mark layer 305 surface, the second epitaxial loayer 309 could be formed.
Another kind is the method adopting chemical vapour deposition (CVD) (CVD), forms first mark layer 305 with germanium silicon on described first epitaxial loayer 303 surface.This kind of method is without the need to cleaning the first mark layer 305, and can carry out subsequent technique, formation process is simple.
In a particular embodiment of the present invention, for making the first mark layer more clear, and formation process is more simple, and preferably adopt second method, i.e. the method for chemical vapour deposition (CVD) (CVD) forms described first mark layer 305.
When forming described first mark layer 305, the design parameter of described chemical vapour deposition (CVD) (CVD) is preferably: depositing temperature is 600 ~ 800 DEG C, and pressure is 2666Pa ~ 5333Pa, and thickness is 40nm ~ 80nm, and the retention time is 40 ~ 60s.
Further, the mark layer formed for making germanium-silicon thin membrane is the most clear, and in described first mark layer, the content of germanium is preferably 7% ~ 12%.
Then, perform step S34, form the second epitaxial loayer 307 covering described first mark layer 305.
The material of described second epitaxial loayer 307 is silicon, and the formation method of described second epitaxial loayer 307 is chemical vapour deposition (CVD); The thickness of described second epitaxial loayer 307 is preferably 4 ~ 8 μm; Form described second epitaxial loayer 307 and be less than two hours with the time difference forming the second mark layer 309.Specifically please refer to the formation method of described first epitaxial loayer 303.
Then, perform step S35, form the second mark layer 309 covering described second epitaxial loayer 307, described second mark layer 309 is germanium silicon.
The formation method of described second mark layer 309 is ion implantation or chemical vapour deposition (CVD); In described second mark layer 309, the content of germanium is preferably 7% ~ 12%.Formation method and the parameter of described second mark layer 309 please refer to the first mark layer 305.
Then, perform step S36, form the 3rd epitaxial loayer 311 covering described second mark layer 309.
The material of described 3rd epitaxial loayer 311 is silicon, and the formation method of described 3rd epitaxial loayer 311 is chemical vapour deposition (CVD); The thickness of described 3rd epitaxial loayer 311 is preferably 4 ~ 8 μm; Form described 3rd epitaxial loayer 311 and be less than two hours with the time difference forming the second mark layer 309.Specifically please refer to the formation method of described first epitaxial loayer 303.
Finally, perform step S37, form the 3rd mark layer 313 covering described 3rd epitaxial loayer 311, described 3rd mark layer 313 is germanium silicon.
The formation method of described 3rd mark layer 313 is ion implantation or chemical vapour deposition (CVD); In described 3rd mark layer 313, the content of germanium is preferably 7% ~ 12%.Formation method and the parameter of described 3rd mark layer 313 please refer to the first mark layer 305.After the structure that formation first epitaxial loayer 303, second epitaxial loayer 307, the 3rd epitaxial loayer 311 and the first mark layer 305, second mark layer 309, second mark layer 313 are mutually overlapping, described in there is Multilayer stack structure semiconductor device complete.
Adopt the semiconductor device of the Multilayer stack structure made in the specific embodiment of the invention to detect crystal orientation, concrete grammar is shown in Fig. 6 to Fig. 7.
Please refer to Fig. 6, after the semiconductor device structure with Multilayer stack of the specific embodiment of the invention completes, along the semiconductor device cutting described Multilayer stack perpendicular to the direction of described semiconductor device substrates open, the cross section 400 of described semiconductor device had expose the cross section 50 of sub-cross section group 405,409,413 in described semiconductor layer and marking structure.
In a particular embodiment of the present invention, the formation process cutting described semiconductor device open is chemical etching.Described chemical etching adopts H
2o
2and HF.H
2o
2for being oxidized described semiconductor device place to be etched, generate oxide skin(coating) (not shown), HF is for removing described oxide skin(coating).Be specially: H
2o
2be oxidized described semiconductor device with speed faster, generate oxide skin(coating), afterwards, HF and described oxide skin(coating) react, and remove described oxide skin(coating).For making the semiconductor device cross section quality cut open good, described H
2o
21: 50 ~ 1: 70 are preferably with the ratio of HF.
Described sub-cross section group 405,409,413 is the cross section of multilayer mark layer (not shown).
Owing to adopting the method for chemical etching to cut described semiconductor device open, HF removes the oxide skin(coating) in the cross section of described semiconductor device, therefore, after described semiconductor device is cut open, can directly observe under scanning electron microscopy (SEM).Be specially: the cross section 400 of described semiconductor device is amplified to the enlargement ratio being suitable for observing sub-cross section group 405,409,413, observe the contour shape of described sub-cross section group 405,409,413.
It should be noted that, because in substrate 501, etching is formed with the cross section 50 of marking structure, therefore when follow-up formation epitaxial loayer and mark layer, also non-fully is smooth on the surface of described epitaxial loayer and mark layer, but there is the region of depression.The region of this depression is not easily observed under macroscopic conditions, only has when being amplified to suitable multiplying power under a scanning electron microscope and just can observe.
Please refer to Fig. 7, Fig. 7 is the schematic diagram of the present invention under scanning electron microscopy (SEM).
Under a scanning electron microscope, the region of caving in is there is in the sub-cross section group observed in the position corresponding with described mark layer, choose the minimum point in the region of described depression, and will different layers be positioned at according to mark layer and those minimum points perpendicular to the vicinity of the straight line on substrate 51 surface are attributed to one group.
Whether the more described minimum point often organized is located on a straight line, and whether the semiconductor device formed under judging these process conditions on this basis is easily accurately aimed at when follow-up photoetching or P body are injected.Be specially: if the minimum point often organized in described sub-cross section group 505,509,513 is positioned on straight line, then represent that epitaxial loayer 503,507,511 is along the growth of identical crystal orientation, the semiconductor device formed so is at the process conditions easier to accurate aligning in follow-up photoetching or P body injection time ratio; If the minimum point often organizing relevant position in described sub-cross section group 505,509,513 is not positioned on straight line, then represent that epitaxial loayer 503,507,511 is along the growth of different crystal orientation, the semiconductor device formed so is at the process conditions not easy accurate aligning when follow-up photoetching or P body are injected.
In the present embodiment, in the sub-cross section group 505,509,513 of described semiconductor device, the preferred two group minimum points corresponding with marking structure 50a and marking structure 50b compare.
In a particular embodiment of the present invention, more described minimum point concrete grammar whether located on a straight line is: choose two groups of minimum point A1 in described sub-cross section group 505,509,513, B1, C1 and A2, B2, C2, whether observation minimum point A1, B1, C1 and A2, B2, C2 lay respectively on straight line 515,517, for ease of observing and understanding, there is shown straight line 515,517.If minimum point A1, B1, C1 and A2, B2, C2 lay respectively on straight line 515,517, then represent that described epitaxial loayer 503,507,511 is along the growth of identical crystal orientation, the semiconductor device formed so is at the process conditions easier to accurate aligning in follow-up photoetching or P body injection time ratio; If minimum point A1, B1, C1 and A2, B2, C2 are not all positioned on straight line 515,517, then represent that described epitaxial loayer 503,507,511 is along the growth of different crystal orientation, the semiconductor device formed so is at the process conditions not easy accurate aligning when follow-up photoetching or P body are injected; If minimum point A1, B1, C1 are positioned on straight line 515, and A2, B2, C2 are not positioned on straight line 517, then the minimum point introducing other groups is again needed to compare.
In the present embodiment, the technique under preferred described straight line 515,517 and substrate 501 perpendicular condition, what formed under this technique has to carry out the positional precision that photoetching or P body inject high in the semiconductor device of Multilayer stack structure, and technique is simple.
It should be noted that, the semiconductor device formed under judging these process conditions when follow-up photoetching or P body are injected than the condition being easier to accurate aligning is: the minimum point that at least two groups are selected is located on a straight line.
After said process performs and terminates, the detection in the crystal orientation of the semiconductor device of Multilayer stack completes.
In another embodiment of the invention, three layers of mark layer and two-layer epitaxial loayer is alternately formed with at substrate surface.As shown in Figure 8, the first mark layer 603, first epitaxial loayer 605, second mark layer 607, second epitaxial loayer 609 and the 3rd mark layer 611 is formed with successively on described substrate 601 surface.
Wherein said substrate 601 comprises substrate 61 and initial epitaxial layer 62, and described marking structure 60 is formed in initial epitaxial layer 62.
The material of described first mark layer 603, second mark layer 607, the 3rd mark layer 611 is germanium silicon, and concrete formation method is ion implantation or chemical vapour deposition (CVD); In described first, second, third mark layer 603,607,611, the content of germanium is preferably 7% ~ 12%.
The material of described first epitaxial loayer 605, second epitaxial loayer 609 is silicon, and concrete formation method is chemical vapour deposition (CVD); The thickness of first, second epitaxial loayer 605,609 described is preferably 4 ~ 8 μm; Described first epitaxial loayer 605 is less than two hours with the time difference forming the second mark layer 607, and described second epitaxial loayer 609 is less than two hours with the time difference forming the 3rd mark layer 611.
Adopt the semiconductor device of the Multilayer stack structure of this embodiment to detect crystal orientation, also can judge whether the semiconductor device formed under these process conditions is easily accurately aimed at when follow-up photoetching or P body are injected, concrete grammar please refer to an embodiment, and this is no longer going to repeat them.
In sum, the invention provides structure of a kind of semiconductor device of Multilayer stack and forming method thereof, between adjacent two epitaxial loayers, increase one deck germanium-silicon thin membrane as mark layer, because germanium diffusion rate is in a layer of silicon less, the mark layer therefore in the present invention has interface clearly.Adopt the structure of the semiconductor device of Multilayer stack of the present invention to detect the crystal orientation of epitaxial loayer, result is more accurate, improves the positional precision that in semiconductor technology, photoetching or P body inject.
If the present invention adopts the method directly forming mark layer in described epi-layer surface, then without the need to cleaning this surface, can form next epitaxial loayer, the formation method technique of the semiconductor device of described Multilayer stack is simple.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; the Method and Technology content of above-mentioned announcement can be utilized to make possible variation and amendment to technical solution of the present invention; therefore; every content not departing from technical solution of the present invention; the any simple modification done above embodiment according to technical spirit of the present invention, equivalent variations and modification, all belong to the protection range of technical solution of the present invention.
Claims (10)
1. a structure for the semiconductor device of Multilayer stack, comprising:
Substrate, has marking structure in described substrate;
Be positioned at least two-layer epitaxial loayer replaced and at least three layers of mark layer of described substrate surface, it is characterized in that, described mark layer is germanium silicon.
2. the structure of the semiconductor device of Multilayer stack as claimed in claim 1, it is characterized in that, the material of described epitaxial loayer is silicon.
3. the structure of the semiconductor device of Multilayer stack as claimed in claim 1, it is characterized in that, in described mark layer, the content of germanium is 7% ~ 12%.
4. a formation method for the semiconductor device of Multilayer stack, comprising:
Substrate is provided, in described substrate, is formed with marking structure;
Alternately form at least two-layer epitaxial loayer and at least three layers of mark layer successively at described substrate surface, it is characterized in that, described mark layer is germanium silicon.
5. the formation method of the semiconductor device of Multilayer stack as claimed in claim 4, it is characterized in that, the formation process of described mark layer is ion implantation.
6. the formation method of the semiconductor device of Multilayer stack as claimed in claim 5, it is characterized in that, the ion of described ion implantation is germanium ion.
7. the formation method of the semiconductor device of Multilayer stack as claimed in claim 4, it is characterized in that, the formation process of described mark layer is chemical vapour deposition (CVD).
8. the formation method of the semiconductor device of Multilayer stack as claimed in claim 7, it is characterized in that, the depositing temperature of described chemical vapor deposition method is 600 ~ 800 DEG C, and pressure is 2666Pa ~ 5333Pa, the thickness of described mark layer is 40nm ~ 80nm, and the retention time is 40 ~ 60s.
9. the formation method of the semiconductor device of Multilayer stack as claimed in claim 4, it is characterized in that, in described mark layer, the content of germanium is 7% ~ 12%.
10. the formation method of the semiconductor device of Multilayer stack as claimed in claim 4, is characterized in that, also comprise and cut described semiconductor device open, described in cut described semiconductor device open technique be chemical etching.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110028185.3A CN102157497B (en) | 2011-01-26 | 2011-01-26 | The structure of the semiconductor device of Multilayer stack and formation method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110028185.3A CN102157497B (en) | 2011-01-26 | 2011-01-26 | The structure of the semiconductor device of Multilayer stack and formation method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102157497A CN102157497A (en) | 2011-08-17 |
| CN102157497B true CN102157497B (en) | 2016-03-09 |
Family
ID=44438858
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110028185.3A Active CN102157497B (en) | 2011-01-26 | 2011-01-26 | The structure of the semiconductor device of Multilayer stack and formation method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102157497B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102891135B (en) * | 2012-10-17 | 2017-02-22 | 上海华虹宏力半导体制造有限公司 | Semiconductor device and formation method thereof |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0975024A2 (en) * | 1998-07-24 | 2000-01-26 | Fuji Electric Co. Ltd. | Semiconductor device with alternating conductivity type layer and method of manufacturing the same |
| CN1281257A (en) * | 1999-06-28 | 2001-01-24 | 株式会社东芝 | Semiconductor device |
| CN1645562A (en) * | 2004-01-21 | 2005-07-27 | 精工爱普生株式会社 | Alignment method, method for manufacturing a semiconductor device, substrate for a semiconductor device, electronic equipment |
| JP2007142436A (en) * | 2005-11-22 | 2007-06-07 | Samsung Electronics Co Ltd | Semiconductor device comprising lineup mark film and method of manufacturing same |
| US7508531B1 (en) * | 2004-03-29 | 2009-03-24 | National Semiconductor Corporation | System and method for measuring germanium concentration for manufacturing control of BiCMOS films |
-
2011
- 2011-01-26 CN CN201110028185.3A patent/CN102157497B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0975024A2 (en) * | 1998-07-24 | 2000-01-26 | Fuji Electric Co. Ltd. | Semiconductor device with alternating conductivity type layer and method of manufacturing the same |
| CN1281257A (en) * | 1999-06-28 | 2001-01-24 | 株式会社东芝 | Semiconductor device |
| CN1645562A (en) * | 2004-01-21 | 2005-07-27 | 精工爱普生株式会社 | Alignment method, method for manufacturing a semiconductor device, substrate for a semiconductor device, electronic equipment |
| US7508531B1 (en) * | 2004-03-29 | 2009-03-24 | National Semiconductor Corporation | System and method for measuring germanium concentration for manufacturing control of BiCMOS films |
| JP2007142436A (en) * | 2005-11-22 | 2007-06-07 | Samsung Electronics Co Ltd | Semiconductor device comprising lineup mark film and method of manufacturing same |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102157497A (en) | 2011-08-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8900891B2 (en) | Fabrication method for interdigitated back contact photovoltaic cells | |
| US9111759B2 (en) | Semiconductor device manufacturing method | |
| CN104538407B (en) | Display panel and preparation method thereof, display device | |
| CN103065929B (en) | Manufacture method of alignment mark protective layer | |
| CN105118807B (en) | A kind of low-temperature polysilicon film transistor and its manufacturing method | |
| CN100364140C (en) | Precision mask for film forming and its manufacturing method, electroluminescence device and manufacturing method | |
| CN105489500B (en) | The preparation method and its hyperconjugation VDMOS device of hyperconjugation VDMOS | |
| CN102792446A (en) | Method for producing silicon carbide semiconductor device | |
| CN109742151A (en) | Thin film transistor and its manufacturing method, array substrate and display panel | |
| CN102157497B (en) | The structure of the semiconductor device of Multilayer stack and formation method | |
| CN101958242B (en) | Method for manufacturing gate oxide layer and grid polycrystalline silicon layer | |
| CN104897319A (en) | Pressure sensor structure and manufacturing method thereof | |
| CN103681250B (en) | The control method of the critical size of twice etching molding figure | |
| CN105321803B (en) | The method for forming semiconductor arrangement | |
| CN102437020B (en) | Wafer control slice and forming method thereof | |
| CN104637811B (en) | Transistor fabrication process and transistor | |
| CN103021936B (en) | Bipolar circuit manufacture method | |
| CN103943509A (en) | Manufacture procedure method of thin film transistor | |
| CN100452410C (en) | Active driving TFT matrix structure and method of manufacture | |
| CN101170129A (en) | Horizontal PNP transistor and its making technology method | |
| CN109116604A (en) | The method of display panel, display panel are made in mixed cutting | |
| CN105572990B (en) | Array substrate and its manufacturing method, liquid crystal display panel | |
| CN104779164A (en) | Method for increasing breakdown voltage of gate oxide layer of trench-type VDMOS | |
| CN102891135A (en) | Semiconductor device and formation method thereof | |
| CN105655347A (en) | TFT backboard, preparation method thereof and display device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| ASS | Succession or assignment of patent right |
Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HONGLI SEMICONDUCTOR MANUFACTURE CO LTD, SHANGHAI Effective date: 20140408 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20140408 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Applicant after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Applicant before: Hongli Semiconductor Manufacture Co., Ltd., Shanghai |
|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |