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CN102157462A - 晶片封装体及其制造方法 - Google Patents

晶片封装体及其制造方法 Download PDF

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Publication number
CN102157462A
CN102157462A CN2011100250484A CN201110025048A CN102157462A CN 102157462 A CN102157462 A CN 102157462A CN 2011100250484 A CN2011100250484 A CN 2011100250484A CN 201110025048 A CN201110025048 A CN 201110025048A CN 102157462 A CN102157462 A CN 102157462A
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CN
China
Prior art keywords
semiconductor
wall
encapsulation body
wafer encapsulation
wafer
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Granted
Application number
CN2011100250484A
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English (en)
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CN102157462B (zh
Inventor
倪庆羽
徐长生
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XinTec Inc
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XinTec Inc
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Publication of CN102157462A publication Critical patent/CN102157462A/zh
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Publication of CN102157462B publication Critical patent/CN102157462B/zh
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    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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Abstract

本发明有关于一种晶片封装体及其制造方法，晶片封装体包括具有晶粒的半导体基底、设置于半导体基底之上的封装层以及设置于半导体基底与封装层之间的间隔层，其中由半导体基底、间隔层与封装层所构成的表面具有凹陷部。晶片封装体的制造方法包括在半导体晶圆的多个晶粒与封装层之间形成多个间隔层，其中对应每一晶粒的每一间隔层互相分离，且此间隔层自晶粒边缘向内退缩形成凹陷部，以及沿着相邻两个晶粒之间的切割道分割半导体晶圆，以形成多个晶片封装体。本发明能够避免晶片封装体产生脱层现象，从而可有效避免水气及空气进入晶片封装体中，以提升晶片封装体的可靠度、避免元件发生电性不良。

Description

晶片封装体及其制造方法
技术领域
本发明有关于一种晶片封装体，特别有关于一种晶片封装体的间隔层结构设计及其制造方法。
背景技术
目前业界针对晶片的封装已发展出一种晶圆级封装技术，半导体晶圆通常与玻璃基板接合在一起，并在半导体晶圆与玻璃基板之间设置间隔层。于晶圆级封装体完成之后，在各晶片之间进行切割步骤以形成晶片封装体。
在现有的晶片封装体中，半导体基底、间隔层与玻璃基板之间为连续的界面，由于各层的材料不同，膨胀系数也不同，因此当现有的晶片封装体受到高温影响下，半导体基底、间隔层与玻璃基板之间会产生脱层的现象，使得水气及空气进入晶片封装体，导致现有的晶片封装体发生电性不良。
因此，业界亟需一种晶片封装体，其可以克服上述问题，避免晶片封装体产生脱层现象。
发明内容
本发明提供一种晶片封装体，包括一具有晶粒的半导体基底、设置于半导体基底之上的封装层以及设置于半导体基底与封装层之间的间隔层，其中由半导体基底、间隔层与封装层所构成的表面具有凹陷部，此凹陷部位于半导体基底与封装层之间，使得半导体基底、间隔层以及封装层形成一不连续的界面。
本发明所述的晶片封装体，该凹陷部围绕该间隔层形成一环状凹陷部。
本发明所述的晶片封装体，该间隔层的形状为一矩形，且该凹陷部设置于该矩形的各角落、各边或前述的组合。
本发明所述的晶片封装体，该凹陷部位于该半导体基底与该封装层之间。
本发明所述的晶片封装体，还包括：一周边接垫区与一元件区，其中该周边接垫区围绕该元件区；多个导电垫，设置于该周边接垫区上；以及一密封环，设置于该周边接垫区上，且围绕所述导电垫。
本发明所述的晶片封装体，该密封环位于该间隔层的范围内。
本发明所述的晶片封装体，还包括：一导通孔，设置于该半导体基底的一表面上以暴露出所述导电垫；一绝缘层，设置于该半导体基底的该表面上，且延伸至该导通孔的侧壁上；一导线层，设置于该绝缘层上，且延伸至该导通孔的底部，与所述导电垫电性连接；一保护层，覆盖该导线层与该绝缘层，且具有一开口，暴露出部分的该导线层；以及一导电凸块，设置于该保护层的该开口中，与该导线层电性连接。
本发明所述的晶片封装体，还包括一间隙形成于该封装层与该半导体基底的该晶粒之间，且该间隙被该间隔层所围绕。
本发明所述的晶片封装体，该间隔层的材料包括感光绝缘材料。
本发明所述的晶片封装体，还包括一粘着层设置于该间隔层与该半导体基底之间，或设置于该间隔层与该封装层之间。
此外，本发明还提供一种晶片封装体的制造方法，包括：提供一半导体晶圆，包含多个晶粒，任两个相邻的晶粒之间包括一切割道；提供一封装层；形成多个间隔层于半导体晶圆的所述晶粒与封装层之间，其中对应每一晶粒的每一间隔层互相分离，且此间隔层自晶粒边缘向内退缩形成凹陷部；接合半导体晶圆与封装层；以及沿着切割道分割半导体晶圆以形成多个晶片封装体。
本发明所述的晶片封装体的制造方法，该凹陷部围绕该间隔层形成一环状凹陷部。
本发明所述的晶片封装体的制造方法，该间隔层的形状为一矩形，且该凹陷部位于该矩形的各角落、各边或前述的组合。
本发明所述的晶片封装体的制造方法，该晶粒包括一周边接垫区与一元件区，且该周边接垫区围绕该元件区。
本发明所述的晶片封装体的制造方法，多个导电垫，形成于该周边接垫区上；以及一密封环，形成于该周边接垫区上，且围绕所述导电垫，其中任两个相邻的该密封环之间定义该切割道。
本发明所述的晶片封装体的制造方法，该密封环位于该间隔层的范围内。
本发明所述的晶片封装体的制造方法，还包括：形成一导通孔于该半导体基底的一表面上以暴露出该导电垫；形成一绝缘层于该半导体基底的该表面上，且延伸至该导通孔的侧壁上；形成一导线层于该绝缘层上，且延伸至该导通孔的底部，与所述导电垫电性连接；形成一保护层，覆盖该导线层与该绝缘层；形成一开口于该保护层中，暴露出部分的该导线层；以及形成一导电凸块于该保护层的该开口中以与该导线层电性连接。
本发明所述的晶片封装体的制造方法，还包括形成一间隙于该封装层与该半导体基底的该晶粒之间，其中该间隙被该间隔层所围绕。
本发明所述的晶片封装体的制造方法，形成该间隔层的步骤包括曝光及显影制程。
本发明所述的晶片封装体的制造方法，还包括形成一粘着层于该间隔层与该半导体基底之间，或者于该间隔层与该封装层之间。
本发明能够避免晶片封装体产生脱层现象。
附图说明
图1A-1H显示依据本发明实施例的形成晶片封装体的制造方法的剖面示意图。
附图中符号的简单说明如下：
100：半导体基底；100A：元件区；100B：周边接垫区；SL：切割道；102：金属层间介电层；104：导电垫；106：密封环；108、110：间隔层；112：粘着层；114：封装层；116：间隙；117：微透镜阵列；118：导通孔；120：绝缘层；122：导线层；124：保护层；126：保护层的开口；128：导电凸块；130：切割线；132：凹陷部；200：光罩；210：光罩图案；220：曝光制程。
具体实施方式
为了让本发明的上述目的、特征及优点能更明显易懂，以下配合所附图式作详细说明如下。
以下以实施例并配合图式详细说明本发明，在图式或说明书描述中，相似或相同的部分使用相同的图号。且在图式中，实施例的形状或厚度可扩大以简化或是方便标示。再者，图式中各元件的部分将以描述说明之，值得注意的是，图中未绘示或描述的元件为本领域技术人员所知的形式。另外，特定的实施例仅为揭示本发明使用的特定方式，其并非用以限定本发明。
本发明以制作影像感测元件封装体(image sensor package)的实施例作为说明。然而，可以了解的是，在本发明的晶片封装体的实施例中，其可应用于各种包含有源元件或无源元件(active or passive elements)、数字电路或模拟电路(digital oranalog circuits)等集成电路的电子元件(electronic components)，例如是有关于光电元件(opto electronic devices)、微机电系统(Micro Electro Mechanical System；MEMS)、微流体系统(microfluidic systems)、或利用热、光线及压力等物理量变化来测量的物理感测器(Physical Sensor)。特别是可选择使用晶圆级封装(wafer scale package；WSP)制程对影像感测元件、发光二极管(light-emitting diodes；LEDs)、太阳能电池(solar cells)、射频元件(RF circuits)、加速计(accelerators)、陀螺仪(gyroscopes)、微制动器(micro actuators)、表面声波元件(surface acoustic wavedevices)、压力感测器(process sensors)或喷墨头(ink printerheads)等半导体晶片进行封装。
其中上述晶圆级封装制程主要指在晶圆阶段完成封装步骤后，再予以切割成独立的封装体，然而，在一特定实施例中，例如将已分离的半导体晶片重新分布在一承载晶圆上，再进行封装制程，亦可称之为晶圆级封装制程。另外，上述晶圆级封装制程亦适用于借堆叠(stack)方式安排具有集成电路的多片晶圆以形成多层集成电路(multi-layer integrated circuit devices)的晶片封装体。
本发明实施例提供一种晶片封装体及其制造方法，在上述元件的晶圆级封装体完成之后以切割制程分割各晶粒，形成晶片封装体。在本发明实施例的晶片封装体中，由半导体基底、间隔层与封装层所构成的表面具有一凹陷部。在一实施例中，此凹陷部位于半导体基底与封装层之间，使得半导体基底、间隔层以及封装层形成一不连续的界面，避免晶片封装体产生脱层(delamination)现象。
接着，请参阅图1A至1H，其显示依据本发明的实施例形成晶片封装体的制造方法的剖面示意图。如图1A所示，首先提供一包含多个晶粒的半导体晶圆100，每个晶粒包含元件区100A与周边接垫区100B，其中周边接垫区100B围绕元件区100A。
此外，半导体晶圆100还具有多个导电垫(conductivepad)104以及密封环(seal ring)106，设置在半导体晶圆100内的晶粒的周边接垫区100B上。导电垫104与密封环106由多层的金属层以及多层的导孔(via)所组成，形成于金属层间介电层(intermetal dielectric layer；IMD)102中，其中密封环106围绕导电垫104，并包围元件区100A，介于任两个相邻的晶粒之间的切割道(scribe line)SL由任两个相邻的密封环106之间所定义。
接着，请参阅图1B，在半导体晶圆100的表面上全面性形成间隔层材料108，间隔层材料108可以为感光绝缘材料，例如环氧树脂(epoxy)、阻焊材料(solder mask)等，可利用涂布方式形成。如图1B所示，提供一光罩200，设置于间隔层材料108上方，光罩200具有光罩图案210，对应至预定形成的间隔层图案。
接着，对间隔层材料108进行曝光220及显影制程，定义间隔层(spacer)110图案，形成多个间隔层110，如图1C所示。在一实施例中，间隔层110形成于周边接垫区100B上，围绕元件区100A，以上视角度观之，对应每一晶粒的每一间隔层110互相分离，形成不连续的间隔层110图案，且间隔层110自晶粒边缘，亦即周边接垫区100B的边界向内退缩，形成凹陷部，密封环106位于间隔层110的范围内。
接着，如图1D所示，提供封装层114与半导体晶圆100接合，封装层114例如为玻璃基板或是另一空白硅晶圆。在一实施例中，可通过间隔层110分开封装层114与半导体晶圆100，同时形成由间隔层110所围绕的间隙116(cavity)。在此实施例中，间隔层110先形成于半导体晶圆100上，然后再通过粘着层112与封装层114接合。在另一实施例中，亦可将间隔层110先形成于封装层114上，然后再通过粘着层(未绘出)与半导体晶圆100接合，此时，粘着层介于间隔层110与半导体晶圆100之间。
上述粘着层可利用网版印刷(screen printing)的方式涂布于间隔层110上，粘着层的图案大抵上与间隔层110的图案相同。
接着，请参阅图1E，于半导体晶圆100的背面，以光刻及蚀刻方式形成导通孔(through hole)118，暴露出导电垫104的表面。然后，如图1F所示，在半导体晶圆100的背面上形成绝缘层120，且延伸至导通孔118的侧壁上。绝缘层120可以为非光致抗蚀剂的绝缘材料，例如氧化硅、氮化硅或氮氧化硅，可利用热氧化法、化学气相沉积法(CVD)或物理气相沉积法(PVD)，顺应性地形成绝缘材料于半导体晶圆100的背面上以及导通孔118的侧壁和底部上，接着，以光刻及蚀刻方式除去导通孔118底部的绝缘材料，形成如图1F所示的绝缘层120。
接着，在绝缘层120上形成导线层(conductive tracelayer)122，且延伸至导通孔118的底部，以与导电垫104电性连接。可通过例如溅镀(sputtering)、蒸镀(evaporating)或电镀(electroplating)的方式，沉积例如铜、铝或镍(nickel；Ni)的导电材料层(未绘示)于绝缘层120上以及导通孔118内，然后再通过光刻及蚀刻方式图案化导电材料层以形成上述导线层122。
如图1G所示，在绝缘层120以及导线层122上涂布一例如阻焊膜(solder mask)的保护层124覆盖导线层122，接着，图案化保护层124形成开口126，以暴露部分的导线层122。然后，在保护层124的开口126内涂布焊料，并进行回焊(reflow)步骤，以形成导电凸块128，导电凸块128可以是焊球(solder ball)或焊垫(solder paste)。
然后，以切割刀(未绘出)沿着切割道SL内的线130将半导体晶圆100分割，即可形成多个晶片封装体，如图1H所示。值得注意的是，切割刀的宽度小于切割道SL的宽度。
请参阅图1H，其显示依据本发明一实施例的晶片封装体的剖面示意图。晶粒具有的半导体基底100例如由半导体晶圆分割而来，晶粒包含元件区100A和周边接垫区100B在半导体基底100中，其中周边接垫区100B围绕元件区100A。
在半导体基底100的周边接垫区100B上具有多个导电垫104以及密封环106，导电垫104例如为接合垫(bonding pad)，可通过金属连线(未绘出)连接至晶片内部，密封环106位于导电垫104的外侧，可以防止半导体晶圆于切割制程中产生的裂缝延伸至晶片内，密封环106并未与晶片内部产生电性连接。
依据本发明的实施例，经由分割半导体晶圆100所形成的晶片封装体中，由封装层114、间隔层110以及半导体基底100所构成的表面具有一凹陷部132，此凹陷部132介于封装层114与半导体基底100之间，使得封装层114、粘着层112、间隔层110以及半导体基底100形成一不连续的界面。
在一实施例中，以上视角度观之，凹陷部132围绕着间隔层110形成一环状凹陷部，此时，对应相邻的两个晶粒的所述间隔层110互相分离。在另一实施例中，以上视角度观之，对应一个晶粒的间隔层110的形状可以为矩形，且凹陷部132可设置于矩形的各角落、各边或前述的组合。当凹陷部132设置于矩形的角落时，即形成一L型的开口于间隔层110的角落；当凹陷部132设置于矩形的各边时，则对应相邻的两个晶粒的所述间隔层110互相连接，并形成矩形的开口于相邻的两个间隔层110中。
在一实施例中，上述晶片封装体可应用于影像感测元件，例如互补式金属氧化物半导体元件(CMOS)或电荷耦合元件(charge-couple device；CCD)，此外如微机电元件等亦不在此限。
上述导电垫104及密封环106较佳可以由铜(copper；Cu)、铝(aluminum；A1)或其它合适的金属材料所制成。在封装层114与半导体基底100之间可设置间隔层110，使半导体基底100与封装层114之间形成间隙116，间隙116被间隔层110所围绕。此外，在半导体基底100的元件区100A上还可以形成微透镜阵列(micro lens array)117，以利于影像感测元件接收光线。
在一实施例中，封装层114可以是透明基底，例如玻璃、石英(quartz)、蛋白石(opal)、塑胶或其它任何可供光线进出的透明基板。值得一提的是，也可以选择性地形成滤光片(filter)及/或抗反射层(anti-reflective layer)于封装层114上。在非感光元件晶片的实施例中，封装层114则可以是半导体材料层，例如硅覆盖层。
在另一实施例中，半导体基底100与封装层114之间也可以完全填满间隔层110，而不形成间隙。
依据本发明的实施例，可在晶片封装体中形成凹陷部132，介于封装层114与半导体基底100之间，使得封装层114、粘着层112、间隔层110以及半导体基底100形成不连续的界面，借此可降低封装层114、粘着层112、间隔层110以及半导体基底100各层之间因为热膨胀系数不同所产生的应力，避免晶片封装体产生脱层现象。
因此，本发明的实施例可有效避免水气及空气进入晶片封装体中，提升晶片封装体的可靠度，以避免元件发生电性不良。
以上所述仅为本发明较佳实施例，然其并非用以限定本发明的范围，任何熟悉本项技术的人员，在不脱离本发明的精神和范围内，可在此基础上做进一步的改进和变化，因此本发明的保护范围当以本申请的权利要求书所界定的范围为准。

Claims (20)

1.一种晶片封装体，其特征在于，包括：
一晶粒，具有一半导体基底；
一封装层，设置于该半导体基底之上；以及
一间隔层，设置于该半导体基底与该封装层之间，其中由该半导体基底、该间隔层与该封装层所构成的一表面具有一凹陷部。
2.根据权利要求1所述的晶片封装体，其特征在于，该凹陷部围绕该间隔层形成一环状凹陷部。
3.根据权利要求1所述的晶片封装体，其特征在于，该间隔层的形状为一矩形，且该凹陷部设置于该矩形的各角落、各边或前述的组合。
4.根据权利要求1所述的晶片封装体，其特征在于，该凹陷部位于该半导体基底与该封装层之间。
5.根据权利要求4所述的晶片封装体，其特征在于，还包括：
一周边接垫区与一元件区，其中该周边接垫区围绕该元件区；
多个导电垫，设置于该周边接垫区上；以及
一密封环，设置于该周边接垫区上，且围绕所述导电垫。
6.根据权利要求5所述的晶片封装体，其特征在于，该密封环位于该间隔层的范围内。
7.根据权利要求5所述的晶片封装体，其特征在于，还包括：
一导通孔，设置于该半导体基底的一表面上以暴露出所述导电垫；
一绝缘层，设置于该半导体基底的该表面上，且延伸至该导通孔的侧壁上；
一导线层，设置于该绝缘层上，且延伸至该导通孔的底部，以与所述导电垫电性连接；
一保护层，覆盖该导线层与该绝缘层，且具有一开口，以暴露出部分的该导线层；以及
一导电凸块，设置于该保护层的该开口中，以与该导线层电性连接。
8.根据权利要求1所述的晶片封装体，其特征在于，还包括一间隙形成于该封装层与该半导体基底的该晶粒之间，且该间隙被该间隔层所围绕。
9.根据权利要求1所述的晶片封装体，其特征在于，该间隔层的材料包括感光绝缘材料。
10.根据权利要求1所述的晶片封装体，其特征在于，还包括一粘着层设置于该间隔层与该半导体基底之间，或设置于该间隔层与该封装层之间。
11.一种晶片封装体的制造方法，其特征在于，包括：
提供一半导体晶圆，包含多个晶粒，任两个相邻的晶粒之间包括一切割道；
提供一封装层；
形成多个间隔层于该半导体晶圆的所述晶粒与该封装层之间，其中对应每一晶粒的每一间隔层互相分离，且该间隔层自该晶粒边缘向内退缩形成一凹陷部；
接合该半导体晶圆与该封装层；以及
沿着该切割道分割该半导体晶圆以形成多个晶片封装体。
12.根据权利要求11所述的晶片封装体的制造方法，其特征在于，该凹陷部围绕该间隔层形成一环状凹陷部。
13.根据权利要求11所述的晶片封装体的制造方法，其特征在于，该间隔层的形状为一矩形，且该凹陷部位于该矩形的各角落、各边或前述的组合。
14.根据权利要求11所述的晶片封装体的制造方法，其特征在于，该晶粒包括一周边接垫区与一元件区，且该周边接垫区围绕该元件区。
15.根据权利要求14所述的晶片封装体的制造方法，其特征在于，多个导电垫，形成于该周边接垫区上；以及一密封环，形成于该周边接垫区上，且围绕所述导电垫，其中任两个相邻的该密封环之间定义该切割道。
16.根据权利要求15所述的晶片封装体的制造方法，其特征在于，该密封环位于该间隔层的范围内。
17.根据权利要求15所述的晶片封装体的制造方法，其特征在于，还包括：
形成一导通孔于该半导体基底的一表面上以暴露出该导电垫；
形成一绝缘层于该半导体基底的该表面上，且延伸至该导通孔的侧壁上；
形成一导线层于该绝缘层上，且延伸至该导通孔的底部，以与所述导电垫电性连接；
形成一保护层，覆盖该导线层与该绝缘层；
形成一开口于该保护层中，以暴露出部分的该导线层；以及
形成一导电凸块于该保护层的该开口中以与该导线层电性连接。
18.根据权利要求11所述的晶片封装体的制造方法，其特征在于，还包括形成一间隙于该封装层与该半导体基底的该晶粒之间，其中该间隙被该间隔层所围绕。
19.根据权利要求11所述的晶片封装体的制造方法，其特征在于，形成该间隔层的步骤包括曝光及显影制程。
20.根据权利要求11所述的晶片封装体的制造方法，其特征在于，还包括形成一粘着层于该间隔层与该半导体基底之间，或者于该间隔层与该封装层之间。
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Publication number Priority date Publication date Assignee Title
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Families Citing this family (19)

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Publication number Priority date Publication date Assignee Title
US8890268B2 (en) * 2010-02-26 2014-11-18 Yu-Lung Huang Chip package and fabrication method thereof
US8742564B2 (en) * 2011-01-17 2014-06-03 Bai-Yao Lou Chip package and method for forming the same
JP5958732B2 (ja) * 2011-03-11 2016-08-02 ソニー株式会社 半導体装置、製造方法、および電子機器
US9203523B2 (en) * 2011-04-29 2015-12-01 Mellanox Technologies Denmark Aps Modular chip layout for active optical links
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US10008413B2 (en) * 2013-08-27 2018-06-26 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer level dicing method
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US9515002B2 (en) 2015-02-09 2016-12-06 Micron Technology, Inc. Bonding pads with thermal pathways
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US9659879B1 (en) * 2015-10-30 2017-05-23 Taiwan Semiconductor Manufacturing Company Semiconductor device having a guard ring
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JP6604476B2 (ja) * 2016-03-11 2019-11-13 パナソニックＩｐマネジメント株式会社 素子チップの製造方法
WO2018069448A1 (en) * 2016-10-12 2018-04-19 At&S Austria Technologie & Systemtechnik Aktiengesellschaft Forming solid material in recess of layer structure based on applied fluidic medium
US10074618B1 (en) * 2017-08-14 2018-09-11 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method thereof
US10276514B1 (en) * 2017-10-31 2019-04-30 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure and manufacturing method thereof
US11011502B2 (en) * 2018-01-19 2021-05-18 Nepes Co., Ltd. Semiconductor package
CN109585480A (zh) * 2018-11-30 2019-04-05 德淮半导体有限公司 半导体器件及其形成方法、切割方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040077121A1 (en) * 2002-04-22 2004-04-22 Hiroshi Maeda Solid-state imaging device and method of manufacturing said solid-state imaging device
CN1713392A (zh) * 2004-06-15 2005-12-28 夏普株式会社 具有盖部分的半导体晶片制造方法和半导体器件制造方法
WO2008117434A1 (ja) * 2007-03-27 2008-10-02 Fujitsu Limited 半導体部品および半導体部品の製造方法
CN101419952A (zh) * 2008-12-03 2009-04-29 晶方半导体科技（苏州）有限公司 晶圆级芯片封装方法及封装结构

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6962834B2 (en) * 2002-03-22 2005-11-08 Stark David H Wafer-level hermetic micro-device packages
JP4526771B2 (ja) * 2003-03-14 2010-08-18 株式会社半導体エネルギー研究所 半導体装置の作製方法
US7229900B2 (en) * 2003-10-28 2007-06-12 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, method of manufacturing thereof, and method of manufacturing base material
US7936062B2 (en) * 2006-01-23 2011-05-03 Tessera Technologies Ireland Limited Wafer level chip packaging
KR20090074970A (ko) * 2008-01-03 2009-07-08 삼성전자주식회사 가아드 링을 갖는 반도체 장치
US8022509B2 (en) * 2008-11-28 2011-09-20 United Microelectronics Corp. Crack stopping structure and method for fabricating the same
US8039367B2 (en) * 2009-05-13 2011-10-18 United Microelectronics Corp. Scribe line structure and method for dicing a wafer
TWI482253B (zh) * 2009-12-28 2015-04-21 Xintec Inc 晶片封裝體
US9252172B2 (en) * 2011-05-31 2016-02-02 Stats Chippac, Ltd. Semiconductor device and method of forming EWLB semiconductor package with vertical interconnect structure and cavity region

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040077121A1 (en) * 2002-04-22 2004-04-22 Hiroshi Maeda Solid-state imaging device and method of manufacturing said solid-state imaging device
CN1713392A (zh) * 2004-06-15 2005-12-28 夏普株式会社 具有盖部分的半导体晶片制造方法和半导体器件制造方法
WO2008117434A1 (ja) * 2007-03-27 2008-10-02 Fujitsu Limited 半導体部品および半導体部品の製造方法
CN101419952A (zh) * 2008-12-03 2009-04-29 晶方半导体科技（苏州）有限公司 晶圆级芯片封装方法及封装结构

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102437109A (zh) * 2011-11-30 2012-05-02 日月光半导体制造股份有限公司 半导体结构及其制作方法
CN103130174A (zh) * 2011-12-02 2013-06-05 台湾积体电路制造股份有限公司 Mems器件及其形成方法
CN103130174B (zh) * 2011-12-02 2015-10-28 台湾积体电路制造股份有限公司 Mems器件及其形成方法
CN103219253A (zh) * 2012-01-20 2013-07-24 东琳精密股份有限公司 芯片尺寸封装结构及其芯片尺寸封装方法
CN103219253B (zh) * 2012-01-20 2016-02-10 东琳精密股份有限公司 芯片尺寸封装结构及其芯片尺寸封装方法
CN102751299A (zh) * 2012-05-04 2012-10-24 香港应用科技研究院有限公司 低成本、高集成度之背照式图像传感器封装
CN102751299B (zh) * 2012-05-04 2015-01-21 香港应用科技研究院有限公司 低成本、高集成度之背照式图像传感器封装
CN103545295B (zh) * 2012-07-16 2016-08-10 精材科技股份有限公司 晶片封装体及其形成方法
CN103545295A (zh) * 2012-07-16 2014-01-29 精材科技股份有限公司 晶片封装体及其形成方法
CN104952894A (zh) * 2014-03-25 2015-09-30 精材科技股份有限公司 半导体结构的制造方法
CN104952894B (zh) * 2014-03-25 2018-06-05 精材科技股份有限公司 半导体结构的制造方法
CN105826332A (zh) * 2015-01-09 2016-08-03 中芯国际集成电路制造(上海)有限公司 半导体结构的形成方法
WO2017071426A1 (zh) * 2015-10-28 2017-05-04 苏州晶方半导体科技股份有限公司 影像传感芯片封装结构及封装方法
US10541262B2 (en) 2015-10-28 2020-01-21 China Wafer Level Csp Co., Ltd. Image sensing chip packaging structure and packaging method

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