CN102035550B - Circuit and method for solving instable power-on process of sigma-delta analog-to-digital conversion circuit - Google Patents
Circuit and method for solving instable power-on process of sigma-delta analog-to-digital conversion circuit Download PDFInfo
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Abstract
The invention provides a circuit and a method for solving the instable power-on process of a sigma-delta analog-to-digital conversion circuit. The circuit comprises controlled devices and a power supply detection circuit, wherein the controlled devices are connected with integrators of the sigma-delta analog-to-digital conversion circuit to be controlled, the power supply detection circuit provides control signals to the controlled devices according to the detected power supply condition of the power supply and can adopt a power-on reset circuit, and the existing power-on reset circuit of an SOC (System On Chip) with the sigma-delta analog-to-digital conversion circuit can be directly utilized to greatly lessen the circuit complexity of the SOC and effectively save the cost. In addition, the invention also provides the SOC of the power-on reset circuit shared by the sigma-delta analog-to-digital conversion circuit and other functional devices.
Description
Technical field
The present invention relates to the unsettled circuit of a kind of control sigma-delta analog to digital conversion circuit and method, particularly a kind of solution ∑-Δ unsettled circuit of analog to digital conversion circuit power up and method.
Background technology
At the numerous areas of electron trade, especially in digital speech, audio frequency and detection metering device field, SOC (system on a chip) (being SOC, System On Chip) is widely used.So-called SOC system, integrates the multiple common function chip of (as audio frequency processing, Video processing, USB/DDR process and power management etc.) exactly.And sigma-delta analog to digital conversion circuit (being Sigma-delta ADC) due to have conversion accuracy high, the performance of analog circuit and device matching are required to become one of requisite member of each SOC (system on a chip) compared with the advantage such as low.
Existing sigma-delta ADC mainly consists of two parts, and one is simulation sigma-delta modulator, and another is decimation filter of digital.Sigma-delta modulator generally consists of one or more integrators, comparator and the DAC on feedback control loop (analog to digital converter); And decimation filter of digital be mainly used in decaying spurious signal outside more than base band quantizing noise, restriction input signal bandwidth, inhibition zone and circuit noise etc., therefore, not only consumed power is large for it, and area occupied also can be more than sigma-delta modulator on chip.For sigma-delta ADC, in order to reduce quantizing noise, sigma-delta modulator all can be to noise shaping, and its mode that realizes noise shaping is all generally the sigma-delta modulator (circuit that comprises a plurality of integration stages) that adopts high-order.Yet, no matter be low order or higher order modulator, when input signal is greater than the scope that sigma-delta ADC input allows, all can there is the saturated labile state of modulator.Once modulator is unstable, even if input signal proceeds to normally, modulator can not got back to normal operating conditions automatically yet conventionally.
Modulator is unstable shows integrator non-linear (be integrator cause to plus or minus level direction integral for a long time saturated) or quantizer long term overloading (being that output signal is long-time for the highest or minimum) conventionally.When sigma-delta ADC powers on, often the most easily occur that modulator is unstable.No matter to low-order-modulated device (exponent number≤2) and higher order modulator (exponent number >=3), in power up, there is the saturated unsettled problem of modulator in capital, for example, when input is that a large-signal (this large-signal is in input signal allowed band) and the quantification reference voltage of ADC be not when also set up completely, just there will be input signal to be greater than quantification reference voltage, thereby cause modulator saturated.In power up, because also may making modulator, the residing nondeterministic statement of integrator is in labile state in addition.Therefore, once sigma delta ADC need to adopt auxiliary circuit to make modulator occur the saturated state that can return to normal operation in power up.
In order to make modulator working stability, research staff has proposed several different methods, is wherein comparatively typically the integrator in modulator is resetted.Whether stable by the output signal of integrator or output state being detected to judge modulator, if find unstablely, just make integrator reset, namely make the input and output short circuit of integrator.As shown in Figure 1, it is the modulator circuit schematic diagram of a sigma-delta adc circuit.This modulator has 4 integrators, it is integrator 10, 12, 14, with 16, wherein, the input of each integrator and input are connected with respectively a controlled switch, in integrator 10 inputs, be connected controlled switch SW1 with input, in integrator 12 inputs, be connected controlled switch SW2 with input, in integrator 14 inputs, be connected controlled switch SW3 with input, in integrator 16 inputs, be connected controlled switch SW4 with input, each controlled switch is controlled by the output signal of oscillation test comparator 20, oscillation test comparator 20 by the output of integrator 12 with reference to thresholding, compare, when the output of integrator 12 surpasses with reference to thresholding, oscillation test comparator 20 output control signals make each controlled switch closed, thereby make each integrator input and output short circuit, realize and resetting thus.
Although this kind of control mode is simple, is difficult to unsettled generation accurately be detected, because the reference thresholding of comparator exists certain accuracy error; And its unstable situation that can detect is also very limited, that is: only just for integrator, 12 outputs surpass with reference to a kind of like this situation of thresholding.And in fact, sigma-delta adc circuit is powering on or more easily to cause integrator work during power down uncertain, for this situation, this kind of method is but helpless.What is more important, the existing SOC (system on a chip) that disposes sigma-delta adc circuit, its chip area is very limited, and the method need to be set up in the limited space of SOC (system on a chip) oscillation test comparator 20 especially again, so easily cause first the interference between device, moreover unavoidably can increase the complexity of SOC (system on a chip) circuit, therefore, the utmost point is necessary to seek a kind of new method and solves the unsettled problem of sigma-delta ADC.
Summary of the invention
The object of the present invention is to provide a kind of solution sigma-delta unsettled circuit of analog to digital conversion circuit power up and method.
Another object of the present invention is to provide the SOC (system on a chip) that a kind of circuit is simple, cost is low.
In order to achieve the above object and other objects, the unsettled circuit of solution sigma-delta analog to digital conversion circuit power up provided by the invention, comprise: at least one controlled device, is connected with an integration of sigma-delta analog to digital conversion circuit to be controlled separately; And power sense circuit, be connected with each controlled device, for detection of the power supply situation that offers the power supply of described sigma-delta analog to digital conversion circuit to be controlled, and to each controlled device, provide the first control signal when power supply instability being detected, each integrator is resetted, and after detection power supply is stable, to each controlled device, provide the second control signal, make each integrator enter integration operating state, thereby make the working stability of described sigma-delta analog to digital conversion circuit to be controlled.
The unsettled method of solution sigma-delta analog to digital conversion circuit power up of the present invention, comprise step: 1) when a power sense circuit detects the power supply during in power supply instability state that offers sigma-delta analog to digital conversion circuit to be controlled, described power sense circuit sends the first control signal to each controlled device that is connected to each modulator of described sigma-delta analog to digital conversion circuit to be controlled, so that each integrator resets; 2) when described power sense circuit detect offer the Power supply of sigma-delta analog to digital conversion circuit to be controlled stable after, described power sense circuit sends the second control signal to each controlled device, so that each integrator in integration operating state, is realized the working stability of described sigma-delta analog to digital conversion circuit to be controlled thus.
Wherein, described power supply instability state comprises the labile state that the power on labile state that causes and power down cause.
Preferably, described power sense circuit can be electrify restoration circuit, can be especially low consumption circuit.For lowering circuit complexity, the electrify restoration circuit that it also can directly adopt the SOC (system on a chip) self at described sigma-delta analog to digital conversion circuit place to be controlled to have.
Preferably, controlled device can be connected on the integrator in modulator, for example, is connected between the input and output of integrator, and it can be controlled switch, such as being relay, regular tap or metal-oxide-semiconductor etc.
Preferably, sigma-delta analog to digital conversion circuit to be controlled can be low order sigma-delta analog to digital conversion circuit, cascade 2-1sigma-delta analog to digital conversion circuit or cascade 2-2sigma-delta analog to digital conversion circuit of exponent number≤2 etc.
SOC (system on a chip) of the present invention, at least comprises: sigma-delta analog to digital conversion circuit; Be connected to each controlled device of described each integrator of sigma-delta analog to digital conversion circuit; At least one function element; And electrify restoration circuit, power supply situation for detection of the power supply accessing, and to each controlled device and described at least one function element, provide the first control signal when power supply instability being detected, each integrator and at least one function element are resetted, and after detection power supply is stable, to each controlled device and at least one function element, provide the second control signal, make each integrator enter integration operating state, make at least one function element enter normal operating conditions simultaneously.
In addition, described function element can be: the oscillator in trigger, latch, register, counter, analog circuit, comparator etc.
In sum, the unsettled Method and circuits of solution sigma-delta analog to digital conversion circuit power up of the present invention adopts and directly the working condition of power supply is detected, control the controlled device being respectively connected between integrator input and output, and then control the reset of each integrator, avoid the generation of the situation of the sigma-delta analog to digital conversion circuit job insecurity that brings because of power supply electrifying or power down.
Accompanying drawing explanation
Fig. 1 is the circuit diagram of the integrator job insecurity of existing solution sigma-delta analog to digital conversion circuit.
Fig. 2 is the basic framework schematic diagram of the unsettled circuit of solution sigma-delta analog to digital conversion circuit power up of the present invention.
Fig. 3 is the embodiment schematic diagram of the workflow of the unsettled circuit of solution sigma-delta analog to digital conversion circuit power up of the present invention.
Fig. 4 is the specific embodiment schematic diagram of the unsettled circuit of solution sigma-delta analog to digital conversion circuit power up of the present invention.
Fig. 5 is the sequential relationship schematic diagram of each voltage of sigma-delta analog to digital conversion circuit of controlling of the unsettled circuit of solution of the present invention sigma-delta analog to digital conversion circuit power up.
Fig. 6 is the circuit diagram of the electrify restoration circuit that adopts of the unsettled circuit of solution of the present invention sigma-delta analog to digital conversion circuit power up.
Fig. 7 is SOC (system on a chip) basic framework schematic diagram of the present invention.
Embodiment
Below with reference to accompanying drawing, the present invention is described in detail.
Refer to Fig. 2, it is the basic framework schematic diagram of the unsettled circuit of solution sigma-delta analog to digital conversion circuit power up of the present invention.Described circuit comprises a plurality of integrators (for example integrator 1, integrator 2 for controlling ... integrator n, n is more than or equal to 1 integer) sigma-delta analog to digital conversion circuit, the unsettled circuit of described solution sigma-delta analog to digital conversion circuit power up comprises: a plurality of controlled device and a power sense circuit.
Described a plurality of controlled device is connected with an integrator of described sigma-delta analog to digital conversion circuit separately, for example, controlled device 1 connects integrator 1, and controlled device 2 connects integrator 2 ... controlled device n connects integrator n, obviously, the number of controlled device is determined according to the number of integrator.One integrator can only with one controlled device be connected, and for example, connects a controlled device between integrator input and output; In addition, an integrator also can be connected with a plurality of controlled device, for example, between the input of integrator and electronegative potential and between the output of integrator and electronegative potential, is connecting respectively a controlled device.And each controlled device can be controlled switch, include but not limited to: 1) relay; 2) transistor, for example, metal-oxide-semiconductor etc.; 3) regular tap etc.
Described power sense circuit and each controlled device (are controlled device 1, controlled device 2 ... controlled device n) be connected, for detection of the power supply situation that offers the power supply of described sigma-delta analog to digital conversion circuit to be controlled, to provide corresponding control signal according to detected result to each controlled device, make the working stability of described sigma-delta analog to digital conversion circuit to be controlled.As a preferred version, described power sense circuit can adopt electrify restoration circuit to detect the situation of power supply, but those skilled in the art should understand that, power sense circuit is not as limit, any can detect power supply whether the circuit in firm unlatching or positive power down all can be used as the power sense circuit in the present invention.
Foregoing circuit avoids the unsettled method of sigma-delta analog to digital conversion circuit power up to be: when power sense circuit detects the power supply during in power supply instability state that offers sigma-delta analog to digital conversion circuit to be controlled, described power sense circuit is to controlled device 1, controlled device 2 ... controlled device n sends the first control signal, so that integrator 1, integrator 2 ... integrator n resets; And when described power sense circuit detect offer the Power supply of sigma-delta analog to digital conversion circuit to be controlled stable after, described power sense circuit is to controlled device 1, controlled device 2 ... controlled device n sends the second control signal, so that integrator 1, integrator 2 ... integrator n, in integration operating state, realizes the working stability of described sigma-delta analog to digital conversion circuit to be controlled thus.
Say more in detail it, as shown in Figure 3, by power sense circuit, detect power supply and whether rigidly connect logical (being whether power supply powers on), if, described power sense circuit (for example sends the first control signal to each controlled device, switch closure signals), make each controlled switch closed, each integrator being connected with each controlled switch thus resets; And if power sense circuit does not detect the signal of power connection, power supply is in disconnecting, and power sense circuit continues to wait for.
Then, after power supply electrifying, whether power sense circuit detects power supply stable, if, to each controlled device, (for example send the second control signal, switch cut-off signal), each controlled switch is disconnected, each integrator being connected with each controlled switch thus enters normal integration state; And if power supply is also unstable, each controlled switch continues closure, and each integrator continues hold reset state.
Then, after power supply is stable, for a certain reason, suddenly power down, described power sense circuit detects after this power loss event, to each controlled device, sends the first control signal (for example, switch closure signals), make each integrator be returned to reset mode, until power supply enters integration state after stablizing again.And if do not have power loss event to occur, each integrator is proceeded proper integral.
A cascade (mash) the 2-2sigma-delta analog to digital conversion circuit of below take is more specifically described the unsettled circuit of solution sigma-delta analog to digital conversion circuit power up of the present invention as example.
As shown in Figure 4, mash 2-2sigma-delta analog to digital conversion circuit comprises: first order second order sigma-delta modulator, summing circuit 112, second level second order sigma-delta modulator and described first order second order sigma-delta modulator and second level second order sigma-delta modulator output signal are carried out to the noise cancellation logical block (being Noise cancel) of noise cancellation, it has the stability advantage of second-order modulator, can realize again the noise shaping effect of fourth-order modulator of Figure simultaneously.Wherein, first order second order sigma-delta modulator comprises: first First-order Integral circuit, second First-order Integral circuit and quantizer 107 serial connections form series circuit and the output of quantizer 107 carried out feeding back to after digital-to-analogue conversion the digital to analog converter (being DAC) 133 of first First-order Integral circuit, and first First-order Integral circuit comprises: integrator 103 and summing circuit 102 etc.; Second First-order Integral circuit comprises: integrator 106 and summing circuit 105 etc.Quantizer 107 is actual is exactly a simple comparator, generally speaking, in sigma-delta modulator, for comparator, conventionally there is no strict designing requirement, because the non-ideal characteristic of comparator all can be by loop filter noise shaping in addition.So a simple comparator that does not comprise preamplifier or imbalance bucking circuit just can meet the demands, as latched comparator is just relatively applicable to this application.Integrator 103, integrator 106 are all realized by switching capacity method.Summing circuit 102 is sent into integrator 103 the input signal Vin through scaler 101 (gain coefficient is a1) convergent-divergent and quantizer 107 through the difference of the signal of digital to analog converter (DAC) 133 and feedback path 108 (feedback factor is b1); Summing circuit 105 is sent into integrator 106 the output signal of the integrator 103 through scaler 105 (gain coefficient is a2) convergent-divergent and quantizer 107 through the difference of the signal of digital to analog converter (DAC) 133 and feedback path 109 (feedback factor is b2), when integrator 106 is output as timing, it is negative for integrator is output as, a positive reference signal of quantizer 107 feedbacks, send into summing circuit 102 and 105 through feedback path 108 and 109 respectively, so that convergent-divergent Vin and integrator 103 outputs and the quantizer 107 of convergent-divergent have fed back a positive reference signal and subtract each other.Equally, when integrator 106 is output as when negative, a negative reference signal of quantizer 107 feedbacks, passes through respectively feedback path 108 and 109, by summing circuit 102 and 105 will be added in respectively convergent-divergent Vin and convergent-divergent integrator 103 export and subtract each other with it.Therefore the integrator on these two rank has accumulated the poor of input signal and quantized output signal, and attempts to keep integrator output near zero.Integrator is output as zero and shows that input signal Vin and the difference that quantizes output are zero.In fact, the feedback that integrator and quantizer form forces the local mean values of the local average value trace input signal of quantizer output.Second level second order sigma-delta modulator is identical with first order second order sigma-delta modulator structure, is the gain coefficient c1 of integrator 115, feedback factor g1, and the gain coefficient c2 of integrator 118 is different with feedback factor g2.Summing circuit 112 is sent integrator 106 output signals through scaler 110 (gain coefficient d1) convergent-divergent with after the quantizer 107 output signal summations of scaler 111 convergent-divergents into second level second order sigma-delta modulator input, and coefficient d 1 and d2 affect the noise transmission function of modulator.Noise cancellation logical block is sent in the output of the output of first order second order sigma-delta modulator and second level second order sigma-delta modulator, after summing junction 131 is added as the output Vout of whole ADC.Logic shown in the square frame of Fig. 4 the right is exactly the structure of noise cancellation logical block.
Because above-mentioned mash 2-2sigma-delta analog to digital conversion circuit comprises 4 integrators, it is integrator 103, 106, 115, with 118, therefore the integrator of above-mentioned mash 2-2sigma-delta analog to digital conversion circuit is resetted and is controlled for realizing, corresponding control circuit can comprise: 4 controlled switchs, it is controlled switch 127, 128, 129, 130, wherein, controlled switch 127 is connected between the input and output of integrator 103, controlled switch 128 is connected between the input and output of integrator 106, controlled switch 129 is connected between the input and output of integrator 115, controlled switch 130 is connected between the input and output of integrator 118, controlled switch 127, 128, 129, 130 controlled ends separately connect power sense circuit, for example, the output of electrify restoration circuit (being por circuit) 132.Because por circuit 132 General Definitions become electronegative potential effective, so controlled switch 127,128,129,130 can manage to realize by PMOS.And if that por circuit 132 is defined as high potential is effective, controlled switch 127,128,129,130 can manage to realize by NMOS.
Refer to Fig. 5, it has shown in sigma-delta analog to digital conversion circuit power up and power down process how to avoid making modulator in saturated labile state because input signal is greater than quantification reference level again.Wherein, AVDD201 is power supply electrifying and power down waveform, Vrefp202 be just quantizing reference level (with respect to syntype bias signal) power on and power down process in waveform, Vrefn203 be negative quantity reference level (with respect to syntype bias signal) power on and power down process in waveform, Vcom204 be common-mode reference level power on and power down process in waveform, reset_n_por205 is the signal output waveform that por circuit 113 produces, por circuit 113 powers on and power down process for detection of supply voltage, after por circuit 113 detects power supply and is stabilized in a suitable scope, it can postpone to make reset_n_por become high level after the regular time (being Tdelay), the length of this set time must can make Vrefp, Vrefn and Vcom are established to the desired accuracy rating of ADC, also want to guarantee that digital circuit can correctly start simultaneously.The general time that all can add delay unit to determine by system of reset_n_por signal delay.When por circuit 113 detects supply voltage and powers on, the reset_n_por signal of its output can make to be connected to controlled switch 127,128,129,130 closures of each integrator input and output, the input and output short circuit of each integrator thus, thereby the voltage of each integrator is common mode electrical level, and each integrator is in reset mode.And powered on stablely when por circuit 113 detects power supply, and after Vrefp, Vrefn sum-product intergrator have all established, por circuit 113 is controlled controlled switchs 127,128,129,130 and is disconnected, and modulator returns to normal operating conditions thus, i.e. integrating function state.Just can there is not saturated labile state in modulator like this in power up.And when por circuit 113 detects power supply and occurs power down, it also can allow modulator in reset mode.AVDD detected lower than a default threshold value when por circuit 113, the output of por circuit 113 will step-down, thereby each integrator is resetted.This method has well solved the instability problem of power supply electrifying and power down process sigma-delta ADC.
Refer to Fig. 6, it is a simple low-power consumption por circuit schematic diagram again.Because por circuit is always in running order, so require low-power consumption, general electric current is all less than 1uA.PMOS pipe M5 and the electric resistance partial pressure on the left side form biasing and sample circuit, the quiescent dissipation of por circuit is introduced by biasing circuit and current mirror thereafter, and for keeping low-power consumption, all-in resistance is controlled at 5M Ω left and right, make branch current greatly about 300nA, the threshold value of AVDD sampled point Vd is at the threshold voltage V of M1
thn_M1(being about 0.7) located.Between AB and CD, all access Schmidt (schmitt) trigger to strengthen antijamming capability.Power on the stage, with power supply, from 0V, rise, when in low voltage, M1 grid voltage lower (Vd < 0.7V) and in cut-off state, M5 and M6 conducting, A point voltage rises with AVDD, and when AVDD is not enough to reach the state that makes the normal operation of schmitt trigger, B point can not provide normal inversion signal, while approaching 1V, schmitt trigger can work, and B changes 0 into, and now each inverter all can work.C point voltage is also that 0, E point voltage is 0.Then AVDD continues to rise, when its partial pressure value exceeds V
thn_M1time, M1 conducting, A point voltage=0, B point voltage=1 (being exactly AVDD), high level is delivered to E point need to experience certain time delay.The very large mos capacitance that C point M3 forms, and it drives inverter to adopt than pipe, the needed time delay of generation system.Through the time delay of certain hour, E is high level, M2 cut-off, and Vd can increase to the resistance between AVSS, so the raising of power supply sampling voltage ratio, when power supply AVDD falls, need to lowlyer just can cause M1 cut-off, and this has just strengthened the antijamming capability of por circuit.In the power down stage, power supply starts to decline from AVDD, as long as not cut-off of M1, the high level of exit point E just can not change.When AVDD decline causes M1 cut-off, it is high level that A point voltage is followed AVDD change, and B point is 0 so, and after certain delay, E point is also 0, and system resets.After this M2 conducting, power supply sampling voltage ratio reduces, and now power supply can not make E point current potential change as there is a small amount of rising interference level yet, has suppressed the interference on supply voltage.
It should be noted that, above-described embodiment is only as a specific embodiment of the present invention, but not for limiting the present invention, any other sigma-delta analog to digital conversion circuit all can adopt Method and circuits of the present invention to control.For example, for other low orders or high-order sigma-delta analog to digital conversion circuit, particularly for the sigma-delta ADC of the types such as stable low order (exponent number≤2) itself and mash2-1,, all can adopt method described above and circuit to make sigma-delta ADC working stability.Equally, the electrify restoration circuit of employing is also not Figure 6 shows that limit, but, take and directly adopts electrify restoration circuit that the SOC (system on a chip) at sigma-delta analog to digital conversion circuit place itself configured as good.
It should be noted that, why SOC (system on a chip) needs to configure electrify restoration circuit, this be because: along with the raising of chip integration, on one single chip, comprised increasing sophisticated functions module.Some of them module must be in certain known initial state when powering on or recover from energy-saving mode, thereby guarantees correctly executable operations.Therefore need to adopt electrification reset (Power On Reset) signal to reset to element circuits such as the oscillator in memory devices such as trigger, latch and register, counter, analog circuit, comparators, to guarantee that those circuit can correctly start in power up.
Specifically can be referring to Fig. 7, it is the basic framework schematic diagram of a SOC (system on a chip).As shown in the figure, described SOC (system on a chip) comprises function element 1 and function element 2, wherein, function element 1 and function element 2 can be oscillator in trigger, latch, register, counter, analog circuit or comparator etc., because function element 1 and function element 2 need power-on reset signal to reset, therefore, described SOC (system on a chip) need to be function element 1 and function element 2 configuration one electrify restoration circuits.And work as described SOC (system on a chip), (for example also comprise sigma-delta analog to digital conversion circuit described above, the sigma-delta analog to digital conversion circuit that comprises n integrator), time, so just can directly adopt this electrify restoration circuit to carry out control connection (is controlled device 1,2 in each controlled device of this each integrator of sigma-delta analog to digital conversion circuit ... n).
Certainly, the structure of SOC (system on a chip) is not limited with above-described embodiment, for example, can comprise other digital circuit or analog circuit etc., at this, exemplifies no longer one by one.
In sum, the unsettled Method and circuits of solution sigma-delta analog to digital conversion circuit power up of the present invention detects the generation of power supply electrifying or power down situation by electrify restoration circuit, and corresponding to provide reset enable signal to be connected to controlled switch between each integrator input and output side closed, avoid the integrator job insecurity causing because of power supply electrifying or power down.With respect to existing by the detection for integrator output signal or output state, this law does not need to set up testing circuit again, but the electrify restoration circuit that can directly utilize SOC (system on a chip) originally to configure, thus, can simplify the circuit structure of SOC (system on a chip), reduce the complexity of its circuit.And this law is directly power supply to be detected, therefore, when power supply power-fail, also can realize the reset of integrator, improved greatly the stability of sigma-delta analog to digital conversion circuit.
Above-described embodiment just lists expressivity principle of the present invention and effect is described, but not for limiting the present invention.Any person skilled in the art person all can without departing from the spirit and scope of the present invention, modify to above-described embodiment.Therefore, the scope of the present invention, should be as listed in claims.
Claims (19)
1. solve the unsettled circuit of sigma-delta analog to digital conversion circuit power up, it is characterized in that comprising:
At least one controlled device, is connected with an integrator of sigma-delta analog to digital conversion circuit to be controlled separately;
Power sense circuit, be connected with each controlled device, for detection of the power supply situation that offers the power supply of described sigma-delta analog to digital conversion circuit to be controlled, and to each controlled device, provide the first control signal when power supply instability being detected, each integrator is resetted, and after detection power supply is stable, to each controlled device, provide the second control signal, make each integrator enter integration operating state, thereby make the working stability of described sigma-delta analog to digital conversion circuit to be controlled; Described power supply instability state comprises the labile state that the power on labile state that causes and power down cause.
2. the unsettled circuit of solution sigma-delta analog to digital conversion circuit power up as claimed in claim 1, is characterized in that: described power sense circuit is electrify restoration circuit.
3. the unsettled circuit of solution sigma-delta analog to digital conversion circuit power up as claimed in claim 2, is characterized in that: described electrify restoration circuit is the configuration that the SOC (system on a chip) self at described sigma-delta analog to digital conversion circuit place to be controlled has had.
4. the unsettled circuit of solution sigma-delta analog to digital conversion circuit power up as claimed in claim 1, is characterized in that: controlled device comprises the controlled switch being connected between integrator input and output.
5. the unsettled circuit of solution sigma-delta analog to digital conversion circuit power up as claimed in claim 4, is characterized in that: described controlled switch is: relay, regular tap or metal-oxide-semiconductor.
6. the unsettled circuit of solution sigma-delta analog to digital conversion circuit power up as claimed in claim 1, is characterized in that: described sigma-delta analog to digital conversion circuit to be controlled is: a kind of in the low order sigma-delta analog to digital conversion circuit of exponent number≤2, cascade 2-1sigma-delta analog to digital conversion circuit and cascade 2-2sigma-delta analog to digital conversion circuit.
7. the unsettled circuit of solution sigma-delta analog to digital conversion circuit power up as claimed in claim 6, it is characterized in that: described 2-2sigma-delta analog to digital conversion circuit comprises: first order second order sigma-delta modulator, summing circuit, second level second order sigma-delta modulator, and described first order second order sigma-delta modulator and second level second order sigma-delta modulator output signal are carried out to the noise cancellation logical block of noise cancellation, wherein, described first order second order sigma-delta modulator and second level second order sigma-delta modulator all comprise separately: by first First-order Integral circuit, second First-order Integral circuit, form series circuit with quantizer serial connection, and the output of quantizer is carried out feeding back to after digital-to-analogue conversion the digital to analog converter of first First-order Integral circuit, described summing circuit is sent the output of second integrating circuit in the first order second order sigma-delta modulator through convergent-divergent with after the output summation of quantizer in the first order second order sigma-delta modulator of convergent-divergent into described second level second order sigma-delta modulator input.
8. one kind solves the unsettled method of sigma-delta analog to digital conversion circuit power up, it is characterized in that comprising step: when a power sense circuit detects the power supply during in power supply instability state that offers sigma-delta analog to digital conversion circuit to be controlled, described power sense circuit sends the first control signal to each controlled device that is connected to each modulator of described sigma-delta analog to digital conversion circuit to be controlled, so that each integrator resets; Described power supply instability state comprises the labile state that the power on labile state that causes and power down cause;
When described power sense circuit detect offer the Power supply of sigma-delta analog to digital conversion circuit to be controlled stable after, described power sense circuit sends the second control signal to each controlled device, so that each integrator in integration operating state, is realized the working stability of described sigma-delta analog to digital conversion circuit to be controlled thus.
9. the unsettled method of solution sigma-delta analog to digital conversion circuit power up as claimed in claim 8, it is characterized in that: when described power sense circuit detects the labile state that the power on labile state that causes or power down cause, send the first control signal.
10. solve as claimed in claim 8 or 9 the unsettled method of sigma-delta analog to digital conversion circuit power up, it is characterized in that: described power sense circuit is electrify restoration circuit.
The unsettled method of 11. solution sigma-delta analog to digital conversion circuit power up as claimed in claim 10, is characterized in that: described electrify restoration circuit is the configuration that the SOC (system on a chip) self at described sigma-delta analog to digital conversion circuit place to be controlled has had.
The unsettled method of 12. solution sigma-delta analog to digital conversion circuit power up as claimed in claim 8, is characterized in that: controlled device comprises and is connected to the input of integrator and the controlled switch between output.
The unsettled method of 13. solution sigma-delta analog to digital conversion circuit power up as claimed in claim 12, is characterized in that: controlled switch is metal-oxide-semiconductor, relay or regular tap.
The unsettled method of 14. solution sigma-delta analog to digital conversion circuit power up as claimed in claim 8, is characterized in that: described sigma-delta analog to digital conversion circuit to be controlled is: a kind of in the low order sigma-delta analog to digital conversion circuit of exponent number≤2, cascade 2-1sigma-delta analog to digital conversion circuit and cascade 2-2sigma-delta analog to digital conversion circuit.
The unsettled method of 15. solution sigma-delta analog to digital conversion circuit power up as claimed in claim 14, it is characterized in that: described 2-2sigma-delta analog to digital conversion circuit comprises: first order second order sigma-delta modulator, summing circuit, second level second order sigma-delta modulator, and described first order second order sigma-delta modulator and second level second order sigma-delta modulator output signal are carried out to the noise cancellation logical block of noise cancellation, wherein, described first order second order sigma-delta modulator and second level second order sigma-delta modulator all comprise separately: by first First-order Integral circuit, second First-order Integral circuit, form series circuit with quantizer serial connection, and the output of quantizer is carried out feeding back to after digital-to-analogue conversion the digital to analog converter of first First-order Integral circuit, described summing circuit is sent the output of second integrating circuit in the first order second order sigma-delta modulator through convergent-divergent with after the output summation of quantizer in the first order second order sigma-delta modulator of convergent-divergent into described second level second order sigma-delta modulator input.
16. 1 kinds of SOC (system on a chip), is characterized in that at least comprising:
Sigma-delta analog to digital conversion circuit;
Be connected to each controlled device of described each integrator of sigma-delta analog to digital conversion circuit;
At least one function element;
Electrify restoration circuit, power supply situation for detection of the power supply accessing, and to each controlled device and described at least one function element, provide the first control signal when power supply instability being detected, each integrator and at least one function element are resetted, and after detection power supply is stable, to each controlled device and at least one function element, provide the second control signal, make each integrator enter integration operating state, make at least one function element enter normal operating conditions simultaneously; Described power supply instability state comprises the labile state that the power on labile state that causes and power down cause.
17. SOC (system on a chip) as claimed in claim 16, is characterized in that: described function element comprises oscillator and the comparator in trigger, latch, register, counter, analog circuit.
18. SOC (system on a chip) as claimed in claim 16, is characterized in that: controlled device is to be connected to the input of integrator and the controlled switch between output.
19. SOC (system on a chip) as claimed in claim 16, is characterized in that: described sigma-delta analog to digital conversion circuit is: a kind of in the low order sigma-delta analog to digital conversion circuit of exponent number≤2, cascade 2-1sigma-delta analog to digital conversion circuit and cascade 2-2sigma-delta analog to digital conversion circuit.
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| CN103021357B (en) * | 2012-12-05 | 2015-08-05 | 江苏清投视讯科技有限公司 | A kind of LCD splicing large screen grouping power supply control apparatus |
| CN105007080B (en) * | 2015-07-01 | 2017-10-31 | 宁波大学 | A kind of method that sampling value stabilization is realized in analog-to-digital conversion |
| CN110007132B (en) * | 2019-05-08 | 2024-03-15 | 南京芯耐特半导体有限公司 | Low-voltage zero-power consumption CMOS power-on detection circuit |
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|---|---|---|---|---|
| CN1249891A (en) * | 1997-11-07 | 2000-04-05 | 皇家菲利浦电子有限公司 | Audio system comprising audio signal processing circuit |
| CN1799199A (en) * | 2003-07-18 | 2006-07-05 | 瑞典卓联半导体公司 | Integrator reset mechanism |
| CN101079634A (en) * | 2007-06-06 | 2007-11-28 | 华东师范大学 | A streamline structure digital sigma-delta modulator |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1249891A (en) * | 1997-11-07 | 2000-04-05 | 皇家菲利浦电子有限公司 | Audio system comprising audio signal processing circuit |
| CN1799199A (en) * | 2003-07-18 | 2006-07-05 | 瑞典卓联半导体公司 | Integrator reset mechanism |
| CN101079634A (en) * | 2007-06-06 | 2007-11-28 | 华东师范大学 | A streamline structure digital sigma-delta modulator |
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