CN102034874A - Non-volatile storage and manufacturing method thereof - Google Patents
Non-volatile storage and manufacturing method thereof Download PDFInfo
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- CN102034874A CN102034874A CN201010540309.1A CN201010540309A CN102034874A CN 102034874 A CN102034874 A CN 102034874A CN 201010540309 A CN201010540309 A CN 201010540309A CN 102034874 A CN102034874 A CN 102034874A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- 238000003860 storage Methods 0.000 title claims abstract description 12
- 239000004065 semiconductor Substances 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims description 22
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 20
- 229920002120 photoresistant polymer Polymers 0.000 claims description 20
- 238000005530 etching Methods 0.000 claims description 15
- 238000000034 method Methods 0.000 claims description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 10
- 229920005591 polysilicon Polymers 0.000 claims description 10
- 239000000377 silicon dioxide Substances 0.000 claims description 10
- 229910052751 metal Inorganic materials 0.000 claims description 8
- 239000002184 metal Substances 0.000 claims description 8
- 239000000203 mixture Substances 0.000 claims description 8
- 235000012239 silicon dioxide Nutrition 0.000 claims description 8
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 7
- 238000009413 insulation Methods 0.000 claims description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- 239000000956 alloy Substances 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 5
- 239000010937 tungsten Substances 0.000 claims description 5
- 229910052721 tungsten Inorganic materials 0.000 claims description 5
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 4
- 239000011810 insulating material Substances 0.000 claims description 4
- 238000002156 mixing Methods 0.000 claims description 4
- 229910045601 alloy Inorganic materials 0.000 claims description 2
- 239000012212 insulator Substances 0.000 claims description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 2
- 239000000463 material Substances 0.000 claims 2
- 230000005669 field effect Effects 0.000 abstract 1
- 230000015654 memory Effects 0.000 description 7
- 239000003292 glue Substances 0.000 description 4
- 238000001259 photo etching Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 230000010355 oscillation Effects 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 238000010301 surface-oxidation reaction Methods 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
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Abstract
The invention belongs to the technical field of a non-volatile storage below 50 nanometers, particularly to a non-volatile storage and a manufacturing method thereof. In the non-volatile storage, a collision ionization type metal-oxide-semiconductor field effect transistor (MOSFET) with a floating gate is used as a basic structure. By utilizing the non-volatile storage provided by the invention, the short channel effect can be overcome, and the driving current is improved while the subthreshold is restricted. The invention also provides the manufacturing method of the non-volatile storage. The non-volatile storage provided by the invention is very applicable to manufacture of integrated circuit chips, especially the manufacture of chips with low power consumption.
Description
Technical field
The present invention relates to a kind of non-volatility memorizer and manufacture method thereof, be specifically related to a kind of non-volatility memorizer and manufacture method thereof of using the collision ionization type MOSFET that is with floating boom to be used as basic structure, belong to the following technical field of non-volatile of 50 nanometers.
Background technology
Memory is broadly divided into two classes: volatile storage and non-volatility memorizer.Volatile storage loses the information in being stored in immediately when system closing, the power supply supply that it need continue is to keep data.Most random asccess memory (RAM) all belongs to volatile storage.Non-volatility memorizer still can continue to keep data message when system closing or non-transformer supply.Non-volatility memorizer can be divided into two classes again, charge trap type memory and floating gate type memory.In floating gate type memory, electric charge is stored in the floating boom, and they still can keep under the situation of non-transformer supply.Be stored in amount of charge in the floating boom and can influence the threshold voltage of device, the logical value 1 or 0 of state during distinguishing thus.
All floating gate type memories all have similar original unit framework, as shown in Figure 1, they all have stacked grid structure, and this stacked grid structure is arranged on the substrate 101, are formed by tunnel oxide 104, floating boom 105, dielectric layer 106 and 107 storehouses of control grid in regular turn.And, in the substrate 101 of grid structure both sides, be provided with source region 102 and drain region 103.
After the D.Kahng of Bell Laboratory in 1967 and S.M.Sze proposed the non-volatility memorizer of floating gate structure, the floating gate type non-volatility memorizer of the MOSFET structure of piling up based on grid just became main flow device on the semiconductor memory market with it in the advantage on capacity, cost and the power consumption.But, the minimum subthreshold value amplitude of oscillation (SS) of conventional MOS FET is limited in 60mv/dec, this has limited the operating rate of floating gate type memory, and, continuous increase along with the semiconductor chip integrated level, the channel length of MOSFET is also in continuous shortening, and when the channel length of MOSFET becomes very in short-term, the leakage current between its source, drain electrode rises rapidly with dwindling also of channel length.
Summary of the invention
The objective of the invention is to propose a kind of novel floating gate type non-volatility memorizer and preparation method thereof, overcoming short-channel effect, and improve the subthreshold value characteristic.
The non-volatility memorizer that the present invention proposes, the collision ionization type MOSFET that uses the band floating boom specifically comprises as basic structure:
A Semiconductor substrate;
The current channel zone that in described Semiconductor substrate, forms;
The drain region that a side in described current channel zone forms in described Semiconductor substrate with first kind of doping type;
The source region that the non-drain region side in described current channel zone forms in described Semiconductor substrate with second kind of doping type;
The ionization by collision zone that is used to produce ionizing collision that between described current channel zone and described source region, forms;
Cover the ground floor gate dielectric layer that described current channel zone forms;
The floating gate region that on described ground floor gate dielectric layer, forms with conductivity as charge-storage node;
Cover the second layer gate dielectric layer that described floating gate region forms;
The control grid that on described second layer gate dielectric layer, forms.
Further, described Semiconductor substrate is monocrystalline silicon or is the silicon (SOI) on the insulator.Described ground floor, second layer gate dielectric layer are formed by the insulating material of silicon dioxide, silicon nitride, silicon oxynitride or high-k.Described floating gate region is formed by the polysilicon, tungsten, titanium nitride or the alloy material that mix.
Further, described first kind of doping type is the n type, and described second kind of doping type is the p type; Perhaps, described first kind of doping type is the p type, and described second kind of doping type is the n type.
Simultaneously, the invention allows for the manufacture method of above-mentioned non-volatility memorizer, comprising:
A Semiconductor substrate is provided;
Form the ground floor photoresist;
Mask, exposure, etching form the figure that need mix in the drain region;
Ion injects the drain region that forms first kind of doping type;
Divest the ground floor photoresist;
Form the ground floor insulation film;
Form the ground floor conductive film;
Form second layer photoresist;
Mask, exposure, etching form the floating boom of device;
Divest second layer photoresist;
Form second layer insulation film;
Form second layer conductive film;
Form the 3rd layer photoetching glue;
Mask, exposure, etching form the control grid of device;
Divest the 3rd layer photoetching glue;
Form the 4th layer photoetching glue;
Mask, exposure, etching form the figure that need mix in the source region;
Ion injects the source region that forms second kind of doping type;
Divest the 4th layer photoetching glue;
Form three-layer insulated film;
Form the layer 5 photoresist;
Mask, exposure, etching form contact hole;
Divest the layer 5 photoresist;
Form Metal Contact.
Further, described ground floor, second layer insulation film are the insulating material of silicon dioxide, silicon nitride, silicon oxynitride or high-k.Described three-layer insulated film is silicon dioxide or is silicon nitride.Polysilicon, tungsten, titanium nitride or the alloy material of described ground floor conductive film for mixing.Described second layer conductive film is metal, alloy or the polysilicon for mixing.
Non-volatility memorizer proposed by the invention uses the collision ionization type MOSFET of band floating boom to be used as basic structure, can overcome short-channel effect, and improve drive current when suppressing the subthreshold value amplitude of oscillation.Non-volatility memorizer proposed by the invention is highly suitable for the manufacturing of integrated circuit (IC) chip, particularly the manufacturing of low-power consumption chip.
Description of drawings
Fig. 1 is a kind of sectional view of a kind of floating gate type non-volatility memorizer of prior art.
Fig. 2 is the sectional view of an embodiment of non-volatility memorizer proposed by the invention.
Fig. 3 to Fig. 9 is preparation technology's flow chart of an embodiment of non-volatility memorizer proposed by the invention.
Embodiment
The present invention is further detailed explanation below in conjunction with accompanying drawing and embodiment, in the drawings, for convenience of description, amplifies or dwindled the thickness in layer and zone, shown in size do not represent actual size.Although the actual size that reflects device that these figure can not entirely accurate, their zones that still has been complete reflection and form mutual alignment between the structure, particularly form between the structure up and down and neighbouring relations.
Reference diagram is the schematic diagram of idealized embodiment of the present invention, and embodiment shown in the present should not be considered to only limit to the given shape in zone shown in the figure, but comprises resulting shape, the deviation that causes such as manufacturing.For example the curve that obtains of etching has crooked or mellow and full characteristics usually, but in embodiments of the present invention, all represents with rectangle, and the expression among the figure is schematically, but this should not be considered to limit the scope of the invention.Simultaneously in the following description, employed term substrate can be understood as and comprises the just Semiconductor substrate in processes, may comprise other prepared thin layer thereon.
Fig. 2 is used as an embodiment of the non-volatility memorizer of basic structure for the collision ionization type MOSFET of use band floating boom proposed by the invention, and it is the sectional view along this device current orientation.As shown in Figure 2, stacked grid is formed on the substrate 200, comprises tunneling medium layer 204, floating boom 205, dielectric layer 206 and control grid 207 in regular turn.In the substrate 200 of grid structure both sides, be provided with drain region 201 and source region 202.Insulating barrier 208 is passivation layers of this device, and they separate described device and other device, and protects described device not to be subjected to the influence of external environment.Metal level 209,210 and 211 is respectively drain electrode, gate electrode and the source electrode of this device.
Before writing data, floating boom 205 is uncharged.When drain and gate is applied suitable bias voltage, can accumulate minority carrier (electronics or hole) and form inversion layer 203 near the substrate surface below the grid, thereby form current channel.Simultaneously, produce high electric field in the part of the substrate between current channel and source region 202 (ionization by collision zone 202, its length is such as being 40 nanometers), thereby generation avalanche current, electronics is injected in the floating boom 205, influences the threshold voltage of device, the logical value 1 or 0 of state during distinguishing thus.
The collision ionization type MOSFET of use band floating boom disclosed in this invention is used as the non-volatility memorizer of basic structure can be by a lot of method manufacturings, the following stated be an embodiment technological process of making non-volatility memorizer as shown in Figure 2.
At first, deposit one deck photoresist 330 on the Semiconductor substrate 300 of light dope p type, mask, exposure, etching form the figure that need mix in the drain region then, then inject the n type drain region 303 that forms device by ion, as shown in Figure 3.
After divesting photoresist 330, at the surface oxidation of substrate 300 growth layer of silicon dioxide film 301, the thickness of silica membrane 301 is such as being 10 nanometers, the polysilicon membrane 302 of deposit one deck heavy doping n type foreign ion then, as shown in Figure 4.Next, deposit one deck photoresist, mask, exposure, etch polysilicon film 302 forms the floating boom of devices then, divests behind the photoresist as shown in Figure 5.
Next, deposit one deck insulation film 304, such as being silicon dioxide, thickness is 10 nanometers.Continue deposit layer of conductive film 305, such as the polysilicon of heavy doping n type, as shown in Figure 6.Then deposit one deck photoresist, and mask, exposure, etch polysilicon film 305 form the control grid of device, divest photoresist then, as shown in Figure 7.
Next, the photoresist that deposit one deck is new, mask, exposure, etching form the figure that need mix in the source region then, and form the p type source region 306 of device by ion implantation technology, divest behind the photoresist as shown in Figure 8.
At last, deposit forms insulation film 307, can or be silicon nitride for silica, and deposit one deck photoresist, and mask, exposure, etching form through-hole structure then.After divesting remaining photoresist, deposit layer of metal 308, metal 308 is such as being aluminium or tungsten, etching forms Metal Contact then, as shown in Figure 9.
As mentioned above, under the situation that does not depart from spirit and scope of the invention, can also constitute many very embodiment of big difference that have.Should be appreciated that except as defined by the appended claims, the invention is not restricted at the instantiation described in the specification.
Claims (10)
1. non-volatility memorizer is characterized in that comprising:
A Semiconductor substrate;
The current channel zone that in described Semiconductor substrate, forms;
The drain region that a side in described current channel zone forms in described Semiconductor substrate with first kind of doping type;
The source region that the non-drain region side in described current channel zone forms in described Semiconductor substrate with second kind of doping type;
The ionization by collision zone that is used to produce ionizing collision that between described current channel zone and described source region, forms;
Cover the ground floor gate dielectric layer that described current channel zone forms;
The floating gate region that on described ground floor gate dielectric layer, forms with conductivity as charge-storage node;
Cover the second layer gate dielectric layer that described floating gate region forms;
The control grid that on described second layer gate dielectric layer, forms.
2. non-volatility memorizer according to claim 1 is characterized in that, described Semiconductor substrate is monocrystalline silicon or is the silicon on the insulator.
3. non-volatility memorizer according to claim 1 is characterized in that, described ground floor, second layer gate dielectric layer material are the insulating material of silicon dioxide, silicon nitride, silicon oxynitride or high-k.
4. non-volatility memorizer according to claim 1 is characterized in that, described floating gate region is formed by the polysilicon, tungsten, titanium nitride or the alloy material that mix.
5. non-volatility memorizer according to claim 1 is characterized in that, described first kind of doping type is the n type, and described second kind of doping type is the p type; Perhaps described first kind of doping type is the p type, and described second kind of doping type is the n type.
6. the manufacture method of a non-volatility memorizer as claimed in claim 1 is characterized in that concrete steps comprise:
A Semiconductor substrate is provided;
Form the ground floor photoresist;
Mask, exposure, etching form the figure that need mix in the drain region;
Ion injects the drain region that forms first kind of doping type;
Divest the ground floor photoresist;
Form the ground floor insulation film;
Form the ground floor conductive film;
Etching ground floor conductive film forms the floating boom of device;
Form second layer insulation film;
Form second layer conductive film;
Etching second layer conductive film forms the control grid of device;
Form second layer photoresist;
Mask, exposure, etching form the figure that need mix in the source region;
Ion injects the source region that forms second kind of doping type;
Divest second layer photoresist;
Form three-layer insulated film;
The three-layer insulated film of etching forms contact hole;
Form Metal Contact.
7. the manufacture method of non-volatility memorizer according to claim 6 is characterized in that, described ground floor, second layer insulating film material are the insulating material of silicon dioxide, silicon nitride, silicon oxynitride or high-k.
8. the manufacture method of non-volatility memorizer according to claim 6 is characterized in that, polysilicon, tungsten, titanium nitride or the alloy material of described ground floor conductive film for mixing.
9. the manufacture method of non-volatility memorizer according to claim 6 is characterized in that, described second layer conductive film is metal, alloy, perhaps the polysilicon for mixing; Described three-layer insulated film is silicon dioxide or is silicon nitride.
10. the manufacture method of non-volatility memorizer according to claim 6 is characterized in that, described first kind of doping type is the n type, and described second kind of doping type is the p type; Perhaps described first kind of doping type is the p type, and described second kind of doping type is the n type.
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| CN201010540309.1A CN102034874A (en) | 2010-11-11 | 2010-11-11 | Non-volatile storage and manufacturing method thereof |
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| CN201010540309.1A CN102034874A (en) | 2010-11-11 | 2010-11-11 | Non-volatile storage and manufacturing method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112259680A (en) * | 2020-10-10 | 2021-01-22 | 北京大学 | Non-volatile read-only memory and preparation method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030137006A1 (en) * | 1999-12-17 | 2003-07-24 | Chartered Semiconductor Manufacturing Ltd. | Low voltage programmable and erasable Flash EEPROM |
| CN1832200A (en) * | 2005-03-10 | 2006-09-13 | 台湾积体电路制造股份有限公司 | Semiconductor apparatus and floating grid memory |
| CN101373634A (en) * | 2007-08-20 | 2009-02-25 | 隆智半导体公司 | CMOS logic compatible non-volatile memory cell structure, operation, and array configuration |
| US20090289298A1 (en) * | 2008-04-28 | 2009-11-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Self-aligned impact-ionization field effect transistor |
-
2010
- 2010-11-11 CN CN201010540309.1A patent/CN102034874A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030137006A1 (en) * | 1999-12-17 | 2003-07-24 | Chartered Semiconductor Manufacturing Ltd. | Low voltage programmable and erasable Flash EEPROM |
| CN1832200A (en) * | 2005-03-10 | 2006-09-13 | 台湾积体电路制造股份有限公司 | Semiconductor apparatus and floating grid memory |
| CN101373634A (en) * | 2007-08-20 | 2009-02-25 | 隆智半导体公司 | CMOS logic compatible non-volatile memory cell structure, operation, and array configuration |
| US20090289298A1 (en) * | 2008-04-28 | 2009-11-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Self-aligned impact-ionization field effect transistor |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112259680A (en) * | 2020-10-10 | 2021-01-22 | 北京大学 | Non-volatile read-only memory and preparation method thereof |
| CN112259680B (en) * | 2020-10-10 | 2022-07-26 | 北京大学 | Non-volatile read-only memory and preparation method thereof |
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Application publication date: 20110427 |