CN101989460A - Improved silicon nitride non-volatile memory and implementation method thereof - Google Patents
Improved silicon nitride non-volatile memory and implementation method thereof Download PDFInfo
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- CN101989460A CN101989460A CN2009100559429A CN200910055942A CN101989460A CN 101989460 A CN101989460 A CN 101989460A CN 2009100559429 A CN2009100559429 A CN 2009100559429A CN 200910055942 A CN200910055942 A CN 200910055942A CN 101989460 A CN101989460 A CN 101989460A
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Abstract
The invention discloses a method for reading word line data bit level state 11 of silicon nitride non-volatile memory, including the following steps: low level terminal threshold VTLH of each word line level state 11 on silicon nitride non-volatile memory NROM is obtained by measuring in advance; gate voltage corresponding to the word line is selected according to the VTLH obtained by measuring in advance, the gate voltage causes the difference of the VTLH of the word line and reference value Ref11 of the level state 11 to be a preset fixed value, the gate voltage corresponding to the word line is applied to the word line, and data of word line data bit is read. The invention also discloses an improved silicon nitride non-volatile memory. The scheme of the invention can greatly improve success rate of reading word line data bit level state 11.
Description
Technical field
The present invention relates to SIC (semiconductor integrated circuit) manufacturing technology field, particularly improved silicon nitride nonvolatile memory and its implementation.
Background technology
Silicon nitride nonvolatile memory (NROM) is a kind of novel nonvolatile read-only memory.Structurally, it replaces floating boom in the conventional flash memory with silicon nitride.Because the insulativity of silicon nitride can make the two ends of silicon nitride become independently storage unit, i.e. the dibit storage unit by controlling the two ends that electronics and hole be injected into silicon nitride.And, can realize the high storage density of every unit 4 bits in conjunction with every unit multilayer current potential (MLC) technology.
Fig. 1 is the structural representation of the storage unit of NROM.Bit line 102 and bit line 103 are the adjacent bit lines that embed the upper surface of wafer silicon substrate, and between the bit line and on the silicon base upper surface is word line 101.Word line 101 comprises polysilicon layer from top to bottom, goes up oxide skin(coating), nitride layer and following oxide skin(coating), and described oxide skin(coating), nitride layer and the following oxide skin(coating) gone up often is called the O-N-O layer for short, as the gate dielectric layer of MOS transistor.The boundary of bit line and adjacent word line is called data bit.Each data bit comprises two bits, and a storage unit has two data bit, can realize the high storage density of 4 bits altogether.
Fig. 2 is the level state distribution schematic diagram of a data bit of storage unit.As can be seen, the data bit of NROM can be in four kinds of level states from the low level to the high level, successively corresponding data " 11 ", " 01 ", " 00 " and " 10 " for ease of describing, will abbreviate level state " 11 " corresponding to the level state of data " 11 " as.It is pointed out that the VT that mentions not is the cut-in voltage of this storage unit here, but its minimum gate voltage (VCCR) when being in low level with respect to reference unit.And each level state is not single level value, but a threshold distribution of level value (Voltage Threshold, VT).In the VT distribution plan, be the minimum VT value defined in the level state " 11 " low level minimum threshold (VTLL), maximum VT value defined is low level max-thresholds (VTLH).In the data of in reading a data bit, storing, actual is the level value of measuring this data bit, the reference value (Ref11) of this level value and predefined level state " 11 " is compared, be lower than 11 reference value and just the data of this data bit storage be read as " 11 " if measure level value.Yet quality test results shows: the NROM product has 28% approximately owing to reading the yield loss that level state " 11 " failure causes.
By analyzing, the basic reason that the NROM product reads level state " 11 " failure is: have bigger spacing between the initial VT of different word lines distributes.Figure 3 shows that level state " 11 " the VT distribution plan of a plurality of memory cell data position among the same NROM, wherein the corresponding storage unit of each bar curve.The nearly 600mV of VTLH distributed area of different pieces of information position is wherein greatly from being positioned at and the adjacent edge word lines of shallow trench isolation region (STI).This mainly is the restriction that comes from technological ability, and when read-write word line and the interference of bit line etc.As shown in Figure 2, in the design of NROM product, interval width between level state " 11 " and " 01 " is 900mV, and the interval width between VTLH and the Ref11 is 650mV, and such setting can make the accuracy that reads level state " 11 " satisfy the demand.But in the CP test, the interval width of the qualification between VTLH and the Ref11 only is 300mV.And interval width all can be failed when reading level state " 11 " less than all data bit of 300mV between the Ref11, serious reduction the yield of product.
Summary of the invention
In view of this, the objective of the invention is to, propose a kind of method and improved silicon nitride nonvolatile memory that reads the word line data bit level state 11 of silicon nitride nonvolatile memory, can greatly improve the success ratio that reads word line data bit level state 11.
A kind of method that reads the word line data bit level state 11 of silicon nitride nonvolatile memory that the present invention proposes comprises the steps:
Measure the upward low level max-thresholds VTLH of each word line level state 11 of silicon nitride nonvolatile memory NROM in advance;
Select the gate voltage of this word line correspondence according to the VTLH that measures in advance, described gate voltage makes that the difference of reference value Ref11 of the VTLH of described word line and level state 11 is predefined fixed value, and the gate voltage of word line correspondence is applied on the described word line, and read the data of described word line data position.
The described VTLH that measures each word line level state 11 on the silicon nitride nonvolatile memory in advance comprises:
A, from the word line of NROM, select a word line as wordline current;
B, be applied to that gate voltage is set to expect that VTLH deducts first threshold on the wordline current, and read the data of word line;
C, judge whether the probability of the failure of reading of data " 11 " meets or exceeds second threshold value, if then raising is applied to gate voltage on the wordline current, and continues execution in step C; Otherwise the gate voltage that is applied on the wordline current is the VTLH of wordline current, and execution in step D;
D, judge whether to also have unmeasured word line, if then go to steps A, otherwise finish the step of the VTLH of each word line level state 11 of measuring N ROM.
Preferably, described first threshold is the arbitrary value in 500 ± 200mV scope.
Preferably, described second threshold value is the arbitrary value in 0 to 5% scope, but does not comprise 0.
Preferably, described predefined fixed value is the arbitrary value between the 350mV to 900mV.
Preferably, in described NROM, set in advance a dedicated memory;
The described VTLH that will measure in advance is applied on the described word line as the gate voltage of this word line and comprises the steps:
The VTLH of described each word line that measures is in advance deducted the acquiescence gate voltage respectively, obtain voltage difference, and described voltage difference is stored in the described dedicated memory corresponding to each word line;
To give tacit consent to gate voltage, to add the above voltage difference after-applied to described voltage difference corresponding word lines.
The embodiment of the invention also proposes a kind of improved silicon nitride nonvolatile memory, on the basis of existing silicon nitride nonvolatile memory, further comprises following functional unit:
The voltage difference storage unit is used to store the voltage difference corresponding to each word line;
The gate voltage adjustment unit is used for the acquiescence gate voltage is added the voltage difference corresponding to arbitrary word line that the above voltage difference storage unit is stored, as the adjusted gate voltage of described word line.
As can be seen from the above technical solutions, measure the VTLH of every word line reality, according to the VTLH value of every word line, different word lines is adopted different VCCR values then, just can make the VTLH of all word lines and the fixed value that the interval width between the Ref11 is design.The problem of level state " 11 " failure so can not occur reading, thereby eliminate original because of reading the problem of the yield reduction that level state " 11 " failure causes.
Description of drawings
Figure 1 shows that the structural representation of a storage unit of silicon nitride nonvolatile memory;
Figure 2 shows that the level state distribution schematic diagram of a data bit of storage unit;
Figure 3 shows that level state " 11 " the VT distribution plan of a plurality of memory cell data position among the same NROM;
A kind of process flow diagram that reads the word line data bit level state 11 of silicon nitride nonvolatile memory that Fig. 4 proposes for the present invention;
Fig. 5 a applies on three word lines of same NROM for acquiescence VCCR, and the VT of the level state 11 that obtains distributes;
Fig. 5 b is that adjusted VCCR applies on three word lines of same NROM, and the VT of the level state 11 that obtains distributes;
Fig. 5 c is that adjusted VCCR applies on three word lines of same NROM, and carries out initial VT distribution optimization and handle, and the VT of the level state 11 that obtains distributes.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, the present invention is further elaborated below in conjunction with accompanying drawing.
The method that the present invention proposes the selectivity gate voltage solves in this NROM product owing to read the yield loss that level state " 11 " failure causes.
A kind of method that reads the word line data bit level state 11 of silicon nitride nonvolatile memory that the present invention proposes as shown in Figure 4, comprises the steps:
Step 401: measure the VTLH that silicon nitride nonvolatile memory NROM goes up each word line level state 11 in advance;
Step 402: select the gate voltage of this word line correspondence according to the VTLH that measures in advance, and the gate voltage of word line correspondence is applied on the described word line, and read the data of described word line data position.
In the prior art, the NROM product is when reading and writing, and all word lines are all used identical VCCR value.In the rule of the selectivity gate voltage (VCCR) that the present invention proposes, each root word line all is used as minimum array element, and measures the VTLH of every word line reality.Then according to the VTLH value of every word line, different word lines is adopted different VCCR values, just can make the VTLH and the interval width between the Ref11 of all word lines be the designs fix value, the 300mV that this fixed value adopts in should testing greater than CP, but should be less than or equal to 900mV.The problem of level state " 11 " failure so can not occur reading, thereby eliminate original because of reading the problem of the yield reduction that level state " 11 " failure causes.
Adopt selectivity VCCR method, at first will measure the VTLH that NROM goes up each word line.This can (Error Detect, method ED) be finished by error-detecting.Specific practice is: the VCCR initial value of setting every word line reads the data on the word line for the difference that expection VTLH deducts the first threshold gained; Whether meet or exceed second threshold value if read the probability of level state 11 failures on this word line, if, then increase the VCCR on the word line, the probability that reads level state 11 failures on this word line is less than described second threshold value, and the VCCR that adds on the word line is exactly the VTLH of this word line at this moment.Wherein, first threshold can be set to the arbitrary value in 500 ± 200mV scope, and second threshold value is the arbitrary value in 0 to 5% scope, but does not comprise 0.
According to the VTLH of every word line, select the VCCR of this word line correspondence just can make all word lines all obtain the interval width that designing institute needs.Specifically, establish the pairing VCCR writing of i word line VCCRi and then be applied on the word line i as VCCRi, the VTLH of word line i and the difference of Ref11 are predefined fixedly difference.This fixedly difference can be taken as 350mV to the arbitrary value between the 900mV.Then, the VCCR of every pairing VCCR of word line and acquiescence is subtracted each other, obtain a voltage difference+/-Δ V, and the voltage difference of every word line all is stored in the particular memory region on the NROM.In reading of data, write data (program) and initial VT distribution optimization (compaction) in, all will with acquiescence VCCR+/-Δ V replaces giving tacit consent to VCCR itself.The VTLH that so just can make all word lines promptly guarantees to have between VTLH and the Ref11 enough interval widths correctly to read 11 bits at same position.Fig. 5 a to Fig. 5 c can explain well and adopt after the selectivity VCCR, and the distribution range from original broad of the VTLH of different word lines focuses on similar any position.Select three word lines of NROM for use, be called WLA, WLB and WLC, VCCR is applied on these three word lines with acquiescence, and the VT of the level state 11 that obtains distributes shown in Fig. 5 a.According to method of the present invention acquiescence VCCR is adjusted, adjusted VCCR is applied to respectively on these three word lines, the VT of the level state 11 that obtains distributes shown in Fig. 5 b.Compaction is to be exactly threshold voltage (Vth) program to position that VT is higher in advance that the method that lower some bits of initial VT inject (HCI) with thermoelectron is improved their reality, but less than VTLH, make initial VT distribution narrow, as the process of Fig. 5 b to Fig. 5 c.Can reduce the dispersion of distribution of initial VT like this, and the VT dispersion of distribution of program later 01 is also narrowed down, thereby further increase the interval width between 11 and 01.
The embodiment of the invention also proposes a kind of improved silicon nitride nonvolatile memory, and this NROM is exactly on existing NROM basis, further increases as lower unit:
The voltage difference storage unit is used to store the voltage difference corresponding to each word line.
The gate voltage adjustment unit is used for the acquiescence gate voltage is added the voltage difference corresponding to arbitrary word line that the above voltage difference storage unit is stored, as the adjusted gate voltage of described word line.
Before NROM dispatches from the factory, measure the upward VTLH of each word line level state 11 of NROM, select the gate voltage of this word line correspondence according to the VTLH that measures in advance, the gate voltage values of selected gate voltage and acquiescence is subtracted each other, obtain voltage difference and be stored in the voltage difference storage unit.So just can realize being fixed value at interval between the VTLH of level state 11 of each word line and the reference value Ref11.
Adopt selectivity VCCR method of the present invention, reading in 11, with regard to not can because of 11 and reference11 between at interval not enough and fail.And because the interval width between the VTLH of all word lines and the Ref11 all is a needed fixed value of when design, we just can suitably reduce this interval width value, make whole VT distribution narrow.Do like this and can shorten program number and time, reduce problems such as bit line interference, help promoting the performance of storer.
The above only is preferred embodiment of the present invention, not in order to restriction the present invention, all any modifications of being done within the spirit and principles in the present invention, is equal to and replaces and improvement etc., all should be included within protection scope of the present invention.
Claims (7)
1. a method that reads the word line data bit level state 11 of silicon nitride nonvolatile memory comprises the steps:
Measure the upward low level max-thresholds VTLH of each word line level state 11 of silicon nitride nonvolatile memory NROM in advance;
Select the gate voltage of this word line correspondence according to the VTLH that measures in advance, described gate voltage makes that the difference of reference value Ref11 of the VTLH of described word line and level state 11 is predefined fixed value, and the gate voltage of word line correspondence is applied on the described word line, and read the data of described word line data position.
2. method according to claim 1 is characterized in that, the described VTLH that measures each word line level state 11 on the silicon nitride nonvolatile memory in advance comprises:
A, from the word line of NROM, select a word line as wordline current;
B, be applied to that gate voltage is set to expect that VTLH deducts first threshold on the wordline current, and read the data of word line;
C, judge whether the probability of the failure of reading of data " 11 " meets or exceeds second threshold value, if then raising is applied to gate voltage on the wordline current, and continues execution in step C; Otherwise the gate voltage that is applied on the wordline current is the VTLH of wordline current, and execution in step D;
D, judge whether to also have unmeasured word line, if then go to steps A, otherwise finish the step of the VTLH of each word line level state 11 of measuring N ROM.
3. method according to claim 2 is characterized in that, described first threshold is the arbitrary value in 500 ± 200mV scope.
4. according to claim 2 or 3 described methods, it is characterized in that described second threshold value is the arbitrary value in 0 to 5% scope, but does not comprise 0.
5. according to claim 2 or 3 described methods, it is characterized in that described predefined fixed value is the arbitrary value between the 350mV to 900mV.
6. method according to claim 1 is characterized in that, sets in advance a dedicated memory in described NROM;
The described VTLH that will measure in advance is applied on the described word line as the gate voltage of this word line and comprises the steps:
The VTLH of described each word line that measures is in advance deducted the acquiescence gate voltage respectively, obtain voltage difference, and described voltage difference is stored in the described dedicated memory corresponding to each word line;
To give tacit consent to gate voltage, to add the above voltage difference after-applied to described voltage difference corresponding word lines.
7. an improved silicon nitride nonvolatile memory is characterized in that, comprising:
The voltage difference storage unit is used to store the voltage difference corresponding to each word line;
The gate voltage adjustment unit is used for the acquiescence gate voltage is added the voltage difference corresponding to arbitrary word line that the above voltage difference storage unit is stored, as the adjusted gate voltage of described word line.
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| CN106935266A (en) * | 2017-03-15 | 2017-07-07 | 珠海格力电器股份有限公司 | Control method, device and system for reading configuration information from memory |
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| US7426139B2 (en) * | 2006-11-02 | 2008-09-16 | Macronix International Co., Ltd. | Dynamic program and read adjustment for multi-level cell memory array |
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| CN106935266A (en) * | 2017-03-15 | 2017-07-07 | 珠海格力电器股份有限公司 | Control method, device and system for reading configuration information from memory |
| CN106935266B (en) * | 2017-03-15 | 2023-08-25 | 珠海格力电器股份有限公司 | Control method, device and system for reading configuration information from memory |
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