CN101989244A

CN101989244A - Signal conversion device and method as well as communication equipment

Info

Publication number: CN101989244A
Application number: CN 200910161051
Authority: CN
Inventors: 朱晓明
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2009-08-05
Filing date: 2009-08-05
Publication date: 2011-03-23
Anticipated expiration: 2029-08-05
Also published as: CN101989244B

Abstract

The embodiment of the invention provides a signal conversion device and method as well as communication equipment. The signal conversion device comprises an LPC (Low Pin Count) bus interface unit, a register configuration unit and a UART (Universal Asynchronous Receiver Transmitter) unit, wherein the LPC bus interface unit is used for performing protocol analysis on signals from an LPC bus and outputting local signals through a local bus, and the local signals comprise a control signal, an address signal and a data signal; the register configuration unit is used for configuring registers of the UART unit according to the local signals; the registers of the UART unit are allocated in a memory address space and an I/O address space; and the UART unit is used for converting data from the LPC bus into serial data according to the local signals and the values of configured registers of the UART unit and then outputting the serial data through a UART interface or outputting the serial data received by the UART interface to the LPC bus through the local signals. The embodiment of the invention can simplify the configuration process of the registers of the USRT unit.

Description

Signal conversion device and method and communication equipment

Technical Field

The invention relates to the field of communication, in particular to a device and a method for converting an LPC bus into a UART interface and communication equipment.

Background

Serial communication interface protocols provide the simplest standard serial interface for data communication and are therefore widely used on many devices. Electronic design engineers often involve human-computer interaction when debugging complex embedded systems, and need to utilize embedded system's serial ports as the control cabinet (console) in the human-computer interaction process to this embedded system is controlled through the serial ports to the host computer, for example through serial ports printed information, therefore almost all embedded systems need the serial ports. In the application of the telecommunication field, the serial port is used for local debugging, and a Baseboard Management Controller (BMC) also communicates and controls the embedded system through the serial port.

The main application scenario of the X86 architecture processor is a microcomputer, a server or a workstation, and has begun to be applied to the embedded and communication fields, but the X86 architecture processor manufacturers have gradually no longer provided UART (Universal Asynchronous Receiver and Transmitter) interface in South Bridge (South Bridge), but instead, connected to Super I/O chip (Super I/O ASIC) by using LPC bus (Low Pin count bus) of South Bridge, which provides various Low-speed interfaces (e.g., parallel port, serial port, floppy drive, PS2, keyboard, mouse, printer, etc. …) required by the microcomputer.

Referring to fig. 1, fig. 1 is a diagram illustrating a hardware connection for implementing UART communication by using a super I/O chip in the prior art. As shown in fig. 1, for a PC or an embedded system, the super I/O chip is directly connected to the south bridge chip through the LPC BUS, and a floppy disk interface, a parallel port, a serial port, a keyboard controller, an X-BUS, and the like are provided through the super I/O chip. But the super I/O chip has up to 128 pins and is bulky. Meanwhile, the scheme is also connected with a flash with an LPC interface on an LPC bus, and the flash is used for storing a Basic Input Output System (BIOS) of the whole software and hardware system.

In the process of implementing the invention, the inventor finds that the prior art has at least the following defects:

when various interfaces (including UART interfaces) are communicated with an LPC bus in the super I/O chip, the configuration of parameters related to each interface can be completed only by operating an Index Port register and a Data Port register in the super I/O chip. When the system is started, if serial Port communication is needed, BIOS is needed to configure the inside of the super I/O chip, the configuration state of the super I/O chip is entered, and writing operation is carried out on an Index Port register and a Data Port register. Only if the serial port interface is firstly distributed to the internal bus as a logic device, then the I/O address of the serial port register can be accessed, and the read-write operation is carried out on the serial port controller, so that the configuration process is relatively complex.

Disclosure of Invention

The embodiment of the invention provides a signal conversion device, a signal conversion method and communication equipment.

In one aspect, an embodiment of the present invention provides a signal conversion apparatus, where the apparatus includes: LPC bus interface unit, register configuration unit, UART unit; the LPC bus interface unit is used for carrying out protocol analysis on signals from an LPC bus and outputting local signals through a local bus, and the local signals comprise control signals, address signals and data signals; the register configuration unit is used for configuring a register of the UART unit according to the local signal; the register of the UART unit is distributed in an internal memory address space and an I/O address space; and the UART unit is used for converting the data from the LPC bus into serial data according to the local signal and the value of a register of the UART unit after configuration and then outputting the serial data through a UART interface or outputting the serial data received from the UART interface to the LPC bus according to the local signal.

In another aspect, an embodiment of the present invention provides a signal conversion method, where the method includes: carrying out protocol analysis on a signal from an LPC bus, and outputting a local signal through a local bus, wherein the local signal comprises an address signal, a data signal and a control signal; configuring a register of the UART unit according to the local signal; the register of the UART unit is distributed in an internal memory address space and an I/O address space; and converting the data from the LPC bus into serial data according to the local signal and the value of a register of the UART unit after configuration, and then outputting the serial data through a UART interface, or outputting the serial data received from the UART interface to the LPC bus according to the local signal.

In a further aspect, an embodiment of the present invention provides a communication device, where the communication device includes: CPU, south bridge, signal conversion device and peripheral equipment of the embodiment of the invention; the CPU is used for sending signals to the signal conversion device and/or the peripheral equipment through an LPC interface of the south bridge; the signal conversion device is used for converting data of an LPC interface and UART data, and sending signals sent by the CPU to the peripheral equipment or receiving signals from the peripheral equipment so as to feed back the signals to the CPU.

The device and the method of the embodiment of the invention realize the signal conversion function from LPC bus protocol to UART serial port communication by utilizing the internal logic circuit of the programmable logic device, avoid using a super I/O chip in the prior art, and achieve the beneficial technical effects of simplifying configuration, saving cost, saving circuit board space and reducing circuit complexity.

The communication equipment of the embodiment of the invention can send the data analyzed by the LPC bus interface unit with low pin number out through the UART unit and read and write the peripheral equipment connected with the communication equipment.

Drawings

FIG. 1 is a diagram illustrating a hardware connection for UART communication using a super I/O chip according to the prior art;

fig. 2 is a schematic structural diagram of a signal conversion apparatus according to embodiment 1 of the present invention;

FIG. 3 is a state transition diagram of an LPC bus interface unit according to embodiment 1 of the present invention;

FIG. 4 is a functional block diagram of a UART unit according to embodiment 1 of the present invention;

FIG. 5 is an interface diagram of the FIFO memory according to embodiment 1 of the present invention;

fig. 6 is a schematic diagram of a transmission operation principle of the transmission subunit according to embodiment 1 of the present invention;

fig. 7 is a schematic diagram of an operating principle of a receiving subunit according to embodiment 1 of the present invention;

fig. 8 is a schematic flowchart of a signal conversion method according to embodiment 2 of the present invention;

fig. 9 is a schematic structural diagram of a communication system according to embodiment 3 of the present invention.

Detailed Description

The following exemplary description, which is set forth in the following detailed description of the embodiments of the present invention with reference to the accompanying drawings, is intended to be illustrative of the claims of the present invention and not limiting thereof.

Example 1:

embodiment 1 of the present invention provides a signal conversion apparatus. In the embodiment 1 of the present invention, the signal conversion apparatus is implemented by using a programmable logic device such as a CPLD or an FPGA as a carrier and using internal logic resources of the logic device, thereby simplifying a configuration process of a corresponding register of a UART unit included in the signal conversion apparatus.

Fig. 2 is a schematic structural diagram of a signal conversion apparatus according to embodiment 1 of the present invention. As shown in fig. 2, the device 20 according to embodiment 1 of the present invention is connected to the south bridge 40 via an LPC (Low Pin Count) bus. Referring to fig. 2, the apparatus according to embodiment 1 of the present invention includes:

LPC bus interface unit 201, register configuration unit 202, UART unit 203;

the LPC bus interface unit 201 is configured to perform protocol analysis on a signal from an LPC bus, and output a local signal through a local bus, where the local signal includes a control signal, an address signal, and a data signal;

the register configuration unit 202 is configured to configure a register of the UART unit 203 according to the local signal; registers of the UART unit 203 are allocated in a memory address space and an I/O address space;

the UART unit 203 is configured to convert data from the LPC bus into serial data according to the local signal and a value of a register of the UART unit after configuration, and output the serial data through a UART interface or output the serial data received from the UART interface to the LPC bus according to the local signal.

Further, the register configuration unit 202 may be further configured to obtain information of a register read-write mode through the local signal, and when the register read-write mode is memory read-write, operate a register of the UART unit 203 allocated in a memory address space; when the read-write mode of the register is I/O read-write, operating the register of the UART unit 203 distributed in the I/O address space;

the register read-write mode information is obtained by the LPC bus interface unit 201 according to the register read-write instruction: when the register read-write instruction is an I/O read-write instruction, the LPC bus interface unit outputs a register read-write mode of I/O read-write; when the register read-write instruction is a memory read-write instruction, the LPC bus interface unit outputs the register read-write mode as memory read-write.

Further, the signal conversion apparatus 20 may further include: a system storage unit 204 for storing a system operating system OS and/or a basic input output system BIOS; the system memory unit 204 is connected to the LPC bus interface unit 201, and performs read/write operation on data stored therein by receiving the local signal from the LPC bus interface unit 201 according to the local signal.

Further, the LPC bus interface unit 201 may be further configured to connect to at least one peripheral device 30 and communicate with the peripheral device 30 through the local signal. The peripheral devices include one or more of the following: the system comprises a main/standby switching device, a power-on reset device, a clock detection device, a version inquiry device and an interrupt processing device.

Optionally, the Local Bus is a Local Bus, and the system memory unit is a NOR flash with a Local Bus interface.

Preferably, the UART unit 203 includes: the register array is used for storing the received data signals or configuring at least one register in the register array according to the data signals; the first FIFO memory is used for storing data to be transmitted; the second FIFO memory is used for storing data to be read; the transmitting unit is used for monitoring the state of the first FIFO memory, reading the data to be transmitted in the first FIFO memory when the state is effective, converting the data to be transmitted into a serial format, and transmitting the data based on a universal asynchronous serial communication protocol; and the receiving unit is used for receiving the serial data, converting the serial data into parallel data, writing the parallel data into the second FIFO memory, and triggering the state of at least one register in the register array to change.

Further, the function of the LPC bus interface unit included in the signal conversion apparatus according to embodiment 1 of the present invention will be described in detail with reference to the drawings.

LPC bus, which is used to connect South Bridge (South Bridge) and peripheral slow devices, table 1 provides definitions of the pins of the LPC bus.

TABLE 1 LPC bus signal definition table

In embodiment 1 of the present invention, the signals required for the LPC bus are LAD [3:0],/LFRAME,/LRESET, LCLK; among the optional signals, serial interrupt signal/SER _ IRQ, needs to be used.

Figure 3 is a state transition diagram of the state machine within the LPC bus interface unit. As shown in fig. 3, the state transition diagram of the internal state machine of the LPC bus interface unit describes the working principle of the LPC bus interface unit, which is not repeated herein, please refer to the document number of the LPC protocol document "Intel Low Pin Count (LPC) interface specification": 251289-001.

Table 2 is a second clock Cycle definition table of LPC "Cycle type & Dir", and as shown in table 2, in the LPC protocol, after a frame starts, in the second clock Cycle (Cycle type & Dir), the read/write mode of the frame data is given: memory read and write, or I/O read and write. From this information, it is determined whether the frame data accesses a memory address space or an I/O address space.

Bits[3:2]	Bit[1]	Definition (Definition)
			00	0	I/O Read (I/O Read)
00	1	I/O Write (I/O Write)
			01	0	Memory Read (Memory Read)

01	1	Memory Write (Memory Write)
			10	0	DMA Read (direct memory access Read)
10	1	DMA Write (direct memory access Write)
			11	x	Reserved

TABLE 2 second clock Cycle definition Table for LPC "Cycle type & Dir

Further, the function, structure and operation principle of the UART unit according to embodiment 1 of the present invention will be explained in detail below, and the same reference numerals are used for the same elements for simplifying the description.

Referring to fig. 4, fig. 4 is a functional block diagram of a UART unit according to embodiment 1 of the present invention. As shown in fig. 4, the UART unit 203 according to embodiment 1 of the present invention includes:

a register array 2031, which may include a receive buffer register, a transmit hold register, an interrupt enable register, an interrupt flag register, a FIFO control register, a line control register, a Modem control register, a line status register, a Modem status register, a cache register, a divisor-latch-low bit register (LSB), and a divisor-latch-high bit register (MSB);

a first FIFO memory 2032 and a second FIFO memory 2035 for buffering data to be sent or read; since the LPC bus rate is much higher than the UART rate, and in order to be compatible with other subsequent designs, in the embodiment of the present invention, a group of 64 × 8(FIFO depth × FIFO width) FIFO (First Input First Output) memories dedicated to transmitting data is embedded in the UART unit 203, another group of 16 × 8(FIFO depth × FIFO width) FIFO memories dedicated to receiving data is embedded in the register array 2031, and the two groups of FIFO memories are respectively connected to the register array 2031 and read data from the register array 2031 or write data into the register array 2031 according to the read/write control command of the register array 2031.

FIG. 5 is a diagram of an interface of the FIFO memory according to embodiment 1 of the present invention. As shown in fig. 5, the CLK pin is a system clock, the RST pin is a system reset signal, when the write enable wr _ en is active, a set of data is written into the FIFO memory every clock cycle, and when the read enable rd _ en is active, a set of data is read out from the FIFO memory every clock cycle, so that when the FIFO memory is read and written, the operation can be performed only in one clock cycle. When the FIFO memory has no data, the empty pin outputs high level; when the FIFO memory is FULL of data, the FULL pin outputs high level; din is a data input pin, and dout is a data output pin.

A transmitting subunit 2033, configured to monitor a state of the first FIFO memory 2032, and when the state is valid, that is, when the FULL pin outputs a high level to indicate that the first FIFO memory 2032 is FULL, read out data in the first FIFO memory, convert the data into a serial format, and transmit the data based on a universal asynchronous serial communication protocol.

Fig. 6 is a schematic diagram of a transmission operation principle of the transmission subunit according to embodiment 1 of the present invention. As shown in fig. 6, after the FIFO memory reads data, the empty pin signal is at low level, the transmitting subunit is triggered to read the FIFO memory, and the read data content is converted into UART communication format for serial transmission, and after the transmission is completed, the state of the transmitting FIFO memory is continuously monitored.

The above-mentioned sending process is further refined as:

step S601, the address analyzed and output by the LPC bus interface unit is the address of the Transmit Hold Register (THR) of the UART communication unit (for example, the address may be 0X03F 8);

step S602, the logic monitoring LPC bus interface unit outputs a write enable (wr _ en) signal;

step S603, when the LPC write enable signal is detected to be effective;

step S604, transmitting (writing) data information on the Local Bus to the above-mentioned transmission holding register of the UART communication unit;

step S605, the logic automatically triggers the sending and holding register to write the first FIFO memory so as to write the data content of the sending and holding register into the first FIFO memory;

step S606, monitoring whether the first FIFO storage is empty, if yes, performing step S607, and if no, performing step S614;

step S607, detecting that the state of the Empty pin of the first FIFO memory is invalid;

after the data is written into the first FIFO memory, its empty pin is set to low (inactive state).

Step S608, when the sending subunit is idle, triggering the sending subunit to perform a read operation on the first FIFO memory, that is, to read data in the first FIFO memory;

step S609, the sending subunit saves the data to be sent and enters a UART conversion mode;

step S610, the sending subunit sends the start bit of the data to be sent;

step S611, setting a frame format by the UART wire control register so that the sending subunit converts the read data into a serial port data format and then sends the serial port data format based on a universal asynchronous serial communication protocol;

the serial data format in the embodiment of the invention may include a 1-bit start bit, 5-8-bit data bits, 0-1-bit parity bits, and 1 or 1.5 or 2-bit stop bits.

Step S612, the sending subunit performs parallel-serial format conversion on the data to be sent and sends the data;

step S613, the sending subunit performs parity check calculation and sends corresponding parity check bits;

and step S614, the sending subunit sends the stop bit.

The receiving subunit 2034 in this embodiment of the present invention is configured to receive serial data according to the configuration parameters of the corresponding register, convert the serial data into parallel data, write the parallel data into the second FIFO memory 2035, and trigger a state change of at least one of the plurality of registers. For example, the state setting of the trigger interrupt flag register or the line state register changes.

Fig. 7 is a schematic diagram of an operating principle of a receiving subunit according to embodiment 1 of the present invention. As shown in fig. 7, the logic monitors the input data of the receiving end Rx of the receiving subunit 2033 of the UART unit 203 by using a clock with a 16-fold serial baud rate, when Rx has a low-level input, it indicates that the start bit of the data frame is monitored, so as to enter the analysis state of the UART data frame, and stores the received data in the second FIFO storage after performing serial-parallel conversion, when the stop bit is detected, it detects and stores the data of the data bit, parity bit, stop bit, and the like of the frame data according to the configuration item of the configuration register 4037 of the UART communication unit, and determines whether parity error, overflow error flag, or frame error exists, so as to change the state setting of the line state register according to the above determination result.

In a specific application, the UART unit 203 according to embodiment 1 of the present invention may further include: the interrupt subunit 2036 is configured to monitor a state change of at least one register of the plurality of registers, for example, monitor a state change of a line state register, to generate an interrupt signal, and upload the interrupt signal to a host connected to the apparatus, to trigger the host to read the data to be read, for example, an interrupt may be reported to the host through a SERIRQ.

Further, the function and the operation principle of the register configuration unit 202 according to embodiment 1 of the present invention will be described in detail as follows:

the embodiment of the invention allocates each register of the UART unit in both I/O address space and Memory address space. The register configuration unit in embodiment 1 of the present invention allocates the local signal to the UART communication unit according to an I/O address or a memory address of a register included in the UART communication unit, and configures a corresponding register included in the UART unit according to the local signal.

Optionally, the address range of each register of the UART unit may be allocated in advance in the I/O address space to be 0X03F 8-0X 03 FF. Optionally, the address range of each register of the UART unit may be allocated in the Memory address space in advance to be 0X F00003F 8-0X F00003 FF.

In the I/O address space, an I/O address 0X03F8 is commonly assigned to the receive buffer register and the transmit hold register, and is accessible when the divisor latch access bit DLAB is 0. Bits 0-7 of the receiving buffer register and the sending holding register are data bits for storing data.

In the IO address space, an I/O address 0X03F8 is commonly allocated to a divisor latch low-order register and a divisor latch high-order register, and when a divisor latch access Bit DLAB is 1, the registers can be accessed, and low 8-Bit data stored in bits 0 to 7 of the divisor latch low-order register and high 8-Bit data stored in bits 0 to 7 of the divisor high-order register are used to configure the baud rate of serial communication.

In an I/O address space, an I/O address 0X03FB is allocated to a line control register, a Bit 0-Bit 1 of the line control register is used for configuring the word length of serial communication, a Bit2 is used for configuring the number of stop bits of the serial communication, a Bit3 is used for configuring whether the serial communication is enabled for parity check, and a Bit4 is used for configuring whether a check mode is odd check or even check.

In the I/O address space, I/O addresses 0X03FC to 0X03FE are allocated to the Modem control register, the line status register, and the Modem status register, respectively.

In the Memory address space, the difference is that a Memory address 0XF00003F8 is commonly allocated to the receive buffer register and the transmit hold register, and when DLAB is 0, the above registers can be accessed. The Memory address 0XF00003F8 is commonly assigned to the divisor-latching low-order register and the divisor-latching high-order register, and when DLAB is 1, the above registers can be accessed. A Memory address of 0XF00003FB is assigned to the line control register. Memory addresses 0XF00003FC to 0X F00003FE are allocated to the Modem control register, line status register, and Modem status register, respectively.

The register configuration unit in embodiment 1 of the present invention may configure each register of the UART communication subunit by receiving the related signal sent by the LPC bus interface unit, so as to provide a UART with a complete function: the Baud rate can be set to be 50-450 k; 1bit start bit; the stop bit 1bit, 1.5bit and 2bit can be set; odd check, even check and no check are optional. And these set functions are assigned to respective addresses in the form of registers. When the Host needs to perform UART communication or setting with the signal conversion device, only the corresponding address of the corresponding register of the UART unit needs to be read and written. For example, the address may be addressed IN the I/O address space and operated on using "OUT" and "IN" instructions, which may be, for example:

MOV DX，03F8H；UART THR register

MOV AL，08H；data

OUT DX，AL

the memory address space can also be addressed, and the MOV instruction is directly used for reading and writing, and the operation instruction can be, for example:

MOV AL，byte ptr DS：[UART_THR_ADD]。

further, the signal conversion apparatus of the embodiment of the present invention further includes a system storage unit, configured to store a system operating system OS and/or a basic input output system BIOS; and the system storage unit is connected with the LPC bus interface unit, receives the local signal from the LPC bus interface unit and carries out read-write operation on the data stored in the system storage unit according to the local signal. Optionally, the Local Bus is a Local Bus, and the system memory unit is a NOR flash with a Local Bus interface.

The BIOS is allocated in the memory address space of FF00_0000 FFFF _ FFFF. When CPU accesses NOR flash stored with BIOS through LPC bus of south bridge, the highest 8bit address line is used to generate flash chip selection signal to access the flash. When the LPC Bus accesses the slave Device in a memory mode, a read/write frame comprises 8 address cycles, each address cycle transmits 4-bit data, and transmits 32-bit address data in total, wherein the 23 bits, the 22 bits, the 21 bits and the 19 bits respectively correspond to 3-0 bits of a Device ID (Device identification), and the 0-18 bits of the address data correspond to 0-18 bits of a Local Bus address. The frame information from the LPC Bus is converted into the read-write time sequence of Local Bus required by flash through the analysis of the LPC Bus interface unit, so that the data stored in the BIOS can be read and written.

The embodiment of the invention also manages the peripheral equipment by using a local bus, such as a LocalBus bus. When all the peripherals and the flash memories are managed by using the same local bus, the system can be effectively integrated, the simplicity and the cleanliness of the system are improved, and the software codes are conveniently written.

In summary, the embodiment 1 of the present invention has the following beneficial technical effects:

in the embodiment 1 of the invention, the programmable logic device such as a CPLD or an FPGA is used as a carrier, and the communication from an LPC bus protocol to a UART serial port is realized by utilizing the internal logic circuit of the logic device, so that the serial port function is realized by using an additional hardware chip in the prior art, the cost is reduced, the space of a circuit board is saved, the complexity and the redundancy of the circuit are reduced, and the configuration process of the UART serial port is simplified.

Before serial port communication is performed, the signal conversion device in embodiment 1 of the present invention can very conveniently configure each register of the UART unit according to the local signal analyzed by the LPC bus interface unit, so as to perform serial port communication through the configured UART unit. In the signal conversion apparatus according to embodiment 1 of the present invention, since the register of the UART unit is allocated in both the I/O address space and the Memory (Memory) address space, the register of the UART unit can be accessed regardless of the I/O access or the Memory access. Therefore, IN the configuration process, the corresponding registers of the UART units addressed to the I/O address space can be configured by using the instructions such as "OUT", "IN", etc., or the corresponding registers of the UART units addressed to the Memory address space can be configured by using the MOV instruction, thereby greatly simplifying the configuration process of the registers of the UART units. The embodiment 1 of the invention can be applied to an I/O read-write mode and a memory read-write mode of a CPU of a CISC system, so that the CPU of an X86 architecture can access a serial port or other external interfaces and memory space without difference like the read-write of the CPU of the RISC system.

Embodiments of the present invention use a common NOR flash instead of the flash of the LPC interface to store BIOS code. The flash of the LPC interface is 4 bits or 8 bits wide, and the data bit width can be set to 16 bits and 32 bits using the ordinary NOR flash. The common NOR flash has independent data bus and address bus, which can read the code directly from flash. And using NOR flash, it can upgrade flash on line at high speed using JTAG. Meanwhile, the OS flash (operating system flash) and the BIOS flash are combined into one flash, so that hardware resources are saved. In the prior art, a flash with an LPC interface can only be loaded through an LPC simulator, JTAG (Joint Test Actions Group) loading is inconvenient to realize if the flash is directly hung on a south bridge, and even if the JTAG loading is reluctantly realized, the loading time is very long, for example, the loading of a 4Mbit flash reaches hours, which is not practical. If the pins of the JTAG control CPLD of the embodiment of the invention are used for loading NOR flash, the online rapid upgrade of the system can be realized, for example, in the embodiment of the invention, the time for loading 4Mbit flash is about several minutes.

Example 2:

embodiment 2 of the present invention provides a signal conversion method.

Fig. 8 is a flowchart of a signal conversion method according to embodiment 2 of the present invention. As shown in fig. 8, the method includes:

step S801, carrying out protocol analysis on a signal from an LPC bus, and outputting a local signal through a local bus, wherein the local signal comprises an address signal, a data signal and a control signal;

the local signals comprise address signals, data signals and control signals; the control signals include a chip select signal, a read enable signal, and a write enable signal.

The specific process of performing protocol resolution on the signal from the LPC bus may include:

receiving frame data from the LPC bus; judging whether the register read-write mode of the register of the UART unit is memory read-write or I/O read-write according to the register read-write identification in the frame data; when the register read-write mode is memory read-write, accessing the register of the UART unit distributed in the memory address space; and when the read-write mode of the register is I/O read-write, accessing the register of the UART unit distributed in the I/O address space.

Step S802, configuring a register of the UART unit according to the local signal; the register of the UART unit is distributed in an internal memory address space and an I/O address space;

the register of the UART unit at least comprises one of the following registers: the device comprises a receiving cache register, a sending holding register, an interrupt enabling register, an interrupt identification register, an FIFO control register, a line control register, a Modem control register, a line state register, a Modem state register, a divisor latching low-order register and a divisor latching high-order register.

It is emphasized that registers of the UART unit, both in the Memory address space and in the I/O address space, can be accessed to registers of the UART communication unit, both for I/O accesses and Memory accesses. The logic can be applied to an I/O read-write mode and a memory read-write mode of a CPU of a CISC (Complex instruction Set Computer) system, so that the CPU of an X86 system can access a serial port or other external interfaces and memory space without difference as the read-write mode of the CPU of a RISC (Reduced instruction Set Computer) system.

The process of configuring the register of the UART unit according to the local signal may specifically include:

configuring bits 0-1 of a line control register to configure the length of an effective sub symbol of serial communication to be 5-8 bits; configuring bit2 of the line control register to configure the number of stop bits of serial communication to be 1bit, 1.5bit or 2 bit; configuring bit3 of the line control register to configure whether serial communication is verified; and configuring a bit4 of the line control register, wherein the configuration adopted verification mode is odd verification or even verification. Configuring bits 0-7 of a divisor latching low-order register and bits 8-15 of a divisor latching high-order register so as to configure baud rate of serial communication; the foregoing is illustrative only and is not to be construed as limiting the invention.

Step S803, converting the data from the LPC bus into serial data according to the local signal and the value of the register of the configured UART unit, and then outputting the serial data through the UART interface, or outputting the serial data received from the UART interface to the LPC bus according to the local signal.

The above process can be further refined as: monitoring the state of an FIFO memory for storing transmission data, reading the data to be transmitted in the FIFO memory for storing the transmission data when the state is effective, converting the data to be transmitted into a serial format, and transmitting the data based on a universal asynchronous serial communication protocol; or receiving serial data, converting the serial data into parallel data, writing the parallel data into an FIFO memory for storing data to be read, and triggering the state of a relevant register to change so as to enable the parallel data to be output to the LPC bus.

Further, the signal conversion method further includes: communicating with at least one peripheral device via the local signal.

Further, the signal conversion method further includes: and receiving the local signal from the interface of the LPC bus, and performing read-write operation on the storage unit through the local signal. The Local Bus may be a Local Bus or other Bus; the storage unit is a NOR flash with a Local Bus interface or a flash with an interface corresponding to other buses; when the interfaces of the local bus and the flash bus are not consistent, the flash can be managed after the two buses are converted.

Compared with the scheme of the prior art that the LPC conversion UART interface is realized by utilizing the super I/O device, the method of the embodiment 2 simplifies the configuration process of the corresponding register of the UART unit, and reduces the hardware cost and the circuit redundancy; because each register of the UART unit is addressed in the internal Memory address space and also addressed in the I/O address space, and each register of the UART communication unit can be accessed no matter the I/O access or the Memory access, the method of the embodiment 2 of the invention can be applied to the I/O read-write mode and the Memory read-write mode of the CPU of the CISC system, so that the CPU of the X86 architecture can access the UART serial port or other external interfaces and the Memory space without difference like the read-write of the CPU of the RISC system.

The signal conversion method in embodiment 2 of the present invention may be implemented by using a CPLD or an FPGA as a carrier, and logically implements protocol interpretation on a signal from an LPC bus, and the LPC protocol may be cut down or increased, and the LPC bus protocol may support read-write modes such as DMA (Direct Memory Access), Memory, and firmware HUB, and may be cut down according to a use requirement.

Example 3:

referring to fig. 9, embodiment 3 of the present invention provides a communication apparatus 90 including: a CPU901, a south bridge 902, a signal conversion device 903 of embodiment 1 of the present invention, and a peripheral device 904; the CPU901 is configured to send a signal 904 to the signal conversion apparatus 903 and/or a peripheral device through an LPC interface of the south bridge 902; the signal conversion device 903 is configured to convert data of an LPC interface and UART data, and send a signal sent by the CPU901 to the peripheral device 904, or receive a signal from the peripheral device 904 to feed back the signal to the CPU 901.

In embodiment 3 of the present invention, both the super I/O function and the system management monitoring function are completed by using a CPLD, and functions such as a signal conversion device, a NOR flash interface, detection monitoring, and the like are integrated or fused. On the premise of not adding devices, the serial port function is completed by only using about 280 logic unit resources and at most 10 pins, so that the space and the cost of a PCB are greatly saved, and the configuration flow of software to the UART serial port is simplified. After the functions of the serial port and the system management function are fused, the simplicity of the single board is greatly improved, and the software compiling is more convenient.

The communication device of embodiment 3 of the present invention can recognize the read-write mode of the LPC bus to configure the UART communication unit implemented logically. In order to facilitate the writing of embedded software, embodiment 3 of the present invention provides a fully functional UART serial port with a CPLD as a carrier: the baud rate can be set to 50-450 k; 1bit start bit; the stop bit can be selected to be 1bit, 1.5bit or 2 bit; odd check, even check or no check are optional. The mode of serial interruption can be adopted, and the interruption module can be cut according to the system requirement. All UART serial registers can be accessed in both memory address space and I/O address space.

The communication device of the embodiment of the invention sends the signal sent by the CPU to the peripheral device, or receives the signal from the peripheral device to feed back to the CPU. The peripheral device includes: the system comprises a main/standby switching device, a power-on reset device, a clock detection device, a version inquiry device and an interrupt processing device. The following describes an operation process in which the communication device receives a signal from the power-on reset device to feed back the signal to the CPU, by taking the above power-on reset device as an example. It should be understood by those skilled in the art that the following exemplary descriptions are only for purposes of illustrating embodiments of the present invention and are not to be construed as limiting the invention.

For example: the reset register address of the reset module may be preset as follows:

when the CPU controls LPC bus through south bridge, it reads and writes 0xF000, 001C address of the memory space. The local bus output address corresponds to 0xF000, 001C and the LPC bus interface unit in the signal conversion means connects the data bus to the input of the reset register of the power-on reset means. When the write enable is active, the register latches the data bus. When the power-on reset device works, the power-on reset device controls the reset of peripheral equipment of the system according to the content of the reset register; when the address output by the local bus is within the range of 0xF000, 03F 8-0 xF000, 03FF, the LPC bus interface unit in the signal conversion device connects the data bus to the input of the corresponding register of the UART unit, and then operates the UART unit according to the content of the control signal, so that the UART communication unit realizes the serial communication of data according to the local signal and the configuration parameters of the corresponding register.

The communication device of embodiment 3 of the present invention has the following beneficial technical effects:

1. the communication equipment of the embodiment of the invention can send the data analyzed by the LPC bus interface unit with low pin number out through the UART unit and read and write the peripheral equipment connected with the communication equipment.

2. The programmable logic device is used as a carrier, and a communication function from an LPC bus protocol to a UART serial port is realized by utilizing a CPLD or FPGA internal logic circuit;

3. the register of the UART unit can be allocated in the Memory address space and the I/O address space, and the register of the UART module can be accessed no matter the I/O access or the Memory access. The logic can be applied to an I/O read-write mode and a memory read-write mode of a CPU of a CISC system, so that the CPU of an X86 architecture can access serial ports or other external interfaces and memory space without difference like the read-write of the CPU of a RISC system.

4. The protocol interpretation of the LPC signal is realized by using logic, and the LPC protocol can be cut down and increased and is changed according to the requirements of a user. The logic implementation is utilized, a CPLD or an FPGA is used as a carrier, the implementation function can be flexible, the LPC protocol can support DMA, Memory, firmware HUB and other reading and writing modes, and the reduction can be carried out according to the use requirement.

The above-disclosed embodiments are merely exemplary embodiments of the present invention, which should not be construed as limiting the scope of the invention, and therefore all equivalent variations that can be made in the scope of the present invention are also included in the claims.

Claims

1. A signal conversion apparatus, characterized in that the signal conversion apparatus comprises: LPC bus interface unit, register configuration unit, UART unit;

the LPC bus interface unit is used for carrying out protocol analysis on signals from an LPC bus and outputting local signals through a local bus, and the local signals comprise control signals, address signals and data signals;

the register configuration unit is used for configuring a register of the UART unit according to the local signal; the register of the UART unit is distributed in an internal memory address space and an I/O address space;

and the UART unit is used for converting the data from the LPC bus into serial data according to the local signal and the value of a register of the UART unit after configuration and then outputting the serial data through a UART interface or outputting the serial data received from the UART interface to the LPC bus according to the local signal.

2. The signal conversion apparatus according to claim 1, wherein the register configuration unit is further configured to obtain information about a register read/write mode through the local signal, and when the register read/write mode is memory read/write, operate a register of the UART unit allocated in a memory address space; when the read-write mode of the register is I/O read-write, operating the register of the UART unit distributed in the I/O address space;

the read-write mode information of the register is obtained by judging by the LPC bus interface unit according to a read-write instruction of the register:

when the register read-write instruction is an I/O read-write instruction, the LPC bus interface unit outputs a register read-write mode of I/O read-write;

when the register read-write instruction is a memory read-write instruction, the LPC bus interface unit outputs the register read-write mode as memory read-write.

3. The signal conversion apparatus of claim 1, wherein the signal conversion apparatus further comprises:

a system storage unit for storing a system Operating System (OS) and/or a Basic Input Output System (BIOS); and the system storage unit is connected with the LPC bus interface unit, receives the local signal from the LPC bus interface unit and carries out read-write operation on the data stored in the system storage unit according to the local signal.

4. The signal conversion apparatus of claim 1, wherein:

the LPC bus interface unit is further configured to connect to at least one peripheral device, and communicate with the peripheral device through the local signal.

5. The signal conversion apparatus of claim 4, wherein:

the Local Bus is a Local Bus, and the system storage unit is a NOR flash with a Local Bus interface.

6. The signal conversion apparatus of claim 1, wherein the UART unit includes:

the register array is used for storing the received data signals or configuring at least one register in the register array according to the data signals;

the first FIFO memory is used for storing data to be transmitted;

the second FIFO memory is used for storing data to be read;

the transmitting unit is used for monitoring the state of the first FIFO memory, reading the data to be transmitted in the first FIFO memory when the state is effective, converting the data to be transmitted into a serial format, and transmitting the data based on a universal asynchronous serial communication protocol;

and the receiving unit is used for receiving the serial data, converting the serial data into parallel data, writing the parallel data into the second FIFO memory, and triggering the state of at least one register in the register array to change.

7. A signal conversion method, characterized in that the signal conversion method comprises:

carrying out protocol analysis on a signal from an LPC bus, and outputting a local signal through a local bus, wherein the local signal comprises an address signal, a data signal and a control signal;

configuring a register of the UART unit according to the local signal; the register of the UART unit is distributed in an internal memory address space and an I/O address space;

and converting the data from the LPC bus into serial data according to the local signal and the value of a register of the UART unit after configuration, and then outputting the serial data through a UART interface, or outputting the serial data received from the UART interface to the LPC bus according to the local signal.

8. The signal conversion method of claim 7, wherein said step of protocol resolving the signal from the LPC bus comprises:

receiving frame data from the LPC bus;

judging whether the register read-write mode of the register of the UART unit is memory read-write or I/O read-write according to the register read-write identification in the frame data;

when the register read-write mode is memory read-write, accessing the register of the UART unit distributed in the memory address space;

and when the read-write mode of the register is I/O read-write, accessing the register of the UART unit distributed in the I/O address space.

9. The signal conversion method of claim 7, further comprising:

communicating with at least one peripheral device via the local signal.

10. The signal conversion method of claim 7, further comprising:

and receiving the local signal from the interface of the LPC bus, and performing read-write operation on the storage unit through the local signal.

11. The signal conversion method of claim 10, wherein:

the Local Bus is a Local Bus; the storage unit is a NOR flash with a Local Bus interface.

12. The signal conversion method according to claim 7, wherein the step of converting the data from the LPC bus into serial data according to the local signal and the value of the register of the UART unit configured to output the serial data through the UART interface, or outputting the serial data received from the UART interface to the LPC bus according to the local signal comprises:

monitoring the state of an FIFO memory for storing transmission data, reading the data to be transmitted in the FIFO memory for storing the transmission data when the state is effective, converting the data to be transmitted into a serial format, and transmitting the data based on a universal asynchronous serial communication protocol; or,

receiving serial data, converting the serial data into parallel data, writing the parallel data into an FIFO memory for storing data to be read, and triggering the state of a relevant register to change so as to enable the parallel data to be output to the LPC bus.

13. A communication device, characterized in that the communication device comprises: CPU, south bridge, signal conversion device and peripheral equipment;

the CPU is used for sending signals to the signal conversion device and/or the peripheral equipment through an LPC interface of the south bridge;

the signal conversion device is as claimed in any one of claims 1 to 6, and is configured to convert data of an LPC interface and UART data, and send or receive a signal sent by the CPU to or from the peripheral device to feed back the signal to the CPU.