CN101861056B - Method for processing high-density integrated circuit - Google Patents
Method for processing high-density integrated circuit Download PDFInfo
- Publication number
- CN101861056B CN101861056B CN 201010193150 CN201010193150A CN101861056B CN 101861056 B CN101861056 B CN 101861056B CN 201010193150 CN201010193150 CN 201010193150 CN 201010193150 A CN201010193150 A CN 201010193150A CN 101861056 B CN101861056 B CN 101861056B
- Authority
- CN
- China
- Prior art keywords
- processing
- compensation
- integrated circuit
- cutting
- actual graphical
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Manufacturing Of Printed Circuit Boards (AREA)
Abstract
The embodiment of the invention discloses a method for processing a high-density integrated circuit, comprising the following steps of: 1, measuring a space a between adjacent actual graphs and the minimum space b between compensated graphs, wherein b is less than a; and 2, cutting a metal layer at the minimum space of the compensated graphs when the minimum space b is less than the processing size c, wherein the cutting sizes are delta b' and delta b, and b+delta b'+delta b is more than or equal to c and less than a. Through adopting the processing method, the graphs subjected to the compensation process are locally cut off to meet the space requirement in the processing process, so as to process the surplus part in the better cut graphs of a cutter and improve the processing precision.
Description
Technical field
The present invention relates to the manufacturing field of wiring board, more particularly, relate to the processing method of high-density integrated circuit.
Background technology
Modern electronic product is integrated towards function, and the volume miniaturization is carried the portability direction and developed.This just requires, PCB (Printed Circuit Board, printed circuit board), and also towards integrated, fine and closely wovenization direction develops as the critical component in the electronic product.Along with the integrated development of PCB wiring board, this has proposed increasingly high requirement to the processing as the figure of signal transmission in the PCB wiring board.
At present, in the processing technology of PCB, the copper method that subtracts is adopted in the processing of figure mostly.Subtract the copper method in employing and add man-hour, adopt etch process usually, so-called etch process is meant: with unwanted metal level on the substrate (normally copper layer), remove with the mode of chemistry with etching solution, form the circuitry needed figure.And as the circuit metal level in the line pattern, the method that adopts sensitization figure transfer or silk screen printing usually prevents that at organic resist of its surface coverage last layer or metal resist layer it is etched.Lateral erosion is unavoidable problem in etch process; Lateral erosion is when carrying out the etching of depth direction owing to etching liquid medicine; Inevitably will react with the metal level of horizontal direction, therefore, the lead sidewall below the resist layer side is etched; Make the shape of circuit change, influence the precision of circuit.In existing technology, adopt compensate for process design live width and spacing usually, more unnecessary layer is machined away behind the etch process.
But adopt this compensate for process; Because the certain size of the whole increasing of figure; Cause the spacing of figure to reduce; And in the actual course of processing, can receive the restriction (spacing has certain working ability, and spacing is crossed the young pathbreaker and caused figure can't process coming) of spacing, need bigger spacing could satisfy processing request; And this and wiring board be towards the fine rule road, and little spacing direction Development Trend is a contradiction.
Summary of the invention
In view of this, the present invention provides the processing method of high-density integrated circuit, and the printed circuit board that processes through this method can satisfy processing dimension.
For realizing above-mentioned purpose, the present invention provides following technical scheme:
A kind of processing method of high-density integrated circuit comprises:
Step 1: measure the minimum spacing a between the adjacent actual graphical, and the minimum spacing b between the compensation figure, wherein, b＜a;
Step 2: as said minimum spacing b during less than processing dimension c, using width is the metal level at the Tool in Cutting compensation figure minimum spacing place of said processing dimension c, and its cutting size is respectively Δ b ' and Δ b, makes c≤b+ Δ b '+Δ b＜a;
Adopt etch process, remove the outer metal of said actual graphical.
Preferably, in the processing method of above-mentioned high-density integrated circuit, taking a step forward in step 1 comprises:
Overall dimensions to the figure on the substrate compensates, and its free size is (a-b)/2, and b＜a.
Preferably, in the processing method of above-mentioned high-density integrated circuit, saidly be compensated for as even compensation.
Preferably, in the processing method of above-mentioned high-density integrated circuit, comprise after the said steps etching technology: the compensated part of cutting compensation figure obtains actual graphical.
Preferably, in the processing method of above-mentioned high-density integrated circuit, said Δ b '=Δ b.
Preferably, in the processing method of above-mentioned high-density integrated circuit, said c＜b+ Δ b '+Δ b＜a.
Through adopting above-mentioned processing method, the graphics sub behind the compensate for process is machined away, be met the spacing requirement in the course of processing, make and unnecessary part in the better cutting image of process tool improved machining accuracy.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art; To do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art below; Obviously, the accompanying drawing in describing below only is some embodiments of the present invention, for those of ordinary skills; Under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
Graphic structure sketch map on the high-density integrated circuit that Fig. 1 provides for the embodiment of the invention;
The processing method flow chart of the high-density integrated circuit that Fig. 2 provides for the embodiment of the invention one;
The processing method flow chart of the high-density integrated circuit that Fig. 3 provides for the embodiment of the invention two;
The processing method flow chart of the high-density integrated circuit that Fig. 4 provides for the embodiment of the invention three.
Embodiment
To combine the accompanying drawing in the embodiment of the invention below, the technical scheme in the embodiment of the invention is carried out clear, intactly description, obviously, described embodiment only is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills are not making the every other embodiment that is obtained under the creative work prerequisite, all belong to the scope of the present invention's protection.
The present invention provides the processing method of high-density integrated circuit, and the printed circuit board that processes through this method can satisfy processing dimension.
As shown in Figure 1, comprise among the figure actual graphical 1 and 1 ' with compensation figure 2 and 2 '.So-called actual graphical is exactly the figure that actual needs is processed into; According to actual Butut actual graphical is engraved on the printing board PCB; But because the existence of lateral erosion in the etch process need compensate actual graphical according to the compensating parameter of etching liquid medicine and the anti-decorations parameter of metal level.Actual graphical just is referred to as compensation figure after overcompensation.
Wherein, actual graphical 1 and actual graphical 1 ' be adjacent figure, compensation figure 2 and compensation figure 2 ' be are respectively the figure of actual graphical 1 and actual graphical 1 ' after compensating.Actual graphical 1 and actual graphical 1 ' minimum range be a; Compensation figure 2 and compensation figure 2 ' between minimum range be b; The free size of actual graphical 1 is Δ a, actual graphical 1 ' free size be Δ a ', add that the processing dimension of needs is c in the adjacent pattern in man-hour; Processing dimension c is the width of cutter, just can better when processing spacing only greater than processing dimension c.Δ b for the cutting compensation figure 2 size, Δ b ' cutting compensation figure 2 ' size.
Embodiment one
A kind of processing method of high-density integrated circuit comprises:
Step S101: measure the minimum spacing a between the adjacent actual graphical, and the minimum spacing b between the compensation figure, wherein, b＜a;
Step S102: as said minimum spacing b during less than processing dimension c, the metal level at cutting compensation figure minimum spacing place, its cutting size is respectively Δ b ' and Δ b, makes c≤b+ Δ b '+Δ b＜a.
Embodiment two
Step S201: the overall dimensions to the actual graphical on the substrate compensates, and its free size is (a-b)/2, and b＜a;
Step S202: measure the spacing a between the adjacent actual graphical, and the minimum spacing b between the compensation figure, wherein, b≤a;
Step S203: as said minimum spacing b during less than processing dimension c, the metal level at cutting compensation figure minimum spacing place, its cutting size is respectively Δ b ' and Δ b, makes c≤b+ Δ b '+Δ b＜a.
Embodiment three
Step S301: the overall dimensions to the actual graphical on the substrate compensates, and its free size is (a-b)/2, and b＜a;
Step S302: measure the minimum spacing a between the adjacent actual graphical, and the minimum spacing b between the compensation figure, wherein, b＜a;
Step S303: as said minimum spacing b during less than processing dimension c, the metal level at cutting compensation figure minimum spacing place, its cutting size is respectively Δ b ' and Δ b, makes c≤b+ Δ b '+Δ b＜a;
Step S304: through adopting etch process, with said actual graphical external compensation part.
In the above-described embodiments, the technology that adopts evenly compensation is to actual graphical 1 and actual graphical 1 ' compensate processing, and increasing identical free size around is Δ a for actual graphical 1 its free size; For actual graphical 1 ' its free size is Δ a '.
Preferably, when cutting, preferably satisfy cutting size Δ b '=Δ b; C＜b+ Δ b '+Δ b＜a.
Through adopting above-mentioned processing method, the graphics sub behind the compensate for process is machined away, be met the spacing requirement in the course of processing, make and unnecessary part in the better cutting image of process tool improved machining accuracy.
To the above-mentioned explanation of the disclosed embodiments, make this area professional and technical personnel can realize or use the present invention.Multiple modification to these embodiment will be conspicuous concerning those skilled in the art, and defined General Principle can realize under the situation that does not break away from the spirit or scope of the present invention in other embodiments among this paper.Therefore, the present invention will can not be restricted to these embodiment shown in this paper, but will meet and principle disclosed herein and features of novelty the wideest corresponding to scope.
Claims (6)
1. the processing method of a high-density integrated circuit is characterized in that, comprising:
Step 1: measure the minimum spacing a between the adjacent actual graphical, and the minimum spacing b between the compensation figure, wherein, b＜a;
Step 2: as said minimum spacing b during less than processing dimension c, using width is the metal level at the Tool in Cutting compensation figure minimum spacing place of said processing dimension c, and its cutting size is respectively Δ b ' and Δ b, makes c≤b+ Δ b '+Δ b＜a;
Adopt etch process, remove the outer metal of said actual graphical.
2. method according to claim 1 is characterized in that, taking a step forward in step 1 comprises:
Overall dimensions to the figure on the substrate compensates, and its free size is (a-b)/2, and b＜a.
3. method according to claim 2 is characterized in that, saidly is compensated for as even compensation.
4. method according to claim 3 is characterized in that, comprises further that after said step 2 compensated part of cutting compensation figure obtains actual graphical.
5. method according to claim 4 is characterized in that, said Δ b '=Δ b.
6. method according to claim 5 is characterized in that, said c＜b+ Δ b '+Δ b＜a.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010193150 CN101861056B (en) | 2010-06-03 | 2010-06-03 | Method for processing high-density integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010193150 CN101861056B (en) | 2010-06-03 | 2010-06-03 | Method for processing high-density integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101861056A CN101861056A (en) | 2010-10-13 |
| CN101861056B true CN101861056B (en) | 2012-12-26 |
Family
ID=42946607
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201010193150 Active CN101861056B (en) | 2010-06-03 | 2010-06-03 | Method for processing high-density integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101861056B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103533756A (en) * | 2013-09-29 | 2014-01-22 | 胜宏科技（惠州）股份有限公司 | Method for etching printed circuit board |
| CN105072808B (en) * | 2015-07-09 | 2018-10-02 | 华进半导体封装先导技术研发中心有限公司 | The corresponding etching to compensate method of high-precision package substrate |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6632575B1 (en) * | 2000-08-31 | 2003-10-14 | Micron Technology, Inc. | Precision fiducial |
| CN100505987C (en) * | 2007-01-26 | 2009-06-24 | 上海美维科技有限公司 | Method for improving the line precision in the etching technology |
| CN100550362C (en) * | 2007-10-18 | 2009-10-14 | 晶方半导体科技（苏州）有限公司 | Circuit of a kind of crystal wafer chip dimension encapsulation and preparation method thereof |
| CN101605433A (en) * | 2009-06-26 | 2009-12-16 | 上海美维电子有限公司 | The processing method of buried resistor in a kind of printed circuit board |
-
2010
- 2010-06-03 CN CN 201010193150 patent/CN101861056B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6632575B1 (en) * | 2000-08-31 | 2003-10-14 | Micron Technology, Inc. | Precision fiducial |
| CN100505987C (en) * | 2007-01-26 | 2009-06-24 | 上海美维科技有限公司 | Method for improving the line precision in the etching technology |
| CN100550362C (en) * | 2007-10-18 | 2009-10-14 | 晶方半导体科技（苏州）有限公司 | Circuit of a kind of crystal wafer chip dimension encapsulation and preparation method thereof |
| CN101605433A (en) * | 2009-06-26 | 2009-12-16 | 上海美维电子有限公司 | The processing method of buried resistor in a kind of printed circuit board |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101861056A (en) | 2010-10-13 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US20190198960A1 (en) | Electronic apparatus | |
| US9570378B2 (en) | Semiconductor device including dummy pattern | |
| CN103002660A (en) | Circuit board and processing method thereof | |
| US7205668B2 (en) | Multi-layer printed circuit board wiring layout | |
| EP2988581B1 (en) | Chip heat dissipation structure and terminal device | |
| CN109413881B (en) | Manufacturing method of carbon oil circuit board and solder-mask windowing | |
| CN101588676B (en) | Manufacture method of printed circuit board (PCB) by utilizing photosensitive dry film to realize plugging holes selectively | |
| CN101861056B (en) | Method for processing high-density integrated circuit | |
| CN107529283A (en) | The production technology of FPC | |
| CN105430884A (en) | Flexible circuit board, terminal and preparation method of flexible circuit board | |
| CN110996535B (en) | Method for manufacturing circuit layer stepped copper thick copper base circuit board by using additive method | |
| WO2012087647A1 (en) | Crosstalk reduction for microstrip routing | |
| US7458053B2 (en) | Method for generating fill and cheese structures | |
| JP2005039271A (en) | Printed circuit board and its forming method | |
| JP2006319031A (en) | Printed board and its manufacturing method | |
| CN108235599B (en) | Manufacturing method of PCB with carbon oil finger gap smaller than 0.60mm and outer layer graphic data | |
| JP2010251554A (en) | Printed board and harness | |
| US20060038264A1 (en) | Printed circuit board | |
| JP2008134512A (en) | Method for correcting pattern data, photomask, and circuit board | |
| CN117634403B (en) | Transmission line structure determining method, system, equipment and readable storage medium | |
| JP2007221369A (en) | Manufacturing method of frequency selective surfaces | |
| CN105338743A (en) | Circuit board manufacturing method and circuit board | |
| JP2007207826A (en) | Printed circuit board | |
| US10062981B2 (en) | Ground routing device and method | |
| CN108235568A (en) | A kind of pcb board by the non-functional PAD of PTH through-holes removal internal layer |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C56 | Change in the name or address of the patentee |
Owner name: SHENNAN CIRCUIT CO., LTD. Free format text: FORMER NAME: SHENZHEN SHENNAN CIRCUITS CO., LTD. |
|
| CP01 | Change in the name or title of a patent holder |
Address after: 518053 Nanshan District, Guangdong, overseas Chinese town, No. East Road, No. 99 Patentee after: SHENZHEN SHENNAN CIRCUIT CO., LTD. Address before: 518053 Nanshan District, Guangdong, overseas Chinese town, No. East Road, No. 99 Patentee before: Shenzhen Shennan Circuits Co., Ltd. |