CN101834142A - A kind of have the groove of heavy insulation bottom and a manufacture method of semiconductor device thereof - Google Patents
A kind of have the groove of heavy insulation bottom and a manufacture method of semiconductor device thereof Download PDFInfo
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- CN101834142A CN101834142A CN201010179208A CN201010179208A CN101834142A CN 101834142 A CN101834142 A CN 101834142A CN 201010179208 A CN201010179208 A CN 201010179208A CN 201010179208 A CN201010179208 A CN 201010179208A CN 101834142 A CN101834142 A CN 101834142A
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- 238000000034 method Methods 0.000 title claims abstract description 98
- 238000009413 insulation Methods 0.000 title claims abstract description 65
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 62
- 239000004065 semiconductor Substances 0.000 title claims abstract description 48
- 150000004767 nitrides Chemical class 0.000 claims abstract description 32
- 229910052751 metal Inorganic materials 0.000 claims abstract description 24
- 239000002184 metal Substances 0.000 claims abstract description 24
- 238000000151 deposition Methods 0.000 claims abstract description 22
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 13
- 239000010703 silicon Substances 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 238000005530 etching Methods 0.000 claims description 16
- 230000003647 oxidation Effects 0.000 claims description 16
- 238000007254 oxidation reaction Methods 0.000 claims description 16
- 230000008021 deposition Effects 0.000 claims description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 12
- 229910052785 arsenic Inorganic materials 0.000 claims description 11
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 10
- 229920005591 polysilicon Polymers 0.000 claims description 10
- 230000015572 biosynthetic process Effects 0.000 claims description 8
- 238000000137 annealing Methods 0.000 claims description 7
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 6
- 229910052796 boron Inorganic materials 0.000 claims description 6
- 230000007773 growth pattern Effects 0.000 claims description 6
- 238000009825 accumulation Methods 0.000 claims description 5
- 239000002019 doping agent Substances 0.000 claims description 4
- 238000005498 polishing Methods 0.000 claims description 4
- 230000005669 field effect Effects 0.000 claims 4
- 229910044991 metal oxide Inorganic materials 0.000 claims 2
- 230000012010 growth Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 23
- 108091006146 Channels Proteins 0.000 description 12
- 230000004888 barrier function Effects 0.000 description 8
- 230000008569 process Effects 0.000 description 7
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- 229910000881 Cu alloy Inorganic materials 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- WPPDFTBPZNZZRP-UHFFFAOYSA-N aluminum copper Chemical compound [Al].[Cu] WPPDFTBPZNZZRP-UHFFFAOYSA-N 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 102000004129 N-Type Calcium Channels Human genes 0.000 description 1
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- 238000012797 qualification Methods 0.000 description 1
- 230000008719 thickening Effects 0.000 description 1
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66719—With a step of forming an insulating sidewall spacer
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66727—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the source electrode
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
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Abstract
A kind of have the groove of heavy insulation bottom and a manufacture method of semiconductor device thereof, this method comprises: utilize trench mask that the epitaxial loayer on the substrate is corroded and form a plurality of gate trenchs, and after trenched side-wall and upper edge depositing nitride, generate the 3rd oxide layer at channel bottom; Remove nitride, deposit spathic silicon in groove, and generate the 4th oxide layer, finish the manufacturing of groove; Utilize base mask and active region mask to form base and source region then respectively, utilize contact hole mask to form contact trench and trench plug, and utilize metal mask to carry out metal attack, form the manufacturing that metal bed course and line are finished device.Manufacture method of the present invention makes the electrical quantitys of making such as device threshold voltage have consistency owing to guaranteed the consistency of side wall grid oxide layer, and the manufacture method of device is simple, easy, realizes easily.
Description
Technical field
The present invention relates to a kind of semiconductor device, relate in particular to the manufacture method of a kind of groove and grooved semiconductor device.
Background technology
In existing grooved semiconductor device manufacturing processes, adopt the method for silicon selective oxidation (LOCOS) to generate the gate leakage capacitance that thick dielectric layer is improved device usually at channel bottom, reach the purpose that reduces device grid electric charge, improve the efficient of device.But, generate in the process of thick dielectric layer at channel bottom in the method that adopts silicon selective oxidation (LOCOS), when nitride is carried out anisotropic etching, the nitride of groove upper edge part is removed, following thin oxide layer is exposed, the result is when generating the channel bottom thick oxide layer, and the oxide layer of groove upper edge is thickening also, has influenced the consistency of electrical quantitys such as device threshold voltage.Figure 23 deposits the schematic diagram of gate oxide and nitride in trenched side-wall and upper edge for the method that adopts silicon selective oxidation (LOCOS), as shown in figure 23, deposit the thin gate oxide of one deck at trenched side-wall and upper edge, deposit one deck nitride again at the gate oxide outer surface.Figure 24 is for after the available technology adopting anisotropic etching handles, gate oxide schematic diagram in trenched side-wall and upper edge deposition, as shown in figure 24, the gate oxide that deposits in the groove upper edge becomes thicker, and the thickness of grid oxide layer of trench sidewall deposition is also inhomogeneous.
American documentation literature (US6551900B1) discloses a kind of formation method of trench-gate oxide, in the method, utilize deposition to add the thick dielectric layer that etching method generates channel bottom, but by this method, be difficult to make the thickness of channel bottom thick dielectric layer to be consistent.
Chinese patent literature (CN200910150226.9) discloses a kind of method that is formed for the structure of the thick bottom-dielectric of trench-gate device (TBD), this method discloses the use mask and formed a plurality of grooves in semiconductor region, mask comprises lip-deep first insulating barrier of semiconductor region, first oxidation barrier layer on first insulating barrier, and second insulating barrier on first oxidation barrier layer.First oxidation barrier layer prevents that the surface along semiconductor region forms dielectric layer in the process that forms TBD.Adopt above-mentioned method in the thick bottom-dielectric structure of trench-gate device owing to make the technical process more complicated of trench-gate device, the production control difficulty is bigger.
Summary of the invention
In order to solve the deficiency that prior art exists, the invention provides a kind of groove and method, semi-conductor device manufacturing method thereof with heavy insulation bottom, guaranteed the consistency of trenched side-wall grid oxic horizon (insulating barrier), adopt control method simply, reach the consistency of electrical quantitys such as threshold voltage, reduced the manufacturing process of device, the pollution of having avoided relevant operation to cause, improve the q﹠r of device, reduced cost and manufacturing time simultaneously.
To achieve these goals, according to the trench fabrication methods with heavy insulation bottom of the present invention, this method may further comprise the steps:
1) utilize trench mask that the epitaxial loayer on the substrate is corroded and form a plurality of gate trenchs, and in trenched side-wall and upper edge depositing nitride;
2) generate the 3rd oxide layer at channel bottom, and remove nitride;
3) deposit spathic silicon in groove, and generate the 4th oxide layer.
Further, the step 1) of described trench fabrication methods is further comprising the steps of:
A) deposition first oxide layer on the epitaxial loayer of substrate;
B) place trench mask on first oxide layer surface and corrode first oxide layer, expose the part of epitaxial loayer, and generate second oxide layer at the upper surface of the epitaxial loayer that exposes;
C) depositing nitride, and it is carried out anisotropic etching, expose the part epitaxial loayer;
D) the epitaxial loayer expose portion is carried out etching and form groove, and described groove carries out the sacrificial oxidation processing;
E) form grid oxic horizon in groove side surface and bottom;
F) depositing nitride, and it is carried out anisotropic etching, remove the nitride of the channel bottom and the first oxide layer upper surface, keep the nitride of trenched side-wall and upper edge.
Further, the step 2 of described trench fabrication methods) further comprising the steps of:
A) adopt the method for silicon selective oxidation to generate the 3rd oxide layer at described channel bottom;
B) nitride of described trenched side-wall of removal and upper edge.
Further, the step 3) of described trench fabrication methods is further comprising the steps of:
A) deposit spathic silicon filling groove in described groove, and make its covering groove end face and the first oxide layer upper surface;
B) adopt the method for chemico-mechanical polishing remove the polysilicon of covering groove end face, first oxide layer with and the polysilicon of upper surface;
C) upper surface at described groove end face and epitaxial loayer generates the 4th oxide layer.
To achieve these goals, according to a kind of grooved semiconductor device making method with heavy insulation bottom of the present invention, this method may further comprise the steps:
1) has the manufacturing of the groove of heavy insulation bottom;
2) utilize base and active region mask to form base and source region respectively;
3) generate inter-level dielectric, by contact hole mask, it is corroded the formation contact trench, and contact trench is filled the formation trench plug;
4) utilize metal mask to carry out metal attack, form metal bed course and line.
Further, the step 1) of described method, semi-conductor device manufacturing method comprises the trench fabrication methods that has the heavy insulation bottom according to of the present invention.
To achieve these goals, according to a kind of grooved semiconductor device making method with heavy insulation bottom of the present invention, this method may further comprise the steps further:
1) utilizes the base mask to inject boron element, form the base;
2) manufacturing of the groove of heavy insulation bottom;
3) utilize contact hole mask etching the 4th oxide layer and first oxide layer, right Hou is injected arsenic element, forms the second portion source region;
4) utilize contact hole mask, the epitaxial loayer that contains dopant is carried out etch, generate contact trench, and contact trench is filled the formation trench plug;
5) utilize metal mask, form metal bed course and line.
Further, also comprise before the step 1) of described method, semi-conductor device manufacturing method: on the epitaxial loayer of substrate, adopt accumulation or hot growth pattern to generate the step of first oxide layer.
Further, the step 2 of described method, semi-conductor device manufacturing method) further comprising the steps of:
A) manufacturing of the groove of heavy insulation bottom;
B) in the process of groove manufacturing, inject arsenic element to the epitaxial loayer that exposes, and adopt the annealing operation that the arsenic element propelling is diffused into epitaxial loayer, form the first source region.
C) in the process that groove is made,, only remove the first oxide layer top polysilicon at Hua Ji tool Pao Guang Time.
The present invention has tangible advantage and good effect, adopt manufacture method of the present invention, guaranteed to have the consistency of the trenched side-wall grid oxic horizon (insulating barrier) of heavy insulation bottom, reduced the manufacturing process of the semiconductor device of groove, guaranteed the consistency of the electrical quantitys such as threshold voltage of semiconductor device with heavy insulation bottom; Because manufacture method of the present invention is simple, easy, manufacturing process realizes easily, and the quality of device and reliability are greatly improved.
Description of drawings
Accompanying drawing is used to provide further understanding of the present invention, and constitutes the part of specification, with embodiments of the invention, is used to explain the present invention, is not construed as limiting the invention.In the accompanying drawings:
Fig. 1 is the trench fabrication methods flow chart with heavy insulation bottom according to the present invention;
Fig. 2 is for having first an oxide layer schematic diagram that deposits in the trench fabrication methods of heavy insulation bottom according to of the present invention;
Fig. 3 is for placing trench mask and utilize the trench mask etching first oxide layer schematic diagram in the trench fabrication methods with heavy insulation bottom according to the present invention;
Fig. 4 is for having second an oxide layer schematic diagram that generates in the trench fabrication methods of heavy insulation bottom according to of the present invention;
Fig. 5 is for having the nitride that deposits in the trench fabrication methods of heavy insulation bottom and an epitaxial loayer schematic diagram of exposure according to of the present invention;
Fig. 6 makees the sacrificial oxidation schematic diagram for etched trench in the trench fabrication methods with heavy insulation bottom according to the present invention and to flute surfaces;
Fig. 7 is for having a grid oxic horizon schematic diagram that forms in the trench fabrication methods of heavy insulation bottom according to of the present invention;
Fig. 8 is the nitride schematic diagram of trenched side-wall surface deposition in the trench fabrication methods with heavy insulation bottom according to the present invention;
The three oxide layer schematic diagram of Fig. 9 for generating at channel bottom in the trench fabrication methods with heavy insulation bottom according to the present invention;
Figure 10 is for having a polysilicon schematic diagram that deposits in the trench fabrication methods of heavy insulation bottom according to of the present invention;
Figure 11 is for having the 4th an oxide layer schematic diagram that forms in the trench fabrication methods of heavy insulation bottom according to of the present invention;
Figure 12 is grooved semiconductor device making method embodiment 1 flow chart with heavy insulation bottom according to the present invention;
The grooved semiconductor device architecture schematic diagram that Figure 13 makes for the grooved semiconductor device making method embodiment 1 with heavy insulation bottom according to the present invention;
Figure 14 is grooved semiconductor device making method embodiment 2 flow charts with heavy insulation bottom according to the present invention;
Figure 15 is for utilizing the base mask to inject boron element, the base schematic diagram of formation in the grooved semiconductor device making method with heavy insulation bottom according to the present invention;
Figure 16 is for having the nitride that deposits in the grooved semiconductor device making method of heavy insulation bottom and an epitaxial loayer schematic diagram of exposure according to of the present invention;
Figure 17 is for having the 4th an oxide layer schematic diagram that generates in the grooved semiconductor device making method of heavy insulation bottom according to of the present invention;
Figure 18 is for utilizing contact hole mask exposed portions epitaxial loayer schematic diagram in the grooved semiconductor device making method with heavy insulation bottom according to the present invention;
Figure 19 is for forming second portion source region schematic diagram in the grooved semiconductor device making method with heavy insulation bottom according to the present invention;
Figure 20 is for having a contact hole schematic diagram that forms in the grooved semiconductor device making method of heavy insulation bottom according to of the present invention;
Figure 21 is for injecting the schematic diagram of p+ in contact hole in the grooved semiconductor device making method with heavy insulation bottom according to the present invention;
Figure 22 is for having metal bed course and a metal connecting line schematic diagram that utilizes metal mask to form in the grooved semiconductor device making method of heavy insulation bottom according to of the present invention;
Figure 23 is the schematic diagram of the method for available technology adopting silicon selective oxidation (LOCOS) at trenched side-wall and upper edge deposition gate oxide and nitride;
Figure 24 is for after the available technology adopting anisotropic etching handles, at the gate oxide schematic diagram of trenched side-wall and upper edge deposition.
Embodiment
Below in conjunction with accompanying drawing the preferred embodiments of the present invention are described, should be appreciated that preferred embodiment described herein only is used for description and interpretation the present invention, and be not used in qualification the present invention.
Fig. 1, is described in detail the trench fabrication methods with heavy insulation bottom of the present invention below with reference to Fig. 1 for the trench fabrication methods flow chart with heavy insulation bottom according to the present invention:
At first, in step 101, on the epitaxial loayer of substrate, adopt accumulation or hot growth pattern to generate first oxide layer (oxide hard light shield), as shown in Figure 2, then, utilize the trench mask on first oxide layer to corrode first oxide layer, expose the part epitaxial loayer, as shown in Figure 3.
In step 102, adopt accumulation or hot growth pattern to generate second oxide layer, as shown in Figure 4 at the epitaxial loayer part upper surface that exposes.
In step 103, at first,, and then utilize the anisotropic etch to remove the nitride on first oxide layer and the part second oxide layer surface at second oxide layer and the first oxide layer surface deposition nitride, expose the part epitaxial loayer, as shown in Figure 5.
In step 104, at first, the part epitaxial loayer that exposes in the step 103 is carried out etching form groove, then, flute surfaces is carried out sacrificial oxidation handle the silicon layer that in grooving process, is destroyed to eliminate by plasma.As shown in Figure 6, in the groove upper edge that forms, keeping the nitride of deposition.
In step 105, adopt hot growth pattern on the surface of groove, to generate grid oxic horizon.As shown in Figure 7, the grid oxic horizon that one deck of generation is thin covers the both sides and the lower surface of groove.
In step 106, at first, the gate oxidation laminar surface and the first oxide layer surface deposition nitride that on the both sides of groove and bottom, generate, then, utilize the anisotropic etch to remove the nitride on the channel bottom gate oxidation laminar surface and the first oxide layer surface again, make grid oxic horizon surface deposition one deck nitride of groove both sides, as shown in Figure 8.
In step 107, utilize the method for silicon selective oxidation (LOCOS) to generate the 3rd oxide layer at channel bottom.As shown in Figure 9, the 3rd oxide layer that generates at channel bottom is the oxide layer of a bed thickness.
In step 108, generate the 4th oxide layer at groove top and epi-layer surface.This step comprises:
1) removes the nitride on trenched side-wall surface, be formed with the 3rd oxide layer (thick oxide layer) in the bottom of groove, sidewall is formed with the layer of even gate oxide;
2) deposition comprises the polysilicon of dopant in groove, with filling groove and cover the top and first oxide layer, as shown in figure 10;
3) utilize the method for chemico-mechanical polishing, remove polysilicon and first oxide layer and the surperficial polysilicon thereof at groove top;
4) generate the 4th oxide layer at groove top and epi-layer surface, as shown in figure 11.
Figure 12, is described in detail the grooved semiconductor device making method embodiment 1 with heavy insulation bottom of the present invention below with reference to Figure 12 for grooved semiconductor device making method embodiment 1 flow chart with heavy insulation bottom according to the present invention:
At first,, adopt the step 101 of trench fabrication methods that as shown in Figure 1 of the present invention have the heavy insulation bottom, finish groove manufacturing with heavy insulation bottom to 108 in step 1201;
In step 1202, placement base and active region mask ， And inject boron and arsenic element respectively on the 4th oxide layer, and the operation of annealing forms base and source region;
In step 1203, remove base and active region mask after, on the 4th oxide layer, generate inter-level dielectric, by contact hole mask, to inter-level dielectric, source region and base corrode the formation contact trench, and contact trench carried out the filling of titanium/titanium nitride and tungsten, form trench plug;
At last,,, utilize metal mask to carry out metal attack, form metal bed course and line at Top lamination shallow lake Aluminum Copper alloy in step 1204.Semiconductor device structure as shown in figure 13 after finishing.
Figure 14, is described in detail the grooved semiconductor device making method with heavy insulation bottom of the present invention below with reference to Figure 14 for the grooved semiconductor device making method flow chart with heavy insulation bottom according to the present invention:
At first, in step 1401, on the epitaxial loayer of substrate, adopt accumulation or hot growth pattern to generate first oxide layer (oxide hard light shield), then, utilize the base mask to inject boron element, adopt the annealing operation that boron element is advanced again and be diffused into epitaxial loayer, form the base, as shown in figure 15.
In step 1402, the step 101 of trench fabrication methods flow chart that has the heavy insulation bottom according to as shown in Figure 1 of the present invention is to 108 manufacturings of finishing groove; Wherein different places has two: first, after utilizing the anisotropic etch to remove the nitride on first oxide layer and the part second oxide layer surface, to inject arsenic element to the epitaxial loayer that exposes, and adopt the annealing operation that the arsenic element propelling is diffused into epitaxial loayer, form the first source region, as shown in figure 16, just carry out etching then and form groove; Second, when chemico-mechanical polishing, keep first oxide layer, only remove the first oxide layer top polysilicon, as shown in figure 17.
In step 1403, place contact hole mask on the 4th oxide layer surface, and etching the 4th oxide layer and first oxide layer, expose the part epitaxial loayer, as shown in figure 18; Inject arsenic element to the epitaxial loayer that exposes, and adopt the annealing operation that the arsenic element propelling is diffused into epitaxial loayer, form the second portion source region, as shown in figure 19.
In step 1404, the epitaxial loayer that contains dopant is corroded, make contact trench deeper pass the second portion source region and enter into the base, as shown in figure 20; Inject p+ to contact trench, and adopt quick high-temp annealing operation, p+ is advanced be diffused into the first base, as shown in figure 21; And, to contact trench fill tungsten, form trench plug again at trenched side-wall, bottom and epitaxial loayer upper surface deposition one deck titanium/titanium nitride layer.
At last,,, carry out metal attack by metal mask then, form metal bed course and line, as shown in figure 22 at titanium/titanium nitride layer upper surface deposition layer of aluminum copper alloy in step 1405.
The foregoing description is that the manufacture process with the N type channel groove N-type semiconductor N power device with heavy insulation bottom describes, manufacturing for P type passage semiconductor power device with heavy insulation bottom, main difference is the type of alloy, adopt the method for the foregoing description, change the type of alloy, can be used to make P type passage semiconductor device equally with heavy insulation bottom.
One of ordinary skill in the art will appreciate that, the above only is the preferred embodiments of the present invention, be not limited to the present invention, the present invention not exclusively relates to the technology and the corresponding device of be used for producing the semiconductor devices (for example, device or the bipolar diode or the Schottky diode of the device of MOS device or igbt (IGBT) type or bipolar junction transistor (BJT) type).
Although with reference to previous embodiment the present invention is had been described in detail, for a person skilled in the art, it still can be made amendment to the technical scheme of previous embodiment record, perhaps part technical characterictic wherein is equal to replacement.Within the spirit and principles in the present invention all, any modification of being done, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (13)
1. manufacture method with groove of heavy insulation bottom, this method may further comprise the steps:
1) utilize trench mask that the epitaxial loayer on the substrate is corroded and form a plurality of gate trenchs, and in trenched side-wall and upper edge depositing nitride;
2) generate the 3rd oxide layer at channel bottom, and remove nitride;
3) deposit spathic silicon in groove, and generate the 4th oxide layer.
2. the manufacture method with groove of heavy insulation bottom according to claim 1 is characterized in that described step 1) further may further comprise the steps:
A) deposition first oxide layer on the epitaxial loayer of substrate;
B) place trench mask etch first oxide layer on first oxide layer surface, expose the part of epitaxial loayer, and generate second oxide layer at the upper surface of the epitaxial loayer that exposes;
C) depositing nitride, and it is carried out anisotropic etching, expose the part epitaxial loayer;
D) the epitaxial loayer expose portion is carried out etching and form groove, and described groove carries out the sacrificial oxidation processing;
E) form grid oxic horizon in groove both sides and lower surface;
F) depositing nitride, and it is carried out anisotropic etching, remove the nitride of the channel bottom and the first oxide layer upper surface, keep the nitride on groove both sides and surface, upper edge.
3. the manufacture method with groove of heavy insulation bottom according to claim 1 is characterized in that described step 2) further may further comprise the steps:
A) adopt the method for silicon selective oxidation to generate the 3rd oxide layer at described channel bottom;
B) nitride of described trenched side-wall of removal and upper edge.
4. the manufacture method with groove of heavy insulation bottom according to claim 1 is characterized in that described step 3) further may further comprise the steps:
A) deposit spathic silicon filling groove in described groove, and make its covering groove end face and the first oxide layer upper surface;
B) method of employing chemico-mechanical polishing is removed polysilicon and first oxide layer and the surperficial polysilicon thereof of covering groove end face;
C) upper surface at described groove end face and epitaxial loayer generates the 4th oxide layer.
5. the manufacture method with groove of heavy insulation bottom according to claim 2 is characterized in that, described step e) is to adopt the mode by the heat growth to generate in groove both sides and lower surface formation grid oxic horizon.
6. grooved semiconductor device making method with heavy insulation bottom, this method may further comprise the steps:
1) has the manufacturing of the groove of heavy insulation bottom;
2) utilize base and active region mask to form base and source region respectively;
3) generate inter-level dielectric,, form contact trench and trench plug by contact hole mask;
4) utilize metal mask to carry out metal attack, form metal bed course and line.
7. the grooved semiconductor device making method with heavy insulation bottom according to claim 6 is characterized in that, described step 1) is to adopt any described manufacture method with groove of heavy insulation bottom of claim 1-5.
8. grooved semiconductor device making method with heavy insulation bottom, this method may further comprise the steps:
1) utilizes the base mask to inject boron element, form the base;
2) has the manufacturing of the groove of heavy insulation bottom;
3) utilize contact hole mask etching the 4th oxide layer and first oxide layer, inject arsenic element then, form the second portion source region;
4) utilize contact hole mask, the epitaxial loayer that contains dopant is corroded, generate contact trench, and contact trench is filled the formation trench plug;
5) utilize metal mask, form metal bed course and line.
9. the grooved semiconductor device making method with heavy insulation bottom according to claim 8 is characterized in that, also comprises before described step 1): adopt accumulation or hot growth pattern to generate the step of first oxide layer on the epitaxial loayer of substrate.
10. the grooved semiconductor device making method with heavy insulation bottom according to claim 8, it is characterized in that, described step 2) manufacturing with groove of heavy insulation bottom is to adopt the described manufacture method with groove of heavy insulation bottom of claim 4 to make groove, and after described step b), c) inject arsenic element to the epitaxial loayer that exposes before, and adopt the annealing operation that the arsenic element propelling is diffused into epitaxial loayer, form the first source region;
11. the grooved semiconductor device making method with heavy insulation bottom according to claim 8, it is characterized in that, described step 2) manufacturing with groove of heavy insulation bottom is to adopt the described manufacture method with groove of heavy insulation bottom of claim 4 to make groove, and keeps first oxide layer in described step b).
12. a groove type power metallic oxide/semiconductor field-effect tube is characterized in that, the N channel groove type power metal oxide-semiconductor field effect transistor that adopts each described method manufacturing of claim 6-11 to form.
13. a groove type power metallic oxide/semiconductor field-effect tube is characterized in that, the P channel groove type power metal oxide-semiconductor field effect transistor that adopts each described method manufacturing of claim 6-11 to form.
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| CN2010101792086A CN101834142B (en) | 2010-05-21 | 2010-05-21 | Method for manufacturing flute with thick insulating bottom and semiconductor device thereof |
| PCT/CN2010/073934 WO2011143836A1 (en) | 2010-05-21 | 2010-06-13 | Method for manufacturing trench with thick insulating bottom and semiconductor device thereof |
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| CN2010101792086A CN101834142B (en) | 2010-05-21 | 2010-05-21 | Method for manufacturing flute with thick insulating bottom and semiconductor device thereof |
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| CN101834142B CN101834142B (en) | 2012-11-14 |
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| WO2012055288A1 (en) * | 2010-10-27 | 2012-05-03 | 香港商莫斯飞特半导体有限公司 | Self-aligned metal silicide groove-type semiconductor device and manufacturing method thereof |
| CN103187292A (en) * | 2011-12-29 | 2013-07-03 | 立新半导体有限公司 | Method of manufacturing trench semiconductor power device |
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Also Published As
| Publication number | Publication date |
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| CN101834142B (en) | 2012-11-14 |
| WO2011143836A1 (en) | 2011-11-24 |
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