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CN101819928B - 制造具有减少的栅极氧化物泄漏的取代金属栅极晶体管的方法 - Google Patents

制造具有减少的栅极氧化物泄漏的取代金属栅极晶体管的方法 Download PDF

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CN101819928B
CN101819928B CN201010145534.5A CN201010145534A CN101819928B CN 101819928 B CN101819928 B CN 101819928B CN 201010145534 A CN201010145534 A CN 201010145534A CN 101819928 B CN101819928 B CN 101819928B
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J·潘
J·佩尔兰
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Abstract

本发明公开了一种具有减少的栅极氧化物泄漏的取代金属栅极晶体管，通过在栅极氧化物层与金属栅极电极之间形成保护层来达成用于取代金属栅极晶体管的具有减少的泄漏的薄而有效的栅极氧化物厚度，因而减少应力。实施例包括形成含有金属碳化物的非晶形碳的保护层，该金属碳化物的浓度从该金属栅极电极朝向该栅极氧化物层跨过该保护层而降低。方法的实施例包括移除可移除的栅极，在栅极氧化物层上沉积非晶形碳层，形成金属栅极电极，及然后在升高的温度加热以使金属从该金属栅极电极扩散进入该非晶形碳层，因而形成金属碳化物。实施例亦包括具有高介电常数的栅极氧化物层及硅集中在该金属栅极电极与衬底的接口处的金属栅极晶体管。

Description

制造具有减少的栅极氧化物泄漏的取代金属栅极晶体管的方法
本申请是申请号为200680040575.X，申请日为2006年11月2日，发明名称为“具有减少的栅极氧化物泄漏的取代金属栅极晶体管”的分案申请。 
技术领域
本发明是关于包括晶体管的半导体器件，该等晶体管具有金属栅极电极与减少的栅极氧化物泄漏(leakage)。本发明特别可应用于具有次微米(submicron)设计特征的高速半导体器件。 
背景技术
在单一集成电路上整合数亿个电路元件(例如晶体管)需要使电路元件包括互连(interconnection)结构的实际尺寸更可观的缩小或微小型化(micro-miniaturization)。微小型化已在晶体管工程复杂度上产生可观的增加，诸如包含渐变式井掺杂(graded well-doping)、外延生长(epitaxial)的晶片、环形注入物(halo implant)、尖端注入物(tip implant)、轻浓度掺杂(lightly doped)漏极结构、用于源极/漏极区域的多种注入物、栅极与源极/漏极的硅化(silicidation)及多种侧壁间隔件(sidewall spacer)。 
高效能的需求需要微电子组件的高速操作，而该等微电子组件除了低泄漏外(亦即，低截止状态电流(low off-state current))还需要高驱动电流，以降低电力消耗。结构与掺杂参数典型地倾向于提供所希望的驱动电流的增加，而不利地影响泄漏电流。 
金属栅极电极已进化成通过减少多晶硅耗乏(polysilicon depletion)用来改善驱动电流，并降低形成金属栅极后的处理温度。为实行取代金属栅极的处理流程，通过干/湿蚀刻来移除假栅极(dummy gate)(例如多晶硅)，然后进行金属沉积。 
对于更微小型化的持续需求需要减小晶体管的特征尺寸，包括用于金属栅极晶体管的栅极氧化物层。必须减小此等栅极氧化物层以达 成极薄的有效氧化物厚度(effective oxide thickness，EOT)。但因为有泄漏电流，企图形成厚度约15埃()的栅极氧化物的此目的不切实际。 
因此，需要具有减小的EOT及减小的泄漏电流的栅极氧化物的金属栅极晶体管。亦需要能制造包括具有减小的EOT的栅极氧化物的金属栅极晶体管的半导体器件而不需牺牲器件速度的方法。 
发明内容
本发明的优点为一种具有晶体管的半导体器件，该晶体管减小的EOT及减少的泄漏电流的栅极氧化物与金属栅极电极。 
本发明的另一优点为一种制造包括晶体管的半导体器件的方法，该晶体管具有减少的EOT及减少的泄漏电流的栅极氧化物与金属栅极电极。 
将在以下说明中提出本发明的额外优点及其他特征，且该等额外优点及其他特征部份在该技术领域具有通常知识者在查看过下列说明后将变的明白，或部份可从本发明的实施而了解。如在所附权利要求书中特别指出者，可实现及获得本发明的优点。 
根据本发明，通过一种半导体器件部份地达成前述及其他优点，该半导体器件包括：衬底；在该衬底上的栅极介电层；在该栅极介电层上的保护层；以及在该保护层上的金属栅极电极；其中，该保护层在该栅极介电层与该金属栅极电极之间具有渐变的组成(gradedcomposition)。 
本发明的实施例包括具有栅极氧化物(例如，氧化硅)及其上的保护层的金属栅极晶体管。此实施例的态样包括保护层，该保护层包括含有金属碳化物的非晶形碳(amorphous carbon)层，该金属碳化物通过在浓度高达约原子百分比(at.％)50％时使金属从栅极电极扩散进入该非晶形碳层而形成。典型地，金属碳化物的浓度在接近非晶形碳层与金属栅极电极之间的接口为约原子百分比80％，并跨过该非晶形碳层而在与栅极氧化物层的接口处减少至约原子百分比20％。实施例亦包括沉积含有至少一种额外元素(例如氧、硅及/或氮)的非晶形碳层。 
本发明的另一态样为一种半导体器件，包括：衬底；在该衬底上的栅极介电层；以及，在该栅极介电层上的金属栅极电极；其中，该 栅极介电层包括氧化物层，该氧化物层含有具有大于4的介电常数(k)的氧化物；以及硅，集中在该氧化物层与该衬底及与该金属栅极电极的接口处。 
实施例包括形成栅极介电层，该栅极介电层包括在衬底上的多晶硅层、在第一多晶硅层上的含有高介电常数氧化物的氧化物层、及在氧化物层上与金属栅极电极邻近的第二多晶硅层。 
本发明的另一态样为一种制造具有金属栅极电极的晶体管的半导体器件的方法，该方法包括下列步骤：在衬底之上形成可移除的栅极，该衬底与该可移除的栅极之间具有栅极介电层；在该衬底之上形成介电层并将该可移除的栅极的上表面暴露出来；移除该可移除的栅极，留下在该介电层中的由该栅极介电层定义其底部并由该介电层的暴露表面定义其侧边的开孔(opening)；在该栅极介电层上形成保护层并作为该开孔的衬里(lining)；以及在该开孔中形成金属栅极电极；其中，该保护层在该栅极介电层与该金属栅极电极之间具有渐变的组成。 
实施例包括通过化学气相沉积(CVD)或原子层沉积(ALD)来沉积非晶形碳层，并加热至升高的温度以扩散金属(例如，钴(Co)、镍(Ni)、钽(Ta)或钼(Mo))进入该非晶形碳层来形成金属碳化物，该金属碳化物的浓度从金属栅极电极跨过该非晶形碳层至该栅极介电层而减少。 
对熟习此技术领域者而言，从下列的详述将使本发明的额外优点变的明白，其中所描述的本发明的实施例，仅通过所思及用于实行本发明的最优模式来说明。应了解，本发明能有其他及不同的实施例，且其数项细节能在各种明显态样中修改，而皆不脱离本发明。因此，所附图式及叙述在本质上视为例示的，而非限制的。 
附图说明
图1至7示意地显示根据本发明实施例的方法的连续阶段；以及 
图8至12代表本发明的另一实施例的连续阶段。 
在图1至12中，相似的元件符号代表相似的特征。 
具体实施方式
本发明提出并解决关于形成多晶硅栅极电极的习知实施所带来的 问题，该等问题是由其高电阻系数所造成，并因此降低了操作速度。本发明亦提出并解决企图减小取代金属栅极晶体管的栅极氧化物厚度所带来的问题，例如增加的泄漏电流及降低的操作速度。 
本发明提出并通过提供没有增加泄漏并具有减小的EOT的栅极氧化物(例如，具有小于15埃(诸如5埃至12埃的厚度，例如，10埃)的厚度的栅极氧化物)的金属栅极晶体管，及通过包括在栅极氧化物层上形成保护层的技术，其中该保护层在该栅极氧化物层与该栅极电极层之间具有渐变的组成(graded composition)，来解决此等问题。渐变保护层的形成减少了在该栅极电极与该栅极氧化物层之间的应力(stress)，因而减少了缺陷，并因此减少了泄漏电流。 
根据本发明的实施例，在移除了可移除的或“假”栅极(例如多晶硅栅极)后，在暴露的栅极氧化物上沉积非晶形碳层并作为通过移除该“假”栅极所产生的开孔的衬里。然后接着通过化学机械研磨(CMP)沉积金属层(例如Ta、Ni、Co、Mo)以形成取代金属栅极。然后，进行加热将来自金属栅极电极的金属扩散进入非晶形碳层以形成金属碳化物。 
本发明的实施例包括加热至约300℃至600℃的温度(例如，400℃)约30秒至约5分钟，在真空下或适当大气下，例如氩、氮或含有约体积百分比(vol.％)4％的氢及约体积百分比96％的氮的混和气体(forming gas)。在加热期间，如在高达约原子百分比50％的量时，来自栅极电极的金属扩散进入非晶形碳层并形成金属碳化物。保护层所造成的结构为渐变的组成，该金属碳化物在非晶形碳层与栅极电极的接口处含有较高量的金属碳化物，其跨过该非晶形碳层至栅极氧化物层而减少。本发明的实施例包括加热以扩散来自金属栅极电极的金属进入非晶形碳层以形成包括在接近与取代金属栅极电极的接口约原子百分比80％金属碳化物的渐变的组成，该金属碳化物的浓度跨过该非晶形碳层而逐渐降低至接近与栅极氧化物层的接口约原子百分比20％的浓度。渐变的组成有利地增强栅极氧化物层与金属栅极电极之间的相容性，因而减少应力，并因此减少缺陷而造成减少的泄漏电流及增加的操作速度。 
在本发明的另一实施例中，栅极氧化物层由高介电常数材料(例如， 1为以真空为基础，具有介电常数(k)大于或等于4的介电材料)形成。本发明的实施例包括从具有介电常数(k)为4至小于约500(例如，约4至小于约40)的介电材料形成栅极介电层。本发明的实施例亦包括从具有介电常数(k)约4至约30(例如，约4至约20)的介电材料形成栅极介电材料。适合的介电材料包括氧化钽(Ta2O5)、氧化铪(Hf2O3)及硫化硅铪(HfSiS3)。在此等实施例中，已发现有利于在该栅极氧化物层与衬底之间的接口处及在该栅极氧化物层与取代金属栅极电极之间的接口处形成具有高浓度的硅的栅极氧化物层。其他实施例包括在高介电常数的栅极氧化物层与衬底之间的接口处形成多晶硅层，及在高介电常数的栅极氧化物层与取代金属栅极电极之间的接口处形成多晶硅层。 
本发明的实施例示意地显示在图1至7中。注意到图1，暂时可取代的或假栅极11(例如多晶硅)形成于衬底10上，并有栅极介电层12夹在这两者之间(例如氧化硅)。本发明的实施例亦包括沉积高介电常数材料，用于栅极介电层12，例如ZrO2、HfO2、Hf2O3、HfSiO3、InO2、LaO2、Ta2O3及TaO2。然后形成浅源极/漏极延伸部13。然后，在可移除的栅极11上形成介电侧壁间隔件15，例如氧化硅、氮化硅或氧氮化硅。然后进行离子注入(ion implantation)以形成深源极/漏极区域14，接着进行硅化以形成金属硅化层16在源极/漏极区域13的暴露表面上，例如通过沉积镍(Ni)层然后加热的硅化镍。图1中所示的操作步骤以习知方式实行。 
注意到图2，沉积介电材料层(例如氧化硅(例如由四乙基氧硅(tetraethyl orthosilicate，TEOS)形成的氧化硅))接着由化学机械研磨(CMP)形成介电层20。应了解，在图1或图2中显示的阶段，或甚至在沉积取代金属栅极电极之前的在图3中显示的阶段，浅源极/漏极延伸部13与源极/漏极区域14通过高温热退火(例如在约900℃及以上的温度)而活化(activate)。 
如图3中所示，如通过蚀刻(例如，利用氢氟酸与硝酸在醋酸中的溶液)，移除取代或假栅极11。根据此实施例的态样，沉积非晶形碳层40作为通过移除假多晶硅栅极11所产生的开孔的衬里，如图4中示意地显示者。本发明的实施例包括通过CVD或ALD沉积非晶形碳层40。典型地非晶形碳层沉积厚度高达约50埃，例如约10至约50埃(例如， 约25至35埃)。通过沉积非晶形碳层在约30埃的厚度可获得合适的结果。 
接着，如图5中所示，如通过物理气相沉积技术，沉积导电材料(例如钽、镍、钴及钼)层50。本发明的实施例包括沉积最初的金属(例如钽、镍、钴或钼)层，然后沉积铜(Cu)或铜合金层。然后实行CMP以平坦化所沉积的导电材料的上表面，因而完成如图6中所示的金属栅极60。 
在本发明的另一实施例中，通过CVD沉积非晶形碳层，并包含至少一种元素(例如氧、硅及氮)。实施例包括通过利用氧、硅烷(silane)(SiH4)及氮的CVD的沉积。在最初的非晶形碳层中的氧、硅及/或氮的夹杂物进一步减少应力及由应力所造成的缺陷，因而减少了泄漏电流。 
接着，加热典型地实行在约300℃至约600℃的温度(例如，400℃)约30秒至约5分钟，在真空下或在适当大气下，例如，氩、氮或含有约体积百分比4％的氢及约体积百分比96％的氮的混和气体。在加热期间，来自取代金属栅极的金属扩散进入非晶形碳层40形成碳化物，该碳化物的浓度从在非晶形电流层40与金属栅极60之间的接口跨过非晶形碳层40朝向栅极介电层12逐渐减少。所造成的结构显示在图7中，元件70代表具有金属碳化物于其中的非晶形碳的保护层。 
加热典型地在足以形成高达原子百分比50％的金属碳化物的条件下进行。金属碳化物浓度范围典型地从在接近保护层70与金属栅极电极60之间的接口约原子百分比80％，跨过保护层70的厚度而逐渐在接近保护层70与栅极氧化物层12之间的接口减少至约原子百分比20％。具有渐变的组成的保护层70改善了相容性因而减少了应力，并因此，减少了在栅极电极/栅极氧化物接口处所产生的缺陷。以此方式，EOT能显著地减小而不会有伴随的不利的泄漏电流的增加。 
本发明的另一实施例示意地显示在图8至12中。注意到图8，处理如图1至3般实行，图8实质上对应至图3。于此时，栅极氧化物层通过使用习知的氢氟酸蚀刻移除，造成图9中所示的中间结构。在此实施例中，新的栅极氧化物形成，而由于等离子体处理以移除多晶硅的假栅极或取代金属栅极的沉积，该新的栅极氧化物不会包含辐射损 害(radiation damage)。根据此实施例的态样，形成新的栅极介电质，其包括具有硅的高介电常数材料，该硅集中浓缩在与衬底之间的接口处及与金属栅极电极之间的接口处，因而形成与该衬底及该金属栅极两者相容的渐变栅极介电层，并因此，减少了应力及相关的缺陷。 
在移除原始的栅极氧化物12之后，形成渐变的高介电常数栅极氧化物。此实施例的态样包括沉积最初的多晶硅层81，显示于图10中，沉积高介电常数材料82(例如Ta2O5、Hf2O3或HfSiO3)于该多晶硅层81上，然后沉积另一多晶硅层83于该高介电常数材料82上。如图11中所示，然后沉积金属90。此实施例的态样包括沉积最初的钽层，接着沉积铜或铜合金层。 
然后实行CMP，造成图12中示意地显示的结构，该结构包括金属栅极电极100。含有硅浓缩在与衬底10之间的接口处及与金属栅极电极100之间的接口处的渐变的组成栅极介电层显著地减少了应力，并因此，减少了缺陷，因而使得泄漏电流没有增加而减小的EOT成为可能。 
本发明的实施例包括使用各种类型的非晶形碳，例如含氢的碳(例如，具有氢浓度约原子百分比5％至约原子百分比40％(典型为约原子百分比20％至约原子百分比30％)的非晶形氢化碳)。本发明的实施例亦包括非晶形氮化碳(amorphous carbon nitride)，有时称之为氮化碳(nitrogenated carbon)，通常具有氮对氢浓度比约5∶20至30∶0。亦可使用非晶形氢-氮化碳(amorphous hydrogen-nitrogenated carbon)。 
本发明提供能够制造具有金属栅极电极的晶体管及具有极薄的EOT的栅极氧化物的半导体器件，而防止泄漏电流产生的方法。本发明能够调整跨于在栅极氧化物层上的保护层的渐变轮廓(graded profile)的电压Vc。 
本发明享有制造各种类型的半导体器件的工业应用性。本发明特别应用在制造具有次微米特征的半导体器件及显现出高驱动电流与最小化的泄漏电流。 
在前面叙述中，提出了许多特定细节(例如特定的材料、结构、化学品、工艺等)以提供本发明的优选了解。然而，本发明不需依靠特定提出的细节亦能实施。在其他范例中，没有详细叙述熟知的处理及材 料是为了不必要的混淆本发明。 
在本申请案中仅显示及叙述本发明的优选实施例及一些其多用途的范例。应了解到，本发明能使用在各种其他的组合及环境中，并能在此所陈述的本发明概念的范畴内作改变或修改。 

Claims (12)

1.一种制造半导体器件的方法，包括：
形成栅极介电层；
在该栅极介电层之上形成可移除的栅极；
在该可移除的栅极之上形成介电层；
通过移除该可移除的栅极，在该介电层中形成开孔；
形成保护层，该保护层作为该开孔的衬里并覆盖该栅极介电层；
在该保护层之上该开孔内形成导电栅极；以及
自该导电栅极扩散金属至该保护层以在该栅极介电层与该导电栅极之间形成渐变的组成，其中，形成渐变的组成包括形成金属碳化物的渐变的组成，该金属碳化物的浓度从具有该导电栅极的接口至具有该栅极介电层的接口的方向降低。
2.如权利要求1所述的方法，其中，该可移除的栅极包括多晶硅。
3.如权利要求1所述的方法，其中，该形成该栅极介电层包括形成含有ZrO2、HfO2、Hf2O3、HfSiO3、InO2、LaO2、Ta2O3或TaO2中的至少一个的层。
4.如权利要求1所述的方法，其中，该形成该保护层包括形成含有非晶形碳、非晶形氢化碳、非晶形氮化碳或非晶形氢-氮化碳中的至少一个的层。
5.如权利要求4所述的方法，其中，该非晶形碳的层具有高达50埃的厚度。
6.如权利要求5所述的方法，其中，该非晶形碳的层还包括氧、硅或氮中的至少一种元素。
7.如权利要求1所述的方法，其中，该形成该导电栅极包括形成含有钽、镍、钴、钼、铜或铜合金中的至少一个的至少一层。
8.一种制造半导体器件的方法，包括：
在栅极介电层之上形成可移除的栅极；
在该可移除的栅极之上形成介电层；
通过移除该可移除的栅极，在该介电层中形成开孔；
移除该栅极介电层；
沉积第一多晶硅层；
在该第一多晶硅层之上沉积氧化物层；
在该氧化物层上沉积第二多晶硅层；以及
在该第二多晶硅层之上的该开孔内形成导电栅极。
9.如权利要求8所述的方法，其中，该氧化物层包括具有4至30之范围中的介电常数的材料。
10.如权利要求8所述的方法，其中，该氧化物层包括ZrO2、HfO2、Hf2O3、HfSiO3、InO2、LaO2、Ta2O3或TaO2中的至少一个。
11.如权利要求8所述的方法，其中，该可移除的栅极包括多晶硅。
12.如权利要求8所述的方法，其中，该形成该导电栅极包括形成含有钽、镍、钴、钼、铜或铜合金中的至少一个的至少一层。
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