CN101814315B - Static random access memory capable of increasing write surplus capacity - Google Patents
Static random access memory capable of increasing write surplus capacity Download PDFInfo
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- CN101814315B CN101814315B CN201010163847.3A CN201010163847A CN101814315B CN 101814315 B CN101814315 B CN 101814315B CN 201010163847 A CN201010163847 A CN 201010163847A CN 101814315 B CN101814315 B CN 101814315B
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Abstract
The invention provides a static random access memory capable of increasing write surplus capacity, at least comprising a static random access memory cell array which includes a plurality of static random access memory cells arranged in array form as well as a controllable power supply circuit which is connected with the static random access memory cell array and is used for providing controllable voltage for each static random access memory cell. Under the reading and hold-on mode, power supply voltage and power supply negative terminal voltage of each line of the static random access memory cell array are constant, when executing write operation, the power supply voltage of the line in which the operated static random access memory cell is located is reduced or the power supply negative terminal voltage of the line in which the operated static random access memory cell is located is improved, voltages in other lines are not changed, thus the acceptable low lever range of the static random access memory cell of the invention is widened and the write capacity of the static random access memory of the invention is increased.
Description
Technical field
The present invention about a kind of semiconductor memory devices, particularly about a kind of static RAM that can increase write surplus capacity.
Background technology
Threshold voltage vt is the important electrical quantity of of MOS transistor, is also important controling parameters in a manufacturing process.The size of Vt and the performance of consistance on circuit and even integrated system have conclusive impact.The mathematic(al) representation of threshold voltage is:
Vt＝Ψms-Qox/Cox+Qb/Cox+2Ψb
In formula, Qox is fixed positive charge density in gate oxide; Cox is unit area gate oxide capacitance, is inversely proportional to gate oxide thickness tox; Qb is substrate impurity concentration (in depletion layer electric charge), and NMOS tube adopts P-type silicon to be substrate, and this value is negative, and PMOS adopts N-type silicon to be substrate, and this value is just; Ψ b is the Fermi potential of semiconductor, and NMOS tube adopts P-type silicon to be substrate, and this value is negative, and PMOS adopts N-type silicon to be substrate, and this value is just; Ψ ms is metal semiconductor work function difference, and aluminum gate process is-0.3v, and silicon gate technology is+0.8v.
First factor affecting threshold voltage is the character as the charge Q ox in the silicon dioxide (gate oxide) of medium and electric charge.This electric charge is normally produced by many reasons, a part of positively charged wherein, and a part is electronegative, the polarity of its net charge obviously can produce electric charge induction to substrate surface, thus affect the formation of inversion layer, or device is exhausted, or hinder the formation of inversion layer.Qox is generally movable positive charge.
Second factor affecting threshold voltage is the doping content Qb of substrate.Usually, will produce inversion layer at the upper surface of substrate, must apply surface depletion can be formed the gate source voltage of the accumulation of substrate minority carrier, the size of this voltage and the doping content of substrate have direct relation.Substrate doping (Qb) is lower, and the concentration of majority carrier is also lower, substrate surface is exhausted with the voltage Vgs required for transoid less.So substrate doping is an important parameter, and substrate doping is lower, the threshold voltage numerical value of device will be less, otherwise then threshold voltage value is higher.For a mature and stable technique and basic device structure, the adjustment of device threshold voltage, mainly through changing substrate doping or substrate surface doping content is carried out.The adjustment of substrate surface doping content is undertaken by ion implanted impurity ion.
3rd factor affecting threshold voltage is the size of the unit area gate capacitance Cox determined by gate oxide thickness tox.The relation of unit area gate capacitance and gate oxide thickness tox is determined by following formula: Cox=ε/tox
In formula, ε is the specific inductive capacity of silicon dioxide gate oxide, and tox is the thickness of silicon dioxide gate oxide.Obviously, unit area gate capacitance is larger, and amount of charge change is more responsive to the change of vgs, and the threshold voltage of device is then less.
Fig. 1 and Fig. 2 is respectively a kind of structural drawing of six traditional transistor static Random Access Storage Units and comprises the structural drawing of static RAM of six transistor static Random Access Storage Unit arrays.Tradition six transistor static Random Access Storage Unit in Fig. 1 comprises PMOS transistor P1 and P2, and nmos pass transistor N1, N2, N3 and N4.The drain electrode lotus root of PMOS transistor P2 is connected to the drain electrode of nmos pass transistor N2, the drain electrode lotus root of PMOS transistor P1 is connected to the drain electrode of nmos pass transistor N1, the source electrode lotus root of nmos pass transistor N2 and N1 is connected to a complementary electrical potential source, as ground connection or Vss, the grid of PMOS transistor P2 and the grid lotus root of nmos pass transistor N2 are connected to a storage node V1, storage node V1 also lotus root is connected to the drain electrode of PMOS transistor P1 and nmos pass transistor N1, the grid of PMOS transistor P1 and the grid lotus root of nmos pass transistor N1 are connected to a storage node V2, this storage node V2 also lotus root is connected to the drain electrode of PMOS transistor P2 and nmos pass transistor N2, nmos pass transistor N3 lotus root meets storage node V1 to bit line BL, nmos pass transistor N4 lotus root meets storage node V2 to paratope line/BL, the grid of nmos pass transistor N3 and N4 is all controlled by a wordline WL, the source electrode of PMOS transistor P1 and P2 is connected to supply voltage Vdd.Fig. 2 is the structural drawing of the static RAM comprising traditional six crystal shunt Random Access Storage Unit arrays.There is shown the static RAM comprising nine static random access memory (sram) cells, wherein, these nine static random access memory (sram) cells are powered by supply voltage Vdd, WL0, WL1 and WL2 are wordline, BL0, BL1 and BL2 are bit line, static random access memory (sram) cell A, B and C shared bit line BL1, static random access memory (sram) cell D, A and E common word line WL1.
Although all can correct threshold voltage vt by various method during Production of Transistor, but along with the development of semiconductor technology, the size of six transistor static Random Access Storage Units is also more and more less, and change is increasing relatively to affect the parameter Qb of threshold voltage vt, Qox, tox etc., therefore the relative Repeat that transistor thresholds voltage Vt fluctuates just adds; On the other hand, for reducing power consumption, all integrated circuit comprise the supply voltage Vdd that six transistor static Random Access Storage Units use to be reduced further with process modification, the reduction of supply voltage Vdd then makes the noise margin of digital circuit reduce simultaneously, and namely low and high level difference voltage reduces.These changes make the write surplus capacity of static random access memory (sram) cell compare to be difficult to ensure card, therefore the write surplus capacity increasing static random access memory (sram) cell is very useful and be necessary.
In sum, there is the problem that cannot ensure write surplus capacity in the static random access memory (sram) cell of known prior art, and therefore the real technological means being necessary to propose to improve, solves this problem.
Summary of the invention
Write surplus capacity shortcoming cannot be ensured for the static random access memory (sram) cell overcoming above-mentioned prior art exists, fundamental purpose of the present invention is to provide a kind of static RAM, it provides controlled supply voltage or power supply negative terminal voltage by controllable power supply circuit, can reach the object of the write surplus capacity increasing static random access memory (sram) cell.
For reaching above-mentioned and other object, a kind of static RAM increasing write surplus capacity of the present invention,
Static random access memory (sram) cell array, this static random access memory (sram) cell array comprises multiple static random access memory (sram) cell arranged in the form of an array; And
Controllable power supply circuit, is connected to this static random access memory (sram) cell array, provides controlled voltage for giving each static random access memory (sram) cell.
Further, this static random access memory (sram) cell comprises the first PMOS transistor, second PMOS transistor, first nmos pass transistor, second nmos pass transistor, 3rd nmos pass transistor and the 4th nmos pass transistor, this first nmos pass transistor and this first PMOS transistor and this second nmos pass transistor and this second PMOS transistor form reverser respectively, 3rd nmos pass transistor is connected with bit line and paratope line respectively with the source electrode of the 4th nmos pass transistor, 3rd nmos pass transistor is connected a wordline with the grid of the 4th nmos pass transistor, the source electrode of this first nmos pass transistor and this second nmos pass transistor is connected to a power supply negative terminal, the grid of this first PMOS transistor and this second PMOS transistor is connected to this controllable power supply circuit, there is provided controlled supply voltage to this static random access memory (sram) cell by this controllable power supply circuit.
Further, when needs carry out write operation, this controllable power supply circuit makes to be reduced by the supply voltage of the static random access memory (sram) cell column operated, and the supply voltage of other row is constant.
Further, it is characterized in that, at reading and Holdover mode, the supply voltage often arranged is constant.
In addition, this static random access memory (sram) cell can comprise the first PMOS transistor, second PMOS transistor, first nmos pass transistor, second nmos pass transistor, 3rd nmos pass transistor and the 4th nmos pass transistor, this first nmos pass transistor and this first PMOS transistor and this second nmos pass transistor and this second PMOS transistor form reverser respectively, 3rd nmos pass transistor is connected with bit line and paratope line respectively with the source electrode of the 4th nmos pass transistor, 3rd nmos pass transistor is connected a wordline with the grid of the 4th nmos pass transistor, the grid of this first PMOS transistor and this second PMOS transistor is connected to a power positive end, the source electrode of this first nmos pass transistor and this second nmos pass transistor is connected to this controllable power supply circuit, there is provided controlled power supply negative terminal voltage to this static random access memory (sram) cell by this controllable power supply circuit.
Further, when needs carry out write operation, this controllable power supply circuit makes to be improved by this power supply negative terminal voltage of the static random access memory (sram) cell column operated, and the power supply negative terminal voltage of other row is constant.
Further, at reading and Holdover mode, the power supply negative terminal voltage often arranged is constant.
Compared with prior art, a kind of static RAM increasing write surplus capacity of the present invention provides controlled voltage by utilizing controllable power supply circuit to the power positive end of its static random access memory (sram) cell array or power supply negative terminal, make it under reading and Holdover mode, often row supply voltage or power supply negative terminal voltage constant, and when needs carry out write operation, make reduced by the supply voltage of the static random access memory (sram) cell column operated or make to be improved by the power supply negative terminal voltage of the static random access memory (sram) cell column operated, and the voltage of other row is constant, the acceptable low and high level scope of static random access memory (sram) cell is expanded, thereby increase the write surplus capacity of static RAM of the present invention.
Accompanying drawing explanation
Fig. 1 is the circuit structure diagram of a kind of six transistor static Random Access Storage Units of prior art;
Fig. 2 is the structural representation that prior art comprises the static RAM of six transistor static Random Access Storage Unit arrays;
Fig. 3 is the structural representation that the present invention comprises static RAM first preferred embodiment of the increased write surplus capacity of static random access memory (sram) cell array.
Fig. 4 is the circuit structure diagram of a static random access memory (sram) cell in Fig. 3;
Fig. 5 is the structural representation that the present invention comprises static RAM second preferred embodiment of the increased write surplus capacity of static random access memory (sram) cell array.
Fig. 6 is the circuit structure diagram of a static random access memory (sram) cell in Fig. 5;
Fig. 7 is the simulation waveform of prior art static RAM;
Fig. 8 is the simulation waveform that the present invention can increase static RAM second preferred embodiment of write surplus capacity.
Embodiment
Below by way of specific instantiation and accompanying drawings embodiments of the present invention, those skilled in the art can understand other advantage of the present invention and effect easily by content disclosed in the present specification.The present invention is also implemented by other different instantiation or is applied, and the every details in this instructions also can based on different viewpoints and application, carries out various modification and change not deviating under spirit of the present invention.
Please also refer to Fig. 3 and Fig. 4, Fig. 3 is the structural representation that the present invention comprises static RAM first preferred embodiment of the increased write surplus capacity of static random access memory (sram) cell array, and Fig. 4 is the circuit structure diagram of static random access memory (sram) cell A in Fig. 3.As shown in the figure, a kind of static RAM 100 increasing write surplus capacity of the present invention comprises static random access memory (sram) cell array 101 and controllable power supply circuit 102, static random access memory (sram) cell array 101 comprises multiple static random access memory (sram) cell (as static random access memory (sram) cell A, B, C, D and E) arranged in the form of an array, and wherein the power end of each static random access memory (sram) cell is all connected to controllable power supply circuit 102; Controllable power supply circuit 102 is powered for giving static random access memory (sram) cell array 101, provides controlled supply voltage (as Vdd0, Vdd1 and Vdd2 in figure).Static RAM 100 of the present invention is at reading and Holdover mode, and the supply voltage often arranged is constant; When needs carry out write operation, make to be reduced by the supply voltage of the unit column operated, the supply voltage of other row is constant.
Please also refer to Fig. 4, a kind of static random access memory (sram) cell A increased in the static RAM of write surplus capacity of the present invention is the storage architecture of a data, temporarily can keep these data of, and in the time after a while, according to the execution instruction required by central processing unit, data are sent to computing environment.Specifically, static random access memory (sram) cell A comprises six transistors, be respectively the first PMOS transistor P1, second PMOS transistor P2, first nmos pass transistor N1, second nmos pass transistor N2, 3rd nmos pass transistor N3 and the 4th nmos pass transistor N4, it is an a kind of storage unit of six transistor architecture, wherein the first nmos pass transistor N1 and the first PMOS transistor P1, second nmos pass transistor N2 and the second PMOS transistor P2 forms CMOS reverser respectively, first nmos pass transistor N1, the grid of the first PMOS transistor P1 and the second PMOS transistor P2, the drain electrode of the second nmos pass transistor N2 connects, form the second storage node X2, second PMOS transistor P2, the grid of the second nmos pass transistor N2 and the first nmos pass transistor N1, the drain electrode of the first PMOS transistor P1 connects, form the first storage node X1, 3rd nmos pass transistor N3 is connected wordline WL with the grid of the 4th nmos pass transistor, via the first nmos pass transistor N1, second nmos pass transistor N2 and and read between bit line (bit line BL and paratope line BLb), the transmission of write data, the drain electrode of the 3rd nmos pass transistor N3 and the 4th nmos pass transistor N4 is connected to the first storage node X1 and the second storage node X2 respectively, the source electrode of the first nmos pass transistor N1 and the second nmos pass transistor connects power supply negative terminal (Vss), the source electrode of the first PMOS transistor P1 and the second PMOS transistor P2 is connected to a controllable power supply circuit 102, this controllable power supply circuit provides supply voltage Vdd1 for static RAM A.
Fig. 3 please be refer again to, specifically, suppose to need the static random access memory (sram) cell A to static RAM of the present invention to carry out write operation, static access memory cell B, C, D, E is adjacent cells, wherein static random access memory (sram) cell D, E and static random access memory (sram) cell A common word line WL1, but (bit line of static random storing storage units D is bit line BL0 to its and bit line different from static random access memory (sram) cell A power supply used, the bit line of static random access memory (sram) cell E is bit line BL2) not selected, therefore static random access memory (sram) cell D, E is in hold mode, although and static random access memory (sram) cell B, C and static random access memory (sram) cell A shared bit line BL1 and power supply Vdd1, but (wordline of static random access memory (sram) cell B is wordline WL0 to wordline, the wordline of static random access memory (sram) cell C is wordline WL2) different, therefore static random access memory (sram) cell B, C are also in hold mode.
Please with reference to Fig. 4, because static random access memory (sram) cell A is symmetrical, the process therefore writing " 1 " or " 0 " is identical.Without loss of generality, if the original state of static random access memory (sram) cell A is the first storage node X1 is high level " 1 ", second storage node X2 is low level " 0 ", first PMOS P1 and the second NMOS tube N2 conducting, second PMOS P2 and the first NMOS tube N1 ends, when needs write " 0 " in nodes X 1, the decoding logic circuit of system is opened write-enable and is chosen static random access memory (sram) cell A, after bit line BL precharge, wordline WL sets high level, be opened as the 3rd NMOS tube N3 of read-write control circuit and the 4th NMOS tube N4, arranging bit line BL is low level " 0 ", paratope line BLb is high level " 1 ", reduce the supply voltage of static random access memory (sram) cell A to Vdd1-Δ Vdd1 simultaneously, because bit line BL is low level, first PMOS P1, nodes X 1, NMOS tube N3 forms a bleeder circuit, because supply voltage has been reduced to Vdd1-Δ Vdd1, therefore the voltage of the first storage node X1 is also reduced for V1-Δ V1, and the first storage node X1 is connected to the grid of the second PMOS P2 and the second NMOS tube N2, this grid voltage reduction can cause that the second PMOS P2 progresses into conducting state and the second NMOS tube N2 exits conducting state gradually, second PMOS P2 progresses into conducting state and the second NMOS tube N2 and exits conducting state gradually and can cause its drain voltage, namely the second storage node X2 voltage raises gradually, and the second storage node X2 is connected to the grid of the first PMOS P1 and the first NMOS tube N1, therefore the grid voltage of the first PMOS P1 and the first NMOS tube N1 can raise, this just cause the first PMOS P1 progress into cut-off and the first NMOS tube N1 progresses into conducting, first PMOS P1 progresses into cut-off and the first NMOS tube N1 progresses into conducting and can make its drain voltage, namely the first storage node X1 voltage declines sooner, so positive feedback makes the first storage node X1 and the second storage node X2 voltage turn rapidly repeatedly, namely the first storage node X1 is written into low level " 0 ", and the second storage node X2 is written into high level " 1 ".Because write moment, supply voltage decline Δ Vdd1 causes the first storage node X1 voltage drop Δ V1, this makes the state of static ram cell A turn acceleration, change an angle to consider, keep turning speed constant, then can increase bit line BL low-voltage to be expanded to the acceptable low level scope of VBL+ Δ VBL, static random access memory (sram) cell A, that is write surplus capacity adds.
If original state for " 0 " and need write high level " 1 " time, then the second storage node X2 initial voltage is high level " 1 ", and paratope line BLb is low level " 0 ", reducing supply voltage makes the second storage node X2 reduce, because static ram cell A is symmetrical, therefore its process be same as completely above-mentioned original state for " 1 " and need write high level " 0 " situation, do not repeat them here.
For original state for " 0 " and need write high level " 0 ", and original state for " 1 " and need write high level " 1 " situation, because all crystals tubulose state does not change, then more simpler, also will not describe in detail at this.
As the present invention second preferred embodiment, Fig. 5 is the structural representation that the present invention comprises static RAM second preferred embodiment of the increased write surplus capacity of static random access memory (sram) cell array, and Fig. 6 is the circuit structure diagram of static random access memory (sram) cell A in Fig. 5.Be different from the present invention first preferred embodiment to use and reduce supply voltage Vdd to increase write surplus capacity, the present invention second preferred embodiment mainly increases write surplus capacity by improving power supply negative terminal voltage Vss.The power supply negative terminal voltage of the row of all static memories is controlled by controllable power supply circuit 102, and only need the power supply negative terminal voltage of unit as static random access memory (sram) cell A column of accessing to be enhanced, the power supply negative terminal voltage of other row is constant.
With reference to figure 5, without loss of generality, suppose to need the static random access memory (sram) cell A of the static RAM to the present invention second preferred embodiment to carry out write operation, static access memory cell B, C, D, E is adjacent cells, wherein static random access memory (sram) cell D, E and static random access memory (sram) cell A common word line WL1, but (bit line of static random storing storage units D is bit line BL0 to its and bit line different from static random access memory (sram) cell A power supply used negative terminal, the bit line of static random access memory (sram) cell E is bit line BL2) not selected, therefore static random access memory (sram) cell D, E is in hold mode, although and static random access memory (sram) cell B, C and static random access memory (sram) cell A shared bit line BL1 and power supply negative terminal Vss1, but (wordline of static random access memory (sram) cell B is wordline WL0 to wordline, the wordline of static random access memory (sram) cell C is wordline WL2) different, therefore static random access memory (sram) cell B, C are also in hold mode.
With reference to figure 6, without loss of generality, suppose that the first memory node X1 initial voltage is high level " 1 ", currently to write low level " 0 ", original state PMOS transistor P1 and nmos pass transistor N2 conducting, when write starts, bit line BL sets low level, paratope line BLb sets high level, and wordline WL sets high level, and nmos pass transistor N3 and N4 opens, boost source negative terminal voltage Vss1, because nmos pass transistor N2 saturation conduction, therefore its drain voltage i.e. voltage rise of the second memory node X2, PMOS transistor P1 grid voltage rises, this makes PMOS transistor P1 conducting die down, its drain voltage i.e. the first memory node X1 voltage step-down, because the first memory node X1 is connected to the grid of PMOS transistor P2 and nmos pass transistor N2, therefore PMOS transistor P2 progresses into conducting and nmos pass transistor N2 progresses into cut-off, the two drain voltage i.e. voltage of the second memory node X2 rises further, first memory node X1 voltage is turned rapidly as low level " 0 " in positive feedback like this and the second memory node X2 voltage turns rapidly as low level " 1 ".
Current to write " 1 " for original state for " 0 ", be initially " 0 " and current will write " 0 " to be initially " 1 " and the current situation that will write " 1 ", the second preferred embodiment shown in Fig. 5-6 and Fig. 3-4 shownschematically the first preferred embodiment are identical, do not repeat them here.
Fig. 7 is the simulation waveform of static RAM in prior art, and Fig. 8 is the simulation waveform that the present invention can increase static RAM second preferred embodiment of write surplus capacity.Abscissa representing time time (ns) in figure, ordinate represents voltage Voltage (v).Fig. 7 and Fig. 8 all shows the first memory node X1 and is initially " 0 " and the current situation that will write " 1 ", wordline WL is always high level, paratope line BLb is changed to low level by high level, first memory node X1 voltage is changed to high level by low level, second memory node X2 voltage is changed to low level by high level with paratope line BLb, make the vertical line perpendicular to time shaft by two storage node voltage intersections, the intersection point of this vertical line and bit line BLb corresponds to write surplus capacity.The present invention of comparison diagram 8 can increase the simulation waveform of static RAM second preferred embodiment of write surplus capacity and the simulation waveform of the prior art of Fig. 7, the write surplus capacity that visible the present invention can increase the static RAM of write surplus capacity is about 300mV (power supply negative terminal voltage is increased to 0.2V), and prior art only 200mV, visible, the write surplus capacity of static RAM of the present invention obviously increases.
By above-mentioned analysis, visible, the present invention utilizes a controllable power supply circuit to the static random access memory (sram) cell powering arrays of static RAM, reading and Holdover mode, make the supply voltage of often row static random access memory (sram) cell constant, and when needs carry out write operation, make to be reduced by the supply voltage of the static random access memory (sram) cell column operated, the supply voltage of other row is constant, the acceptable low level scope of static RAM of the present invention is expanded, add the write surplus capacity of static RAM.
Above-described embodiment is illustrative principle of the present invention and effect thereof only, but not for limiting the present invention.Any those skilled in the art all without prejudice under spirit of the present invention and category, can carry out modifying to above-described embodiment and change.Therefore, the scope of the present invention, should listed by claims.
Claims (3)
1. can increase a static RAM for write surplus capacity, at least comprise:
Static random access memory (sram) cell array, this static random access memory (sram) cell array comprises multiple static random access memory (sram) cell arranged in the form of an array; And
Controllable power supply circuit, is connected to this static random access memory (sram) cell array, provides controlled voltage for giving each static random access memory (sram) cell;
This static random access memory (sram) cell comprises the first PMOS transistor, second PMOS transistor, first nmos pass transistor, second nmos pass transistor, 3rd nmos pass transistor and the 4th nmos pass transistor, this first nmos pass transistor and this first PMOS transistor and this second nmos pass transistor and this second PMOS transistor form reverser respectively, 3rd nmos pass transistor is connected with bit line and paratope line respectively with the source electrode of the 4th nmos pass transistor, 3rd nmos pass transistor is connected a wordline with the grid of the 4th nmos pass transistor, the grid of this first PMOS transistor and this second PMOS transistor is connected to a power positive end, the source electrode of this first nmos pass transistor and this second nmos pass transistor is connected to this controllable power supply circuit, there is provided controlled power supply negative terminal voltage to this static random access memory (sram) cell by this controllable power supply circuit.
2. can increase the static RAM of write surplus capacity as claimed in claim 1, it is characterized in that, when needs carry out write operation, this controllable power supply circuit makes to be improved by this power supply negative terminal voltage of the static random access memory (sram) cell column operated, and the power supply negative terminal voltage of other row is constant.
3. can increase the static RAM of write surplus capacity as claimed in claim 2, it is characterized in that, at reading and Holdover mode, the power supply negative terminal voltage often arranged is constant.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1193846A (en) * | 1997-03-19 | 1998-09-23 | 三菱电机株式会社 | Semiconductor integrated circuits |
| CN1870175A (en) * | 2005-05-23 | 2006-11-29 | 株式会社瑞萨科技 | Semiconductor memory device |
| CN1975926A (en) * | 2005-11-29 | 2007-06-06 | 国际商业机器公司 | SRAM and SRAM voltage control method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1193846A (en) * | 1997-03-19 | 1998-09-23 | 三菱电机株式会社 | Semiconductor integrated circuits |
| CN1870175A (en) * | 2005-05-23 | 2006-11-29 | 株式会社瑞萨科技 | Semiconductor memory device |
| CN1975926A (en) * | 2005-11-29 | 2007-06-06 | 国际商业机器公司 | SRAM and SRAM voltage control method |
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