CN101795070A - System for linearly adjusting slope compensation voltage slope - Google Patents
System for linearly adjusting slope compensation voltage slope Download PDFInfo
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- CN101795070A CN101795070A CN 201010143890 CN201010143890A CN101795070A CN 101795070 A CN101795070 A CN 101795070A CN 201010143890 CN201010143890 CN 201010143890 CN 201010143890 A CN201010143890 A CN 201010143890A CN 101795070 A CN101795070 A CN 101795070A
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Abstract
The invention discloses a system for linearly adjusting the slope compensation voltage slope. With a duty factor detection circuit, a voltage and current conversion circuit and a slope generation circuit, a duty factor of a switch signal in a peak current control mode chip is converted into a voltage signal forming a linear relationship with the duty factor by using the duty factor detection circuit, the voltage signal is linearly converted into a first current signal by using the voltage and current conversion circuit, and a second current signal formed by superposing the first current signal and a reference current source passes through the slope generation circuit to obtain slope compensation voltage, so that the invention achieves the function of linearly adjusting the slope of the slope compensation voltage according to the duty factor of the switch signal in the peak current control mode chip, well solves the problems that the peak current control mode chip is easy to generate over compensation during low duty factor and generate under compensation during high duty factor and ensures that the chip has favorable loading capacity and load regulating capacity in the work range of all duty factors.
Description
Technical field
The present invention relates to the slope compensation technology in a kind of peak current control model chip, especially relate to a kind of system of linearly adjusting slope compensation voltage slope.
Background technology
Peak current control model (PCM, Peak Current Model) be one of most widely used control mode of field of switch power, its major advantage is embodied in: (1) is because output load current is proportional to inductive current, PCM has realized switch periods inner control output current one by one, adjusts characteristic and anti-input electric source disturbance ability thereby have more superior load; (2) have the instantaneous peak current current-limiting function, can not damage, significantly reduced the protection of overload and short circuit because of overcurrent makes switching tube; (3) whole feedback circuit has become a firstorder circuit, so the control ring compensating network of error amplifier simplified, and stability is improved and can improves the stability of frequency response loop, easily compensation; (4) output voltage ripple is less.But, because output load current is directly proportional with inductive current mean value among the PCM, rather than be directly proportional with inductive current peak, and there is difference between inductive current mean value and the inductive current peak, when the switching signal duty ratio of switch power supply system exists the inductive current peak that is difficult to proofread and correct and the error of inductive current mean value, switch power supply system open-loop unstable greater than 50% the time.In order to remedy this shortcoming, common way is at the ramp signal of a positive slope of stack on the current sampling signal or in the ramp signal of a negative slope of the output of the error amplifier stack error between compensating inductance current peak and the inductive current mean value in addition, the switching signal duty ratio that makes switch power supply system is greater than maintained switch power-supply system loop stability under 50% the situation.Yet the slope of traditional slope compensation voltage is a fixed value, is easy to generate overcompensation and undercompensation, if the slope compensation voltage slope is too big, overcompensation takes place easily when big duty ratio, thereby will reduce the load capacity of switch power supply system; If the slope compensation voltage slope is too little, undercompensation then easily takes place when less duty ratio, thereby will reduce switch power supply system stability and load regulation ability.
Summary of the invention
Technical problem to be solved by this invention provides a kind of simple and practical, can be according to the slope of the linear adjusting slope compensation voltage of the size of the duty ratio of the switching signal in the peak current control model chip, and can not produce the system of overcompensation or undercompensation problem.
The present invention solves the problems of the technologies described above the technical scheme that is adopted: a kind of system of linearly adjusting slope compensation voltage slope, comprise duty detection circuit, voltage-current converter circuit, slope generating circuit and reference current source, described duty detection circuit is converted to the switching signal of input and the linear voltage signal of described switching signal, and described voltage signal is transferred to described voltage-current converter circuit, described voltage-current converter circuit is also exported first current signal that converts to of described voltage signal linearity, described first current signal and the superimposed formation of described reference current source input to second current signal of described slope generating circuit, described slope generating circuit output slope compensation voltage, the duty ratio of described slope compensation voltage and described switching signal is linear.
Described duty detection circuit is mainly by inverter, first nmos pass transistor, second nmos pass transistor, first resistance and first electric capacity are formed, the input of described inverter inserts described switching signal, the output of described inverter is connected with the grid of described first nmos pass transistor and the grid of described second nmos pass transistor respectively, the drain electrode of described first nmos pass transistor inserts reference voltage, the source electrode of described first nmos pass transistor is connected with first end of described first resistance, the drain electrode of described second nmos pass transistor is connected with first end of described first resistance, the source ground of described second nmos pass transistor, described first electric capacity is connected between the source electrode of second end of described first resistance and described second nmos pass transistor, output of the public connecting end of described first resistance and described first electric capacity and the linear voltage signal of described switching signal.
Described voltage-current converter circuit is mainly by low pressure difference linear voltage regulator, second resistance and first current mirror are formed, described low pressure difference linear voltage regulator comprises operational amplifier and the 3rd nmos pass transistor, described first current mirror comprises the 4th PMOS transistor and the 5th PMOS transistor, the positive input terminal of described operational amplifier inserts described voltage signal, the output of described operational amplifier is connected with the grid of described the 3rd nmos pass transistor, the source electrode of described the 3rd nmos pass transistor is connected with the negative input end of described operational amplifier, the source electrode of described the 3rd nmos pass transistor is connected with first end of described second resistance with the public connecting end of the negative input end of described operational amplifier, the second end ground connection of described second resistance, the drain electrode of described the 3rd nmos pass transistor respectively with the transistorized source electrode of described the 4th PMOS, transistorized grid of described the 4th PMOS and the transistorized grid of described the 5th PMOS are connected, described the 4th PMOS transistor drain and described the 5th PMOS transistor drain connect power supply respectively, and the transistorized source electrode of described the 5th PMOS is exported described first current signal.
Described slope generating circuit is mainly by second current mirror, the 3rd current mirror, the tenth PMOS transistor, the 11 nmos pass transistor and second electric capacity are formed, described second current mirror comprises the 6th nmos pass transistor and the 7th nmos pass transistor, described the 3rd current mirror comprises the 8th PMOS transistor and the 9th PMOS transistor, the drain electrode of described the 6th nmos pass transistor inserts described first current signal, the drain electrode of described the 6th nmos pass transistor respectively with the negative pole end of described reference current source, the grid of the grid of described the 6th nmos pass transistor and described the 7th nmos pass transistor is connected, the source electrode of the source electrode of described the 6th nmos pass transistor and described the 7th nmos pass transistor is ground connection respectively, the drain electrode of described the 7th nmos pass transistor respectively with the transistorized source electrode of described the 8th PMOS, transistorized grid of described the 8th PMOS and the transistorized grid of described the 9th PMOS are connected, the positive terminal of described reference current source, described the 8th PMOS transistor drain and described the 9th PMOS transistor drain connect power supply respectively, the transistorized source electrode of described the 9th PMOS is connected with described the tenth PMOS transistor drain, the grid of transistorized grid of described the tenth PMOS and described the 11 nmos pass transistor inserts the clock signal in the charging interval that is used to control described second electric capacity respectively, the transistorized source electrode of described the tenth PMOS is connected with the drain electrode of described the 11 nmos pass transistor, the source ground of described the 11 nmos pass transistor, described second electric capacity is connected between the source electrode of the public connecting end of drain electrode of transistorized source electrode of described the tenth PMOS and described the 11 nmos pass transistor and described the 11 nmos pass transistor, the transistorized source electrode of described the tenth PMOS, the public connecting end of the drain electrode of described the 11 nmos pass transistor and described second electric capacity is exported described slope compensation voltage.
Compared with prior art, the invention has the advantages that by duty detection circuit is set, voltage-current converter circuit and slope generating circuit, utilize duty detection circuit with the duty cycle conversion of the switching signal in the peak current control model chip be one with the linear voltage signal of the duty ratio of switching signal, voltage-current converter circuit is then first current signal that converts to of this voltage signal linearity, second current signal that first current signal and reference current source stack back form obtains slope compensation voltage behind slope generating circuit, having realized can be according to the function of the slope of the linear adjusting slope compensation voltage of the size of the duty ratio of the switching signal in the peak current control model chip, solved well overcompensation has easily taken place when low duty ratio in the peak current control model chip, under-compensated problem easily takes place when high duty ratio, makes peak current control model chip all have good load capacity and load adjustment capability in all duty ratio working ranges.
Description of drawings
Fig. 1 is the logic diagram of system of the present invention;
Fig. 2 is a duty detection circuit schematic diagram of the present invention;
Fig. 3 is a voltage-current converter circuit schematic diagram of the present invention;
Fig. 4 is the connecting circuit schematic diagram of slope generating circuit of the present invention and reference current source;
Fig. 5 is the integrated circuit schematic diagram of system of the present invention;
Fig. 6 is the equivalent circuit theory figure of duty detection circuit among the present invention.
Embodiment
Embodiment describes in further detail the present invention below in conjunction with accompanying drawing.
As shown in the figure, a kind of system of linearly adjusting slope compensation voltage slope, comprise duty detection circuit 1, voltage-current converter circuit 2, slope generating circuit 3 and reference current source IB, duty detection circuit 1 is converted to the voltage signal Vc linear with switching signal V1 with the switching signal V1 of input, and voltage signal Vc is transferred to voltage-current converter circuit 2, voltage-current converter circuit 2 is also exported the first current signal Ic that converts to of voltage signal Vc linearity, the first current signal Ic and the superimposed formation of reference current source IB input to the second current signal Ic2 of slope generating circuit 3, slope generating circuit 3 obtains slope compensation voltage Vramp after the second current signal Ic2 is to its charging, the duty ratio of slope compensation voltage Vramp and switching signal V1 is linear.
In this specific embodiment, duty detection circuit 1 is mainly by inverter U1, the first nmos pass transistor M1, the second nmos pass transistor M2, first resistance R 1 and first capacitor C 1 are formed, the input of inverter U1 inserts switching signal V1, at this switching signal V1 is that one-period is T, duty ratio is the square-wave signal of D, the output of inverter U1 is connected with the grid of the first nmos pass transistor M1 and the grid of the second nmos pass transistor M2 respectively, the drain electrode of the first nmos pass transistor M1 inserts reference voltage V 2, in this reference voltage V 2 is constant, in the different peak current control model chips, the adjustable size of V2 saves the required slope compensation voltage of this chip.The source electrode of the first nmos pass transistor M1 is connected with first end of first resistance R 1, the drain electrode of the second nmos pass transistor M2 is connected with first end of first resistance R 1, the source ground of the second nmos pass transistor M2, first capacitor C 1 is connected between the source electrode of second end of first resistance R 1 and the second nmos pass transistor M2, output of the public connecting end of first resistance R 1 and first capacitor C 1 and the linear voltage signal Vc of switching signal V1.
When switching signal V1 in n cycle, and nT≤t≤n is (during T+T * D), promptly when switching signal V1 is high level, the first nmos pass transistor M1 conducting, and the second nmos pass transistor M2 closes, and the current potential V3 of the public connecting end of the drain electrode of the source electrode of the first nmos pass transistor M1 and the second nmos pass transistor M2 equals reference voltage V 2 at this moment.When switching signal V1 in n cycle, and n is (during the T of T+T * D)≤t≤(n+1), promptly when switching signal V1 is low level, the first nmos pass transistor M1 closes, and the second nmos pass transistor M2 conducting, the current potential V3 of the public connecting end of the drain electrode of the source electrode of the first nmos pass transistor M1 and the second nmos pass transistor M2 equals 0V at this moment, can learn that the current potential V3 of public connecting end of drain electrode of the source electrode of the first nmos pass transistor M1 and the second nmos pass transistor M2 and switching signal V1 are fully synchronously and the maximum level of current potential V3 is constant is reference voltage V 2, be current potential V3 be one with switching signal V1 on time domain synchronously and high level be that constant is the square-wave signal of V2, this moment, duty detection circuit 1 can equivalence be that a square-wave signal V3 and first resistance R 1 and first capacitor C 1 can constitute a RC loop, as shown in Figure 6, when the capacitance of the resistance of first resistance R 1 and first capacitor C 1 is enough big, first capacitor C 1 can be approximated to be direct voltage Vc with the voltage of the end that first resistance R 1 is connected, with this direct voltage Vc as the voltage signal Vc that inputs to voltage-current converter circuit 2, the duty ratio D of this voltage signal Vc and switching signal V1 is linear, promptly there is Vc=V2 * D, and all irrelevant with amplitude and the frequency of switching signal V1.Make a concrete analysis of as follows: make U
C1(t) be instantaneous voltage on first capacitor C 1, in one-period, (during T+T * D), the RC loop is a zero state response, has U as nT≤t≤n
C1(t)=V
C* (1-e
-t/RC), and (during the T of T+T * D)≤t≤(n+1), the RC loop is zero input response, has U as n
C1(t)=V
C* e
-t/RC, wherein, R and C are the time constant in RC loop, and at this, the size of time parameter RC should be taken all factors into consideration according to precision and resistance R, capacitor C area occupied in chip of the required Vc voltage of chip, and R and C are big more as can be known by above-mentioned two formulas, then U
C1What (t) change is slow more, U
C1(t) steady-state response can be similar to regards a triangular wave as, when R and C big to making U
C1(t) the amplitude of oscillation very hour, calculate for convenience, it can be approximately a direct voltage (being voltage signal) Vc, promptly the voltage on first capacitor C 1 is that constant is voltage signal Vc in one-period T, so the charging charge of interior first capacitor C 1 of one-period T
The discharge charge of first capacitor C 1
According to the charge conservation theorem, obtain Q
Charge=Q
Discharge, promptly
Thereby can obtain Vc=V2 * D, the duty ratio of voltage signal Vc and current potential V3 is linear as can be known by Vc=V2 * D, slope is V2, and current potential V3 and switching signal V1 are synchronous fully on time domain, therefore the duty ratio D of voltage signal Vc and switching signal V1 is linear as can be known, and slope is V2, above-mentioned C
1Be the capacitance of first capacitor C 1, R
1It is the resistance value of first resistance R 1.
In this specific embodiment, voltage-current converter circuit 2 is mainly by low pressure difference linear voltage regulator (LDO, lowdropout regulator) 7, second resistance R 2 and first current mirror 4 are formed, low pressure difference linear voltage regulator 7 comprises operational amplifier U2 and the 3rd nmos pass transistor M3, first current mirror 4 comprises the 4th PMOS transistor M4 and the 5th PMOS transistor M5, the positive input terminal of operational amplifier U2 inserts voltage signal Vc, the output of operational amplifier U2 is connected with the grid of the 3rd nmos pass transistor M3, the source electrode of the 3rd nmos pass transistor M3 is connected with the negative input end of operational amplifier U2, the source electrode of the 3rd nmos pass transistor M3 is connected with first end of second resistance R 2 with the public connecting end of the negative input end of operational amplifier U2, the second end ground connection of second resistance R 2, the drain electrode of the 3rd nmos pass transistor M3 respectively with the source electrode of the 4th PMOS transistor M4, the grid of the grid of the 4th PMOS transistor M4 and the 5th PMOS transistor M5 is connected, the drain electrode of the drain electrode of the 4th PMOS transistor M4 and the 5th PMOS transistor M5 connects power supply respectively, and the source electrode of the 5th PMOS transistor M5 is exported the first current signal Ic.Voltage-current converter circuit 2 utilizes the degree of depth negative feedback of operational amplifier U2 to obtain an identical voltage Vc1 of voltage signal Vc that inserts with the positive input terminal of operational amplifier U2, the effect of the low pressure difference linear voltage regulator 7 that is made of operational amplifier U2 and the 3rd nmos pass transistor M3 is exactly to force Vc1=Vc, and this voltage Vc1 is added in and obtains a direct current I relevant with voltage signal Vc on second resistance R 2
M3_D, promptly flow through the direct current of the drain electrode of the 3rd nmos pass transistor M3
R2 is the resistance value of second resistance R 2, direct current I
M3_DBy first current mirror of forming by the 4th PMOS transistor M4 and the 5th PMOS transistor M5 4 obtain one with the linear DC compensation electric current I c of voltage Vc1, first current mirror 4 forces I
C=I
M3_D, promptly have
With this DC compensation electric current I c as the first current signal Ic that inputs to slope generating circuit 3, because Vc=Vc1, therefore also there are linear relationship in the first current signal Ic and voltage signal Vc, the first current signal Ic is also linear with the duty ratio D of switching signal V1, promptly according to Vc=V2 * D and
Can obtain
From
The duty ratio D that can draw the first current signal Ic and switching signal V1 is linear.
In this specific embodiment, slope generating circuit 3 is mainly by second current mirror 5, the 3rd current mirror 6, the tenth PMOS transistor M10, the 11 nmos pass transistor M11 and second capacitor C 2 are formed, second current mirror 5 comprises the 6th nmos pass transistor M6 and the 7th nmos pass transistor M7, the 3rd current mirror 6 comprises the 8th PMOS transistor M8 and the 9th PMOS transistor M9, the drain electrode of the 6th nmos pass transistor M6 inserts the first current signal Ic, the drain electrode of the 6th nmos pass transistor M6 respectively with the negative pole end of reference current source IB, the grid of the grid of the 6th nmos pass transistor M6 and the 7th nmos pass transistor M7 is connected, the source electrode of the source electrode of the 6th nmos pass transistor M6 and the 7th nmos pass transistor M7 is ground connection respectively, the drain electrode of the 7th nmos pass transistor M7 respectively with the source electrode of the 8th PMOS transistor M8, the grid of the grid of the 8th PMOS transistor M8 and the 9th PMOS transistor M9 is connected, the positive terminal of reference current source IB, the drain electrode of the drain electrode of the 8th PMOS transistor M8 and the 9th PMOS transistor M9 connects power supply respectively, the source electrode of the 9th PMOS transistor M9 is connected with the drain electrode of the tenth PMOS transistor M10, the grid of the tenth PMOS transistor M11 and the grid of the 11 nmos pass transistor M11 insert the clock signal Vclock in the charging interval that is used to control second capacitor C 2 respectively, the source electrode of the tenth PMOS transistor M10 is connected with the drain electrode of the 11 nmos pass transistor M11, the source ground of the 11 nmos pass transistor M11, second capacitor C 2 is connected between the source electrode of the public connecting end of drain electrode of the source electrode of the tenth PMOS transistor M10 and the 11 nmos pass transistor M11 and the 11 nmos pass transistor M11, the source electrode of the tenth PMOS transistor M10, the public connecting end output slope compensation voltage Vramp of the drain electrode of the 11 nmos pass transistor M11 and second capacitor C 2.Because there are linear relationship in the first current signal Ic and voltage signal Vc, and again because there is linear relationship in the duty ratio D of voltage signal Vc and switching signal V1, and the reference current of reference current source IB is a constant, at this, reference current source IB provides a fixed bias for slope generating circuit 3, the size of its reference current is by the decision of the required slope compensation size of peak current control model chip, therefore also there is linear relationship in the second current signal Ic2 (Ic2=Ic+IB) of the first current signal Ic and reference current source IB stack back formation with the duty ratio D of switching signal V1, the second current signal Ic2 obtains constant current (i.e. the charging current of second capacitor C 2) Iramp by second current mirror of being made up of the 6th nmos pass transistor and the 7th nmos pass transistor 5 and the 3rd current mirror of being made up of the 8th PMOS transistor and the 9th PMOS transistor 6, wherein, the effect of second current mirror 5 and the 3rd current mirror is exactly to force constant current Iramp to equal the second current signal Ic2.Above-mentioned clock signal Vclock is the output signal of the oscillator in the peak current control model chip, it has fixing frequency f and duty ratio Dclock in same peak current control model chip, when clock signal Vclock is low level, the tenth PMOS transistor M10 conducting, the 11 nmos pass transistor is closed, slope generating circuit 3 can obtain slope compensation voltage Vramp in the regular hour 2 chargings of second capacitor C with constant current Iramp, wherein, charging interval t1=Dclock/f; When clock signal Vclock is high level, the tenth PMOS transistor M10 closes, the 11 nmos pass transistor conducting, second capacitor C 2 is passed through the 11 nmos pass transistor with very big current discharge, discharge off before next clock cycle generation, wherein discharging current is relevant with the breadth length ratio of the 11 nmos pass transistor, and to sum up the stable state on second capacitor C 2 should be a slope compensation voltage Vramp mutually, and this slope compensation voltage Vramp can be approximated to be a triangular wave
C
2Be the capacitance of second electric capacity, promptly the slope of slope compensation voltage Vramp and constant current Iramp are linear, according to
With
Can obtain
From
The duty ratio D that can learn slope compensation voltage Vramp and switching signal V1 is linear.In same peak current control model chip, f, R
2And C
2Be definite value, therefore rationally regulate
In reference voltage V 2 and the size of the reference current of reference current source IB, can make chip under all duty ratio conditions, all have suitable slope compensation size, have good load capacity and anti-power supply interference performance, realization is according to the function of the slope of the big or small linear regulation slope compensation voltage of the duty ratio of the switching signal in the peak current control model chip.
Claims (4)
1. the system of a linearly adjusting slope compensation voltage slope, it is characterized in that comprising duty detection circuit, voltage-current converter circuit, slope generating circuit and reference current source, described duty detection circuit is converted to the switching signal of input and the linear voltage signal of described switching signal, and described voltage signal is transferred to described voltage-current converter circuit, described voltage-current converter circuit is also exported first current signal that converts to of described voltage signal linearity, described first current signal and the superimposed formation of described reference current source input to second current signal of described slope generating circuit, described slope generating circuit output slope compensation voltage, the duty ratio of described slope compensation voltage and described switching signal is linear.
2. the system of a kind of linearly adjusting slope compensation voltage slope according to claim 1, it is characterized in that described duty detection circuit is mainly by inverter, first nmos pass transistor, second nmos pass transistor, first resistance and first electric capacity are formed, the input of described inverter inserts described switching signal, the output of described inverter is connected with the grid of described first nmos pass transistor and the grid of described second nmos pass transistor respectively, the drain electrode of described first nmos pass transistor inserts reference voltage, the source electrode of described first nmos pass transistor is connected with first end of described first resistance, the drain electrode of described second nmos pass transistor is connected with first end of described first resistance, the source ground of described second nmos pass transistor, described first electric capacity is connected between the source electrode of second end of described first resistance and described second nmos pass transistor, output of the public connecting end of described first resistance and described first electric capacity and the linear voltage signal of described switching signal.
3. the system of a kind of linearly adjusting slope compensation voltage slope according to claim 1 and 2, it is characterized in that described voltage-current converter circuit is mainly by low pressure difference linear voltage regulator, second resistance and first current mirror are formed, described low pressure difference linear voltage regulator comprises operational amplifier and the 3rd nmos pass transistor, described first current mirror comprises the 4th PMOS transistor and the 5th PMOS transistor, the positive input terminal of described operational amplifier inserts described voltage signal, the output of described operational amplifier is connected with the grid of described the 3rd nmos pass transistor, the source electrode of described the 3rd nmos pass transistor is connected with the negative input end of described operational amplifier, the source electrode of described the 3rd nmos pass transistor is connected with first end of described second resistance with the public connecting end of the negative input end of described operational amplifier, the second end ground connection of described second resistance, the drain electrode of described the 3rd nmos pass transistor respectively with the transistorized source electrode of described the 4th PMOS, transistorized grid of described the 4th PMOS and the transistorized grid of described the 5th PMOS are connected, described the 4th PMOS transistor drain and described the 5th PMOS transistor drain connect power supply respectively, and the transistorized source electrode of described the 5th PMOS is exported described first current signal.
4. the system of a kind of linearly adjusting slope compensation voltage slope according to claim 3, it is characterized in that described slope generating circuit is mainly by second current mirror, the 3rd current mirror, the tenth PMOS transistor, the 11 nmos pass transistor and second electric capacity are formed, described second current mirror comprises the 6th nmos pass transistor and the 7th nmos pass transistor, described the 3rd current mirror comprises the 8th PMOS transistor and the 9th PMOS transistor, the drain electrode of described the 6th nmos pass transistor inserts described first current signal, the drain electrode of described the 6th nmos pass transistor respectively with the negative pole end of described reference current source, the grid of the grid of described the 6th nmos pass transistor and described the 7th nmos pass transistor is connected, the source electrode of the source electrode of described the 6th nmos pass transistor and described the 7th nmos pass transistor is ground connection respectively, the drain electrode of described the 7th nmos pass transistor respectively with the transistorized source electrode of described the 8th PMOS, transistorized grid of described the 8th PMOS and the transistorized grid of described the 9th PMOS are connected, the positive terminal of described reference current source, described the 8th PMOS transistor drain and described the 9th PMOS transistor drain connect power supply respectively, the transistorized source electrode of described the 9th PMOS is connected with described the tenth PMOS transistor drain, the grid of transistorized grid of described the tenth PMOS and described the 11 nmos pass transistor inserts the clock signal in the charging interval that is used to control described second electric capacity respectively, the transistorized source electrode of described the tenth PMOS is connected with the drain electrode of described the 11 nmos pass transistor, the source ground of described the 11 nmos pass transistor, described second electric capacity is connected between the source electrode of the public connecting end of drain electrode of transistorized source electrode of described the tenth PMOS and described the 11 nmos pass transistor and described the 11 nmos pass transistor, the transistorized source electrode of described the tenth PMOS, the public connecting end of the drain electrode of described the 11 nmos pass transistor and described second electric capacity is exported described slope compensation voltage.
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Effective date of registration: 20170116 Address after: 315809 Beilun City, Ningbo Province, Wan Chai street, Wan Jing Road, No. G, block, floor three, 12-3, 213 Patentee after: Core integrated circuit (Ningbo) Co., Ltd. Address before: Ningbo city science and Technology Park in Zhejiang province 315040 lease Poplar Road No. 7 Lane 578 Patentee before: Daily Silver IMP Microelectronics Co., Ltd. |