CN101794771B

CN101794771B - SIP (Session Initiation Protocol) chip and SOC (System On Chip) thereof

Info

Publication number: CN101794771B
Application number: CN2010101157011A
Authority: CN
Inventors: 罗挺; 吴大畏
Original assignee: SHENZHEN SILICONGO SEMICONDUCTOR CO Ltd
Current assignee: Shenzhen SiliconGo Semiconductor Co., Ltd.
Priority date: 2010-02-26
Filing date: 2010-02-26
Publication date: 2011-06-08
Anticipated expiration: 2030-02-26
Also published as: CN101794771A

Abstract

The invention relates to an SOC (Session Initiation Protocol) which comprises a chip functional control module, a pin module and a pin control module, wherein the pin control module is connected between the chip functional control module and the pin module for controlling the working mode of the pin module. The invention also provides an SIP chip and solves the reduction problem of binding rate caused by crossed bound wires during the binding among bare chips in the prior art.

Description

SIP chip and SOC chip thereof

Technical field

The present invention relates to the chip technology field, relate in particular to SIP chip and SOC chip thereof.

Background technology

SIP (System in Package) encapsulation technology is by a plurality of bare chips (Die) are encapsulated, form the complete relatively subsystem of function, such as can be with system level chip (System on Chip, SOC) and the various memories (Memory) used of this SOC be packaged together and form the SOC subsystem, thereby reduce the quantity of external devices and the size of finished product system.

When carrying out the SIP encapsulation, can connect by substrate (Substrate) between the different Die, also can directly carry out bare chip bare chip (Die to die) is bound.Connect by substrate and to have very high flexibility, but cost also is relatively higher than the Die-to-die binding; Though and Die-to-die binding cost is lower, dumb.For example, when SOC and memory were encapsulated, if be provided with the pin positions of SOC at the memory of a certain producer, in the time of being replaced with the memory of other producer, it was incompatible just to run into pin possibly, the situation that can't carry out the Die-to-die binding.

Summary of the invention

The object of the present invention is to provide a kind of chip, when carrying out bare chip to the binding of bare chip in the prior art, cause binding the problem that yield descends because binding line intersects to solve.

The invention provides a kind of SOC chip, comprise chip functions control module and pin module, and the pin control module, this pin control module is connected between chip functions control module and the pin module, is used to control the mode of operation of pin module.

Preferably, aforementioned tube foot control molding piece comprises a plurality of pin control submodules, and the pin module comprises a plurality of pins, and pin is controlled submodule and corresponding pin connection, is used to control the mode of operation of corresponding pin.

Preferably, the said chip functional control module comprises a plurality of Enable Pins, output and the binding end that connects with corresponding pin control submodule, and described pin control submodule is selected corresponding Enable Pin and the output pin output level to correspondence according to the level of binding end.

Preferably, the said chip functional control module also comprises a plurality of inputs that connect with corresponding pin control submodule, described pin control submodule according to the level of binding end to the corresponding input end incoming level.

Preferably, aforementioned tube foot control system submodule comprises first multiplexer that is connected with corresponding Enable Pin, pin and binding end, is used for selecting the pin output level of corresponding Enable Pin to correspondence according to the level of binding end.

Preferably, aforementioned tube foot control system submodule also comprises second multiplexer that is connected with corresponding output, pin and binding end, is used for selecting the pin output level of corresponding output to correspondence according to the level of binding end.

Preferably, aforementioned tube foot control system submodule also comprises the 3rd multiplexer that is connected with corresponding input end, pin and binding end, and the level that is used for holding according to binding is to the corresponding input end incoming level.

The present invention also provides a kind of SIP chip, comprises chip to be bound, and above-mentioned SOC chip, is connected with chip to be bound.

SOC chip provided by the present invention can be used for flexible configurable SIP encapsulation, control the mode of operation of the pin of SOC chip by binding, solve when carrying out bare chip in the prior art, cause binding the problem that yield descends because binding line intersects to the binding of bare chip.

Description of drawings

Fig. 1 is the SOC chip operation is bound the formed SIP chip in back at pattern one and Flash1 a schematic diagram;

Fig. 2 is the SOC chip operation is bound the formed SIP chip in back at pattern two and Flash2 a schematic diagram;

Fig. 3 is the SOC chip operation is bound the formed SIP chip in back at pattern three and Flash3 a schematic diagram;

Fig. 4 is the SOC chip operation is bound the formed SIP chip in back at pattern four and Flash4 a schematic diagram;

Fig. 5 is the module map of a kind of embodiment of SOC chip of the present invention;

Fig. 6 is the concrete structure figure of SOC chip of the present invention.

Embodiment

Below in conjunction with the drawings and specific embodiments technical solution of the present invention is described in further detail, can be implemented so that those skilled in the art can better understand the present invention also, but illustrated embodiment is not as a limitation of the invention.

The present invention is packaged together with Nand flash bare chip that different pin puts in order with SOC and is example, is elaborated.The pin of present Nand Flash bare chip mainly contains four kinds of different putting in order, and the annexation of corresponding SOC and Flash1, Flash2, Flash3 and Flash4 respectively as shown in Figure 1, Figure 2, Figure 3 and Figure 4.

Fig. 1 is the SOC chip operation is bound the formed SIP chip in back at pattern one and Flash1 a schematic diagram.

Fig. 2 is the SOC chip operation is bound the formed SIP chip in back at pattern two and Flash2 a schematic diagram.

Fig. 3 is the SOC chip operation is bound the formed SIP chip in back at pattern three and Flash3 a schematic diagram.

Fig. 4 is the SOC chip operation is bound the formed SIP chip in back at pattern four and Flash4 a schematic diagram.

In the SOC chip shown in Fig. 1 to 4, have 20 pins, wherein pin one to 18 is Enable Pin, input and the output of SOC chip, and pin one 9 and 20 is binding end, and VDD is high level (promptly 1), and VSS is low level (promptly 0).

The pin working mode of SOC chip provided by the present invention is as shown in table 1, table 1 connects different level combinations by binding end 1 and binding end 2, pin one is operated in respectively under the different patterns to pin one 8, thereby the realization pin one is arranged by different functional sequences to pin one 8.For example, when the level of binding end 1 and 2 was 0, pin one was as the MIO0 pin; When the level of binding end 1 and 2 was respectively 1 and 0, pin one was as the MWP pin; When the level of binding end 1 and 2 was respectively 0 and 1, pin one was as the MIO0 pin; When the level of binding end 1 and 2 was 1, pin one was as the MIO7 pin, and the rest may be inferred for other pin.

Table 1

Sequence number	The level of binding end 1 is that the level of 0 binding end 2 is 0	The level of binding end 1 is that the level of 1 binding end 2 is 0	The level of binding end 1 is that the level of 0 binding end 2 is 1	The level of binding end 1 is that the level of 1 binding end 2 is 1
					1	MIO0	?MWP	?MIO0	?MIO7
2	MIO1	?MWE	?MIO1	?MIO6
					3	MIO2	?MALE	?MIO2	?MIO5
4	MIO3	?MCLE	?MIO3	?MIO4
					5	MIO4	?MCE3	?MRB0	?MWP
6	MIO5	?MCE2	?MRE	?MWE
					7	MIO6	?MCE1	?MCE0	?MALE
8	MIO7	?MCE0	?MCE1	?MCLE
					9	MRB0	?MRE	?MCE2	?MCE3
10	MRE	?MRB0	?MCE3	?MCE2
					11	MCE0	?MIO7	?MCLE	?MCE1
12	MCE1	?MIO6	?MALE	?MCE0
					13	MCE2	?MIO5	?MWE	?MRE
14	MCE3	MIO4	MWP	MRB0
					15	MCLE	MIO3	MIO4	MIO3
16	MALE	MIO2	MIO5	MIO2
					17	MWE	MIO1	MIO6	MIO1
18	MWP	MIO0	MIO7	MIO0

Can find out from table 1:

When binding end 1 connects 0, binding end 2 connects 0, and SOC is operated in pattern one, this moment SOC pin one to the functional definition of pin one 8 shown in the secondary series of table 1, according to the definition of this pin kinetic energy, pin one to the connected mode of the pin of pin one 8 and Flash bare chip as shown in Figure 1.At this moment, in the time of the binding of the pin of SOC and first kind of Flash bare chip, the intersection of binding line can not appear.

When binding end 1 connects 1, binding end 2 connects 0, and SOC is operated in pattern two, this moment SOC pin one to the functional definition of pin one 8 as shown in the 3rd of table 1 is listed as, according to the definition of this pin kinetic energy, pin one to the connected mode of the pin of pin one 8 and Flash bare chip as shown in Figure 2.At this moment, in the time of the binding of the pin of SOC and second kind of Flash bare chip, the intersection of binding line can not appear.

When binding end 1 connects 0, binding end 2 connects 1, and SOC is operated in pattern three, this moment SOC pin one to the functional definition of pin one 8 as shown in the 4th of table 1 is listed as, according to the definition of this pin kinetic energy, pin one to the connected mode of the pin of pin one 8 and Flash bare chip as shown in Figure 3.At this moment, in the time of the binding of the pin of SOC and the third Flash bare chip, the intersection of binding line can not appear.

When binding end 1 connects 1, binding end 2 connects 1, and SOC is operated in pattern four, this moment SOC pin one to the functional definition of pin one 8 as shown in the 5th of table 1 is listed as, according to the definition of this pin kinetic energy, pin one to the connected mode of the pin of pin one 8 and Flash bare chip as shown in Figure 4.At this moment, in the time of the binding of the pin of SOC and the 4th kind of Flash bare chip, the intersection of binding line can not appear.

Fig. 5 is the module map of a kind of embodiment of SOC chip of the present invention.

SOC chip in the present embodiment comprises chip functions control module 100, pin module 300 and pin control module 200.Pin control module 200 is connected between chip functions control module 100 and the pin module 300, is used to control the mode of operation of pin module 300.

Wherein, pin control module 200 comprises a plurality of pin control submodules (pin control submodule 1 to 18), and the pin module comprises a plurality of pins (pin one to 18), and pin is controlled submodule and corresponding pin connection, is used to control the mode of operation of corresponding pin.

Present embodiment is realized the redistribution of the pin function of chip by the mode of operation of control pin, reaches corresponding with the pin of chip to be bound, and avoids occurring the phenomenon that binding line intersects.The number of SOC chip pin can be for a plurality of, and present embodiment is an example with 18 pins.Chip to be bound can be memory, interface chip or processor.Memory can be Nand flash, Nor Flash, Sram, Sdram or FRAM.

Fig. 6 is the concrete structure figure of SOC chip of the present invention.

In the present embodiment, to be example with the structure of pin one and pin control submodule 1 inside, the annexation of chip of the present invention is described, internal structure and operation principle thereof, the internal structure of other pin and pin control submodule is identical with pin one and pin control submodule 1.

Chip functions control module 100 comprises a plurality of Enable Pins, output and the binding end that connects with corresponding pin control submodule, to select corresponding Enable Pin and the output pin output level to correspondence according to the level of binding end.In the present embodiment, the Enable Pin relevant with pin one is MIO0 Enable Pin, MWP Enable Pin and MIO7 Enable Pin; The output relevant with pin one is MIO0 output, MWP output and MIO7 output; All pins use identical binding end 1 and binding end 2.

Chip functions control module 100 also comprises a plurality of inputs that connect with corresponding pin control submodule, with according to the level of binding end to the corresponding input end incoming level.In the present embodiment, the input relevant with pin one is MIO0 input, MWP input and MIO7 input.

Pin control submodule 1 also comprises first multiplexer 201 that is connected with corresponding Enable Pin, pin and binding end, to select the pin output level of corresponding Enable Pin to correspondence according to the level of binding end.Wherein, the S1 pin of first multiplexer is connected to the MIO0 Enable Pin, and the S2 pin is connected to the MWP Enable Pin, and the S3 pin is connected to the MIO0 Enable Pin, the S4 pin is connected to the MIO7 Enable Pin, and the MIO0 Enable Pin that the S1 pin is connected with the S3 pin is essentially same Enable Pin.

Pin control submodule 1 also comprises second multiplexer 202 that is connected with corresponding output, pin and binding end, is used for selecting the pin output level of corresponding output to correspondence according to the level of binding end.Wherein, the S1 pin of second multiplexer is connected to the MIO0 output, and the S2 pin is connected to the MWP output, and the S3 pin is connected to the MIO0 output, the S4 pin is connected to the MIO7 output, and the MIO0 output that the S1 pin is connected with the S3 pin is essentially same output.

Pin control submodule 1 also comprises the 3rd multiplexer 203 that is connected with corresponding input end, pin and binding end, and the level that is used for holding according to binding is to the corresponding input end incoming level.Wherein, the 3rd multiplexer 203 is that pin one and pin one 8 are shared, and promptly pin one 8 is connected to the S2 and the S4 pin of the 3rd multiplexer 203; Accordingly, also shared same the 3rd multiplexer of pin two and pin one 7, and the like.

SOC chip provided by the present invention can be used for flexible configurable SIP encapsulation, the mode of the pin by binding SOC chip is operated in different patterns, solve when carrying out bare chip in the prior art, cause binding the problem that yield descends because binding line intersects to the binding of bare chip.

Below only be the preferred embodiments of the present invention; be not so limit claim of the present invention; every equivalent structure or equivalent flow process conversion that utilizes specification of the present invention and accompanying drawing content to be done; or directly or indirectly be used in other relevant technical fields, all in like manner be included in the scope of patent protection of the present invention.

Claims

1. SOC chip, comprise chip functions control module and pin module, it is characterized in that described chip also comprises the pin control module, described pin control module is connected between chip functions control module and the pin module, is used to control the mode of operation of pin module; Described pin control module comprises a plurality of pin control submodules, and the pin module comprises a plurality of pins, and pin is controlled submodule and corresponding pin connection, is used to control the mode of operation of corresponding pin; Described chip functions control module comprises a plurality of Enable Pins, output and the binding end that connects with corresponding pin control submodule, and described pin control submodule is selected corresponding Enable Pin and the output pin output level to correspondence according to the level of binding end.

2. SOC chip as claimed in claim 1, it is characterized in that, described chip functions control module also comprises a plurality of inputs that connect with corresponding pin control submodule, described pin control submodule according to the level of binding end to the corresponding input end incoming level.

3. as each described SOC chip of claim 1 to 2, it is characterized in that, described pin control submodule comprises first multiplexer that is connected with corresponding Enable Pin, pin and binding end, is used for selecting the pin output level of corresponding Enable Pin to correspondence according to the level of binding end.

4. as each described SOC chip of claim 1 to 2, it is characterized in that, described pin control submodule also comprises second multiplexer that is connected with corresponding output, pin and binding end, is used for selecting the pin output level of corresponding output to correspondence according to the level of binding end.

5. SOC chip as claimed in claim 4 is characterized in that, described pin control submodule also comprises the 3rd multiplexer that is connected with corresponding input end, pin and binding end, and the level that is used for holding according to binding is to the corresponding input end incoming level.

6. a SIP chip comprises chip to be bound, and it is characterized in that, also comprises SOC chip as claimed in claim 5, is connected with chip described to be bound.