CN101788963B - DRAM (Dynamic Random Access Memory) storage control method and device - Google Patents
DRAM (Dynamic Random Access Memory) storage control method and device Download PDFInfo
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Abstract
The invention discloses DRAM storage control method and device. The method comprises the following steps of: A10. decoding read and write requests and rearranging into a plurality of BANK-based read and write request arrays according to BANK addresses; A20. respectively arbitrating the read and write requests; A30. respectively generating respective read and write request commands and activating commands and/or precharge commands; and A40. sending the read and write request commands to a command bus, and on the premise of satisfying the read and write protection time limit of a DRAM, inserting the activating commands and/or percharge commands of the read and write command requests in the other BANKs based read and write request arrays before the read and write command request in the BANK-based read and write request array. In the invention, the activating commands and the precharge commands can be completely hidden in the data transmission process, and seemingly, a DRAM data bus always transmits data, and therefore, the bus efficiency of the DRAM is greatly improved.
Description
Technical field
The present invention relates to DRAM, be specifically related to DRAM storage controlling method and device.
Background technology
Employed terminological interpretation is following in the application documents:
BANK, memory cell array;
BC, bank controller, BANK control module;
MC, master controller, MC main control unit.
At present, data communication field is used high capacity external memory storages such as SDRAM, DDR SDRAM and DDR2 SDRAM through regular meeting.And the bus bandwidth of external memory storage has often determined the maximum bandwidth processing power of a data communication system in real work, and therefore, the bus bandwidth that improves DRAM is one of important channel of improving data communication system bandwidth processing ability.
As shown in Figure 1, DRAM is made up of memory cell array 100, command decoder 101, BANK address decoder 103, row-address decoder 102, column address decoder 104, IO interface control section 105 and DLL unit 106.Memory cell array 100 is positioned at the core of DRAM, and each dram chip has 4 or 8 memory cell arrays 100 (being BANK) usually, and each data bit separate, stored is in the storage unit lattice by row address and column address addressing of specifying BANK.So the client requests address correspondingly is divided into 3 parts, i.e. BANK address, row address and column address are respectively by the decode storage unit of corresponding address of BANK address decoder 103, row-address decoder 102 and column address decoder 104.Wherein row address and column address are read into the row address buffer and the column address buffer of storage array respectively when the capable gating of the RAS of command decoder 101 and CAS column selection are logical.All storage instructions of DRAM CS sheet choosing effectively, CKE is effectively and during the rising edge of clock; 3 order wire RAS, CAS and WEN and assembled state by DRAM confirm, mainly comprises pattern loading instruction, refreshing instruction, write command, reads instruction, activation instruction and charging instruction.The IO interface control section 105 of DRAM is accomplished the bidirectional data transfers of data and is write the data mask function.106 of DLL unit are input clock and the sheet internal clocks of calibration DRAM under high-frequency clock, with reduce owing in the sheet, the data AC time sequence difference that causes of sheet external clock difference.
The access control method of DRAM has multiple, and the utilization ratio of its bus of Different control method is different.For example after accomplishing read-write operation, whether to this activation page charge and close the utilization ratio that will influence bus.Before activation page has not been closed, if follow-up read-write operation is addressed to same one page, just can directly read and write, save activationary time, this is referred to as page or leaf and hits (page hit); If follow-up read-write operation is addressed to the different pages, just must close this page earlier, activate the page of wanting addressing again, just can read and write then, this just causes time-delay very big on the time, is referred to as page or leaf disappearance (page miss); In addition, time loss between page or leaf hit and page or leaf disappearance between be that accessing operation wants the page of addressing to close, only need to carry out activate the back just can read-write operation, be referred to as a page free time (a page idle).
DRAM supports the random read-write access, the access of promptly a plurality of BANK table tennis.When this representes that a certain BANK does the read/write access operation; Other BANK can do charging or activation command, utilize this characteristic, are avoiding under data bus conflict and the command line conflict; Can overlappingly send instruction and give different B ANK; Be the concurrent working that can interlock between the BANK, make full use of bus and reach, this is the important channel of improving the DRAM access performance.
In addition; DRAM writes or switches to when reading by writing by reading to switch to; All losses if having time on the data bus, and client's read write command is at random, must cause a large amount of read-writes, write-read to switch if carry out accessing operation by the client requests order fully; Produce a large amount of idle conditions on the data bus, therefore reducing access command, to switch the bandwidth lose that causes also be to improve DRAM access features important channel.
In addition; Some special client's reading and writing requests are arranged, and the data volume of these requests can not be carried out access by the monoblock data of DRAM, and for example DDR2 SDRAM uses 32bit bit wide and BL4 pattern (Burst Lengthmode; Implication is a DDR2 burst-length pattern configurations; Configurable is 4 or 8), promptly a DDR piece data quantity transmitted is 4 * 32bit (16BYTE), and certain request only needs to handle 14BYTE; DDR2 can only effectively transmit 14BYTE in the time that can transmit 16BYTE so, has therefore reduced bandwidth availability ratio; Even some clients' reading and writing request in addition; Once need data quantity transmitted to have only 1BYTE; For example ethernet frame is stored in the DDR2 application, if press 64BYTE as a data quantity transmitted, the postamble of the ethernet frame of 65BYTE just only remains a next BYTE so; This can cause a large amount of losses on the DRAM data bus, and it also is to improve the problem that the DRAM access performance must solve that elimination customer data and DRAM data block size do not match.
This shows that the bus efficiency of DRAM remains to be improved further at present.
Summary of the invention
Technical matters to be solved by this invention is to solve the problem that further improves the bus efficiency of DRAM.
In order to solve the problems of the technologies described above, the technical scheme that the present invention adopted provides a kind of DRAM storage controlling method, may further comprise the steps:
A10, client's reading and writing request carried out address decoder after, be arranged in a plurality of reading and writing request queues again according to the BANK address, and the back is parallel synchronously sends with above-mentioned a plurality of reading and writing request queues based on each BANK based on each BANK;
A20, respectively each is arbitrated based on a plurality of reading and writing requests in the reading and writing request queue of each BANK, and rank according to priority orders;
A30, according to each based on the reading and writing request in the reading and writing request queue of each BANK, generate separately reading and writing request command and activation command and/or precharge command respectively;
A40, the reading and writing request command is delivered to command line; And satisfying under the DRAM reading and writing prerequisite in protection time limit, insert the activation command and/or the precharge command of the reading and writing command request in other BANK reading and writing request queues before the reading and writing command request order in this BANK reading and writing request queue.
In the such scheme, the request queue of writing based on each BANK in the steps A 10 generates through following steps:
A101, with the client who receives write request put into have certain configurable deep write the solicited message formation;
A102, the client that will write solicited message formation exit successively write request and carry out address resolution;
A103, the BANK address of writing request according to the back client of parsing rearrange a plurality of request queues of writing based on each BANK again with it, write respectively in the request pretreatment unit;
A104, a plurality of back synchronously walking abreast of request queue of writing based on each BANK are sent.
Read request queue based on each BANK generates through following steps:
A111, client's read request of receiving put into read request message queue with certain configurable deep;
A112, order are carried out address resolution with client's read request in read request message queue exit;
A113, it is rearranged a plurality of read request queue based on each BANK again according to the BANK address of resolving back client's read request; Write respectively in the read request pretreatment unit; In this step; The current read-out position of the first pointed read request message queue is set, the writing position of this read request of second pointed in the read request pretreatment unit is set, the read request corresponding with first pointer writes the relevant position in the read request pretreatment unit of second pointed;
A114, the back is parallel synchronously sends with a plurality of read request queue based on each BANK.
In steps A 40, read each BANK reading and writing request queue successively according to the current reading and writing solicited status sign that is sent to command line.
When the data width of a reading and writing request during greater than DRAM interface data bit wide; This reading and writing request msg is cut apart according to DRAM interface data bit wide; And, send the reading and writing request after cutting apart to DRAM by the mode continuous of same page according to cutting apart corresponding size of data and the start address of each reading and writing request of back.
The present invention also provides a kind of DRAM memory control device; This DRAM is made up of a plurality of BANK; Be provided with a plurality of basic units of storage of confirming by row address and column address respectively among each BANK; Described memory control device comprises some reading and writing request interface processing units; Asynchronous converting unit; With BANK number corresponding reading and writing request queue arbitration unit and BANK control module and reading and writing buffer queue unit and MC main control unit; Be respectively equipped with reading and writing request address demoder and reading and writing request queue pretreatment unit in the described reading and writing request interface processing unit, BANK address, row address and column address decoder parse client's reading and writing request address, and this address is corresponding with the corresponding basic unit of storage of corresponding BANK; Described reading and writing request queue pretreatment unit is arranged in a plurality of reading and writing request queues based on each BANK again according to the BANK address of the client's reading and writing request after resolving, and with above-mentioned a plurality of reading and writing request queues parallel reading and writing request queue arbitration units that mail to after asynchronous converting unit is synchronous based on each BANK; Described reading and writing request queue arbitration buffer cell is arbitrated a plurality of reading and writing requests in the reading and writing request queue of each BANK respectively, and generates a plurality of reading and writing buffer queues according to priority orders and be buffered in the reading and writing buffer queue unit; Described BANK control module; According to the reading and writing request in each BANK reading and writing request queue in the reading and writing buffer queue unit; Generate separately reading and writing request command and activation command and/or precharge command respectively, the parallel MC main control unit that mails to of above-mentioned reading and writing request command and activation command and/or precharge command; The MC main control unit; The reading and writing request command of receiving is delivered to command line; And satisfying under the DRAM reading and writing prerequisite in protection time limit, insert the activation command and/or the precharge command of the reading and writing command request in other BANK reading and writing request queues before the reading and writing command request order in this BANK reading and writing request queue.
In the said apparatus, also be provided with solicited message queue unit in the described reading and writing request interface processing unit with certain configurable deep.
Be provided with first, second pointer in client's read request interface processing unit, indicate the read-out position of read request message queue in client's read request interface processing unit and the writing position in the read request pretreatment unit respectively.
Be provided with the collaborative status unit of MC positioning indicator and MC in the MC main control unit; This MC positioning indicator has to be write, writes transition, read, read transition, refreshes protection and refresh six kinds of state Warning Marks of protection releasing; Be provided with the collaborative status unit of BC in the BC control module and to each reading and writing request one BC positioning indicator be set all, this BC positioning indicator has write gate, write and read transition, read gate, read and write transition, refresh and refresh six kinds of state Warning Marks of protection;
When the MC main control unit sends the request write or during read request to DRAM; The Status Flag of its positioning indicator is set to write or read; The collaborative status unit of MC sends to the collaborative status unit of BC and writes collaborative indication or read collaborative indication simultaneously; The Status Flag of the collaborative status unit BC positioning indicator of BC is set to write gate or read gate; And whole the writing buffer queue or read buffer queue of gating, close whole reading buffer queue or write buffer queue, this moment, the MC main control unit can only respond request write or read request at the write or read of configuration in the time period; Do not handle read request or write request; The Status Flag of MC positioning indicator was set to write transition or reads transition after the write or read time period finished, and after each was write request or read request and sends, the Status Flag of this BC positioning indicator is set to write to be read transition or read and write transition;
When the Status Flag of MC positioning indicator when writing transition or reading transition; The collaborative status unit of MC sends to the collaborative status unit of BC and writes the collaborative indication of transition or read the collaborative indication of transition; The Status Flag of the collaborative status unit BC positioning indicator of BC is set to write to be read transition or reads and write transition; And gating is remaining writes buffer queue or read buffer queue; Close whole reading buffer queue or write buffer queue, wait all remainingly to write request or after read request all handled, the MC main control unit sent read request or writes request to DRAM; And its Status Flag is set to read or write, and the Status Flag of all BC positioning indicators all is set to read or write;
When the Status Flag of MC positioning indicator when reading or writing; The collaborative status unit of MC sends to the collaborative status unit of BC and reads collaborative indication or write collaborative indication; The Status Flag of the collaborative status unit BC positioning indicator of BC is set to read or write; And whole the reading buffer queue or write buffer queue of gating, close whole writing buffer queue or read buffer queue, the MC main control unit can only respond read request or write request reading or writing of configuration in the time period this moment; Not processing write requests or read request; Read or write the time period finish after the Status Flag of MC positioning indicator be set to read transition or write transition, after each read request or the request of writing were sent, the Status Flag of this BC positioning indicator is set to read to be write transition or writes and read transition;
When the Status Flag of MC positioning indicator when reading transition or writing transition; The collaborative status unit of MC sends to the collaborative status unit of BC and reads the collaborative indication of transition or write the collaborative indication of transition; The collaborative status unit of BC is write the Status Flag of BC positioning indicator transition or is write and read transition for reading; Wait after all the remaining read requests or the request of writing all handle; The Status Flag of MC positioning indicator is set to write or read, and the Status Flag of all BC positioning indicators all is set to write gate or read gate;
When the Status Flag of BC positioning indicator when refreshing; The Status Flag of BC positioning indicator is set to refresh protection; Simultaneously the collaborative status unit of BC sends the protection instruction to the collaborative status unit of MC, and MC main control unit cell response refresh command is after waiting refresh command to carry out to finish; The collaborative status unit of BC sends to the collaborative status unit of MC and refreshes protection releasing instruction, and the MC main control unit was in and received the reading and writing solicited status this moment.
Also comprise data partitioning unit in this device; Whether this data partitioning unit is whether basis for estimation obtains the judged result to cutting apart this reading and writing requested data block greater than DRAM interface data bit wide with the data width of a reading and writing request of client; When judged result shows need cut apart this reading and writing requested data block the time; This reading and writing request msg is cut apart according to DRAM interface data bit wide; Calculate and cut apart corresponding data block size and the start address of each request of back, and send the read-write requests after cutting apart to DRAM by the mode continuous of same page.
The present invention; Client's reading and writing request is converted to the reading and writing request of corresponding BANK based on the BANK address; BANK produces reading and writing command request separately simultaneously successively respectively based on separately reading and writing request queue, and the reading and writing command request of above-mentioned produced simultaneously BANK is parallel sends; Precedence by the reading and writing command request of receiving BANK is sent to command line successively; And order activation command and the precharge command that is inserted in back BANK before in the reading and writing command request of current BANK respectively, like this, activation instruction and precharge instruction can be hidden in the data transmission procedure fully; The DRAM data bus is carrying out data transmission always on the surface, has therefore improved the bus efficiency of DRAM greatly.
Description of drawings
Fig. 1: traditional DRAM structural representation;
Fig. 2: the structural representation of DRAM memory control device of the present invention;
Fig. 3: BC control module workflow diagram in the DRAM memory control device of the present invention;
Fig. 4: MC control module and BC control module interact and accomplish the process flow diagram of read write command binding among the present invention;
Fig. 5: the sequential chart under traditional DRAM control method;
Fig. 6: the sequential chart under the DRAM storage controlling method of the present invention.
Embodiment
To the lower problem of present DRAM external memory stores bus efficiency; The invention provides a kind of DRAM memory control device; This device has improved the utilization ratio of DRAM memory bus, thereby has improved the maximum bandwidth processing power of data communication system in real work greatly.Below in conjunction with accompanying drawing and specific embodiment the present invention is made detailed explanation.
Fig. 2 is the structural representation of DRAM memory control device of the present invention; As shown in Figure 2; This device 200 is accomplished the data storage between client and the DRAM220 through memory bus; Wherein have a plurality of BANK (present embodiment is BANK1, BANK2, BANK3 and BANK4) among the DRAM (DDR2 or DDR) 220, have a plurality of basic units of storage on each BANK.DRAM memory control device 200 comprises that the client writes request interface processing unit 210, client's read request interface processing unit 211, writes the asynchronous converting unit of request 212, the asynchronous converting unit of read request 213, write request arbitration unit 214, read request arbitration unit 215, write buffer queue unit 216, read buffer queue unit 217, BC control module 218 and MC control module 219; Wherein write request interface processing unit 210, client's read request interface processing unit 211 can have a plurality of parallel uses according to client's number, write the request arbitration unit 214, read request arbitration unit 215 and BC control module 218 number identical with the BANK number of the DDR2 that selects for use.
The client writes and is provided with BANK address, row address and column address decoder in the request interface processing unit 210, and above-mentioned demoder is used to parse client's the request address of writing, and this address is corresponding with the respective memory unit of corresponding BANK.This client writes also to be provided with in the request interface processing unit 210 has writing the solicited message formation and writing the request queue pretreatment unit of certain adjustment degree of depth; Writing solicited message buffer queue client writes request interface processing unit 210 received clients and writes request; Write request the client and can play certain " peak disappears " effect when peak bandwidth occurring; Write the request queue pretreatment unit and be arranged in a plurality of reading and writing request queues again based on each BANK according to the BANK address of the client's reading and writing request after resolving; And above-mentioned a plurality of reading and writing request queues are disperseed to mail to concurrently write asynchronous converting unit; That is to say that will write request at one time based on the client of different B ANK gives concurrently and write asynchronous converting unit, make the client write request at interface with regard to parallelization.
It is similar that client's read request interface processing unit 211 and client write request interface processing unit 210; It also is provided with BANK address, row address and column address decoder; Above-mentioned demoder is used to parse client's read request address, and this address is corresponding with the respective memory unit of corresponding BANK.Also be provided with read request message queue and read request queue pretreatment unit in client's read request interface processing unit 211 with certain depth; " peak disappears " effect is played in the read request message queue when peak bandwidth appears in client's read request; And the read request queue pretreatment unit is used for read request is resequenced by the input sequence of read request, makes the client can directly use the data of reading.Specific practice is; Through being set, first, second two covers pointer indicates the read-out position of read request message queue in client's read request interface processing unit and the writing position in the read request pretreatment unit respectively; This first, second pointer is responsible for control by reading client; As read pointer just can add 1 after reading the corresponding data block of read request, and the indication next one is treated reading location, and the read data of other positions if the corresponding read data in this position is not ready for is because out of order execution and ready words; Read the client and still can not read this position data, be ready to up to this position data.
In the actual system, the client clock territory is different with the DDR clock zone usually, and generally speaking, DDR adopts very high clock to obtain higher performance, so client's reading and writing request must have asynchronous transfer process before getting into the processing of DDR clock zone; The asynchronous converting unit 212 of the request of writing is carried out asynchronous conversion with common " making a call to 2 claps " mode of asynchronous conversion 213 employings of read request, and DDR clock zone and client clock territory are complementary;
Write request arbitration unit 214 and determine respectively that with read request arbitration unit 215 client writes, the priority ranking of read request; According to the client request of the demand decision limit priority of bandwidth is processed earlier; Write request arbitration unit 214 and respectively a plurality of reading and writing requests in the reading and writing request queue of each BANK are arbitrated, and generate a plurality of reading and writing buffer queues according to priority orders and be buffered in the reading and writing buffer queue unit 217,216 with read request arbitration unit 215;
Write buffer queue 216 with read buffer queue 217 be write, the read command pipeline, have the function of first in first out; Because above-mentioned asynchronous conversion and arbitration meeting certain processing time of loss; And follow-up BC control module unit 218 is very fast with MC control module unit 219 processing speeds, can cause BC control module unit 218 and MC control module unit 219 often to be in like this and not ask manageable " hunger " state; Write buffer queue 216 and read buffer queue 217 and can guarantee that the request number of unit 218 and unit 219 is abundant.
BC control module 218 is used to produce all request commands in the single BANK body of DDR, and Fig. 3 is the workflow diagram of BC control module 218, and its step is following:
Step 310: whether inspection has the reading and writing request, if the reading and writing request is arranged, goes to step 311, otherwise returns the beginning idle condition;
Step 311: whether page or leaf hits in inspection reading and writing request, directly goes to step 317 if page or leaf hits, otherwise goes to step 312;
Step 312: whether the corresponding BANK of inspection reading and writing request closes, and goes to if just closed
Step 313: generate charge command for the first time;
Whether step 314: whether the inspection charge protection time satisfies, and goes to step 315 if satisfied, satisfy otherwise continue the inspection charge protection time;
Step 315: generate activation command;
Whether step 316: whether inspection activates guard time satisfied, goes to step 317 if satisfied, satisfy otherwise continue inspection activation guard time;
Step 317: generate the reading and writing order;
Step 318: whether inspection has new reading and writing request, if there is new reading and writing request to go to step 311, otherwise goes to step 319;
Step 319: check that being activated to of this BANK close minimum guard time and whether satisfy, go to step 320 if satisfy; Otherwise go to step 318;
Step 320: generate charge command for the second time, this charge command is accomplished " closing page or leaf " function, initiatively closes BANK, and purpose is in order to save next time shut-in time of same page reading and writing request not with BANK.
Whether step 321: whether the inspection charge protection time satisfies, and goes to end step if satisfied, satisfy otherwise continue the inspection charge protection time.
Each BC control module 218 is parallel carries out above-mentioned flow process simultaneously, if client's reading and writing request can be assigned to different BANK preferably, client's reading and writing request almost can walk abreast and resolved so, has greatly reduced wait blocking time.
The order that BC control module 218 generates is not directly to give the DDR command line; So the order that BC control module 218 sends can not carried out immediately, and need MC main control unit unit 219 to gather the order of each BANK and consider refresh command after produce the DDR order and give DDR command line by unit 219.
Unit 219 exectorial priority ranking are from high to low successively: refresh command, read write command, activation command, charge command, and the load configurations order only just can be used at the DDR initial phase, and normal work stage is not considered.MC main control unit unit 219 is not when having refresh command; Carry out the reading and writing order successively by the BANK order; Guaranteeing under the DDR guardtime parameter condition; Activation command and charge command are filled in the idle slit of command line, and activation command and charge command are like being hidden in the effective transmission window of data bus.
The read-write of DDR is switched frequently also can bring very big data bus loss; As write to switch to and read; Write burst and must wait on WTR cycle (time parameter of the DDR) command line after last data and read command could occur, read command must be waited for again and just occur the data of reading on CL cycle (time parameter of DDR) the DDR data bus afterwards; Read to switch to when writing, the conversion space of 1 clock period also must be arranged on the data bus.Therefore reducing unnecessary read-write switching is the important behave that improves the DDR bus efficiency; MC main control unit unit 219 is as ACTIVE CONTROL side among the present invention; With each BC control module 218 Collaborative Control binding reading and writing order; The concrete practice is as shown in Figure 4; Be provided with the collaborative status unit of MC positioning indicator and MC in the MC main control unit 219; This MC positioning indicator has to be write 410, write transition 411, reads 412, reads transition 413, refreshes protection 414 and refresh protection and remove 415 6 kinds of state Warning Marks, is provided with the collaborative status unit of BC in the BC control module 218 and to each reading and writing request one BC positioning indicator is set all, and this BC positioning indicator has write gate 420, write and read transition 421, read gate 422, read and write transition 423, refresh 424 and refresh 425 6 kinds of state Warning Marks of protection;
When sending to DRAM, MC main control unit 219 writes when request; The Status Flag of its positioning indicator is set to write 410; Simultaneously the collaborative status unit of MC sends to the collaborative status unit of BC and writes collaborative indication, and the Status Flag of the collaborative status unit BC positioning indicator of BC is set to write gate 420, and gating whole write buffer queue 216; Close whole buffer queues 217 of reading; This moment, MC main control unit 219 can only respond the request of writing writing in the time period of configuration, did not handle read request, write the time period finish after the Status Flag of MC positioning indicator be set to write transition 411; After each was write request and sends, the Status Flag of this BC positioning indicator is set to write read transition 421;
When the Status Flag of MC positioning indicator when writing transition 411; The collaborative status unit of MC sends to the collaborative status unit of BC and writes the collaborative indication of transition; The Status Flag of the collaborative status unit BC positioning indicator of BC is set to write reads transition 421, and the remaining buffer queue of writing of gating, closes whole buffer queues of reading; Wait all remaining writing after request all is processed; MC main control unit 219 sends read request to DRAM, and its Status Flag is set to read 412, and the Status Flag of all BC positioning indicators all is set to read 422;
When the Status Flag of MC positioning indicator when reading 412; The collaborative status unit of MC sends to the collaborative status unit of BC and reads collaborative indication, and the Status Flag of the collaborative status unit BC positioning indicator of BC is set to read 422, and gating whole read buffer queue 217; Close whole buffer queues 216 of writing; This moment, the MC main control unit 219 can only respond read request in the read time section of configuration, processing write requests not, and the Status Flag of MC positioning indicator was set to read transition 413 after the read time section finished; After each read request was sent, the Status Flag of this BC positioning indicator is set to read write transition 423;
When the Status Flag of MC positioning indicator when reading transition 413; The collaborative status unit of MC sends to the collaborative status unit of BC and reads the collaborative indication of transition; The collaborative status unit of BC is write transition 423 with the Status Flag of BC positioning indicator for reading; Wait after all remaining read requests all are processed, the Status Flag of MC positioning indicator is set to write 410, and the Status Flag of all BC positioning indicators all is set to write gate 420.
When MC main control unit 219 when DRAM sends read request; The Status Flag of its positioning indicator is set to read 412; Simultaneously the collaborative status unit of MC sends to the collaborative status unit of BC and reads collaborative indication, and the Status Flag of the collaborative status unit BC positioning indicator of BC is set to read gate 422, and gating whole read buffer queue 217; Close whole buffer queues 216 of writing; This moment, MC main control unit 219 can only respond read request writing in the time period of configuration, processing write requests not, and the Status Flag of MC positioning indicator was set to read transition 413 after the read time section finished; After each read request was sent, the Status Flag of this BC positioning indicator is set to read write transition 423;
When the Status Flag of MC positioning indicator when reading transition 413; The collaborative status unit of MC sends to the collaborative status unit of BC and reads the collaborative indication of transition; The Status Flag of the collaborative status unit BC positioning indicator of BC is set to read writes transition 423, and the remaining buffer queue of reading of gating, closes whole buffer queues of writing; Wait after all remaining read requests all are processed; MC main control unit 219 sends the request of writing to DRAM, and its Status Flag is set to write 410, and the Status Flag of all BC positioning indicators all is set to write 420;
When the Status Flag of MC positioning indicator when writing 410; The collaborative status unit of MC sends to the collaborative status unit of BC and writes collaborative indication, and the Status Flag of the collaborative status unit BC positioning indicator of BC is set to write 420, and gating whole write buffer queue 216; Close whole buffer queues 217 of reading; MC main control unit 219 can only respond the request of writing in the read time section of configuration at this moment, does not handle read request, and the Status Flag of MC positioning indicator was set to write transition 411 after the read time section finished; After each was write request and sends, the Status Flag of this BC positioning indicator is set to write read transition 421;
When the Status Flag of MC positioning indicator when writing transition 411; The collaborative status unit of MC sends to write to the collaborative status unit of BC reads collaborative indication; The collaborative status unit of BC is read transition 421 with the Status Flag of BC positioning indicator for writing; Wait all remaining writing after request all is processed, the Status Flag of MC positioning indicator is set to read 412, and the Status Flag of all BC positioning indicators all is set to read gate 422.
When the Status Flag of BC positioning indicator when refreshing 424; The Status Flag of BC positioning indicator is set to refresh protection 425; The collaborative status unit of BC sends the protection instruction to the collaborative status unit of MC simultaneously; MC main control unit unit 219 response refresh commands send protection releasing instruction etc. the collaborative status unit of refresh requests end back BC to the collaborative status unit of MC, and this moment, the MC main control unit can receive the reading and writing request.
Among the present invention refresh command being placed on read command and carrying out afterwards, is because read request is higher than the request of writing to the requirement of delaying time.Through above-mentioned 2 collaborative status unit collaborative works, can client's reading and writing request binding separately within a certain period of time be produced write the two or more syllables of a word together and connect the interpreting blueprints case, eliminate frequent switching and brought bandwidth lose; Though the way of order binding can be introduced certain response time-delay, control module had also correspondingly improved the response speed of client requests after bandwidth elevated.
During the DRAM of data volume once export greater than to(for) the data volume of client's reading and writing request; The present invention can cut client's reading and writing request; If the data volume that occurs one-time request in a large number has only the situation of 1BYTE; The present invention can reduce the data bit width of the DDR2 that selects for use, reduces loss bandwidth on the DDR2 bus, to satisfy the application of DRAM interface.Be provided with data partitioning unit in the MC main control unit; Whether this data partitioning unit is whether basis for estimation obtains the judged result to cutting apart this reading and writing requested data block greater than the base memory unit of DRAM with the size of a reading and writing requested data block of client; When judged result shows need cut apart this reading and writing requested data block the time; At first confirm the address boundary of DRAM burst block (data quantity transmitted); Calculate then and cut apart corresponding data block size and the start address of each request of back, and send the read-write requests after cutting apart to DRAM by the mode continuous of same page.
The present invention also provides the DRAM storage controlling method, may further comprise the steps:
A10, client's reading and writing request carried out address decoder after, be arranged in a plurality of reading and writing request queues again according to the BANK address, and the back is parallel synchronously sends with above-mentioned a plurality of reading and writing request queues based on each BANK based on each BANK;
The request queue of writing based on each BANK in this step generates through following steps:
A101, with the client who receives write request put into have certain configurable deep write the solicited message formation;
A102, the client that will write solicited message formation exit successively write request and carry out address resolution;
A103, the BANK address of writing request according to the back client of parsing rearrange a plurality of request queues of writing based on each BANK again with it, write respectively in the request pretreatment unit;
A104, a plurality of back synchronously walking abreast of request queue of writing based on each BANK are sent.
Read request queue based on each BANK generates through following steps:
A111, client's read request of receiving put into read request message queue with certain configurable deep;
A112, order are carried out address resolution with client's read request in read request message queue exit;
A113, it is rearranged a plurality of read request queue based on each BANK again according to the BANK address of resolving back client's read request; Write respectively in the read request pretreatment unit; In this step; The current read-out position of the first pointed read request message queue is set, the writing position of this read request of second pointed in the read request pretreatment unit is set, the read request corresponding with first pointer writes the relevant position in the read request pretreatment unit of second pointed;
A114, the back is parallel synchronously sends with a plurality of read request queue based on each BANK.
A20, respectively each is arbitrated based on a plurality of reading and writing requests in the reading and writing request queue of each BANK, and rank according to priority orders;
A30, according to each based on the reading and writing request in the reading and writing request queue of each BANK, generate separately reading and writing request command and activation command and/or precharge command respectively;
A40, the reading and writing request command is delivered to command line; And satisfying under the DRAM reading and writing prerequisite in protection time limit, insert the activation command and/or the precharge command of the reading and writing command request in other BANK reading and writing request queues before the reading and writing command request order in this BANK reading and writing request queue.
In the said method, MC main control unit and BC control module associated treatment, concrete implementation method is as previously mentioned.
During greater than DRAM interface data bit wide, this method can be cut client's reading and writing request for the data width of client's reading and writing request, and concrete implementation method as previously mentioned.
The effect of with an instantiation method provided by the invention being brought is below carried out detailed explanation.
This instantiation is, one group of client requests is W0/R0/W1/R1/W2/R2/W3/R3 sequentially, and wherein W0 representes the request of writing to BANK0, and R0 is the read request to BANK0, but read-write requests address same page not, the rest may be inferred for other.The sequential of DDR2 protection restriction is in the sequential chart 5: CL (CAS latent period) is 3T; Tras (being activated to the shut-in time) is 8T, and Trrd (being activated to activationary time) is 2T, and Twr (writing data to the duration of charging) is 3T; Twtr (writing data to the read command time) is 2T; Trcd (being activated to the read write command time) is 3T, and Trp (being charged to activationary time) is 3T, and T is the clock period.
Fig. 5 is the sequential chart by traditional control method, owing to do not support many BANK ping-pong operation and order binding, access command is progressively carried out according to the guardtime restriction of DRAM in order successively; As shown in Figure 5; One group of required instruction of client requests above accomplishing is 8 and activates ACT that 8 charging PRE write WR for 4; Read RD for 4, need 104T to accomplish above-mentioned 8 client requests altogether.
Fig. 6 adopts access control method access sequential chart of the present invention; Owing to support parallel ping-pong operation of BANK and order binding; Though number of instructions is the same among required instruction and Fig. 5, charging and activate the effective stage of data bus that all is hidden into, when only the write-read after the binding switches since the guardtime limitation loss 5T; Only need 42T just to accomplish all client requests altogether, improved the utilization factor of data bus greatly.
The present invention is not limited to above-mentioned preferred forms, and anyone should learn the structural change of under enlightenment of the present invention, making, and every have identical or close technical scheme with the present invention, all falls within protection scope of the present invention.
Claims (11)
1.DRAM storage controlling method is characterized in that may further comprise the steps:
A10, client's reading and writing request carried out address decoder after, be arranged in a plurality of reading and writing request queues again according to the BANK address, and the back is parallel synchronously sends with above-mentioned a plurality of reading and writing request queues based on each BANK based on each BANK;
A20, respectively each is arbitrated based on a plurality of reading and writing requests in the reading and writing request queue of each BANK, and rank according to priority orders;
A30, according to each based on the reading and writing request in the reading and writing request queue of each BANK; Generate separately reading and writing request command and activation command and precharge command respectively; Perhaps generate separately reading and writing request command and activation command respectively, perhaps generate separately reading and writing request command and precharge command respectively;
A40, the reading and writing request command is delivered to command line; And satisfying under the DRAM reading and writing prerequisite in protection time limit, insert the activation command and/or the precharge command of the reading and writing command request in other BANK reading and writing request queues before the reading and writing command request order in this BANK reading and writing request queue.
2. DRAM storage controlling method as claimed in claim 1 is characterized in that, the request queue of writing based on each BANK in the steps A 10 generates through following steps:
A101, with the client who receives write request put into have certain configurable deep write the solicited message formation;
A102, the client that will write solicited message formation exit successively write request and carry out address resolution;
A103, the BANK address of writing request according to the back client of parsing rearrange a plurality of request queues of writing based on each BANK again with it, write respectively in the request pretreatment unit;
A104, a plurality of back synchronously walking abreast of request queue of writing based on each BANK are sent.
3. DRAM storage controlling method as claimed in claim 1 is characterized in that, in the steps A 10, passes through following steps based on the read request queue of each BANK and generates:
A111, client's read request of receiving put into read request message queue with certain configurable deep;
A112, order are carried out address resolution with client's read request in read request message queue exit;
A113, it is rearranged a plurality of read request queue based on each BANK again according to the BANK address of resolving back client's read request; Write respectively in the read request pretreatment unit; In this step, the current read-out position of the first pointed read request message queue is set, the writing position of this read request of second pointed in the read request pretreatment unit is set; Read request that will be corresponding with first pointer writes the relevant position in the read request pretreatment unit of second pointed;
A114, the back is parallel synchronously sends with a plurality of read request queue based on each BANK.
4. like claim 1,2 or 3 described DRAM storage controlling methods, it is characterized in that, in steps A 40, read each BANK reading and writing request queue successively according to the current reading and writing solicited status sign that is sent to command line.
5. DRAM storage controlling method as claimed in claim 4; It is characterized in that; When the data width of a reading and writing request during greater than DRAM interface data bit wide; This reading and writing request msg is cut apart according to DRAM interface data bit wide, and, sent the reading and writing request after cutting apart to DRAM by the mode continuous of same page according to cutting apart corresponding size of data and the start address of each reading and writing request of back.
6.DRAM memory control device; This DRAM is made up of a plurality of BANK; Be provided with a plurality of basic units of storage of being confirmed by row address and column address respectively among each BANK, described memory control device comprises some reading and writing request interface processing units, asynchronous converting unit; With BANK number corresponding reading and writing request queue arbitration unit and BANK control module and reading and writing buffer queue unit and MC main control unit, it is characterized in that:
Be respectively equipped with reading and writing request address demoder and reading and writing request queue pretreatment unit in the described reading and writing request interface processing unit; BANK address, row address and column address decoder parse client's reading and writing request address; This address is corresponding with the corresponding basic unit of storage of corresponding BANK; Described reading and writing request queue pretreatment unit is arranged in a plurality of reading and writing request queues based on each BANK again according to the BANK address of the client's reading and writing request after resolving, and with above-mentioned a plurality of reading and writing request queues parallel reading and writing request queue arbitration units that mail to after asynchronous converting unit is synchronous based on each BANK;
Described reading and writing request queue arbitration buffer cell is arbitrated a plurality of reading and writing requests in the reading and writing request queue of each BANK respectively, and generates a plurality of reading and writing buffer queues according to priority orders and be buffered in the reading and writing buffer queue unit;
Described BANK control module; According to the reading and writing request in each BANK reading and writing request queue in the reading and writing buffer queue unit; Generate separately reading and writing request command and activation command and precharge command respectively; Perhaps generate separately reading and writing request command and activation command or precharge command respectively, above-mentioned reading and writing request command and activation command, the parallel MC main control unit that mails to of precharge command;
The MC main control unit; The reading and writing request command of receiving is delivered to command line; And satisfying under the DRAM reading and writing prerequisite in protection time limit, insert the activation command and/or the precharge command of the reading and writing command request in other BANK reading and writing request queues before the reading and writing command request order in this BANK reading and writing request queue.
7. DRAM memory control device as claimed in claim 6 is characterized in that also being provided with the solicited message queue unit with certain configurable deep in the described reading and writing request interface processing unit.
8. DRAM memory control device as claimed in claim 7; It is characterized in that being provided with first, second pointer in client's read request interface processing unit, indicate the read-out position of read request message queue in client's read request interface processing unit and the writing position in the read request pretreatment unit respectively.
9. DRAM memory control device as claimed in claim 8; It is characterized in that being provided with in the MC main control unit the collaborative status unit of MC positioning indicator and MC; This MC positioning indicator has to be write, writes transition, read, read transition, refreshes protection and refresh six kinds of state Warning Marks of protection releasing; Be provided with the collaborative status unit of BC in the BC control module and to each reading and writing request one BC positioning indicator be set all, this BC positioning indicator has write gate, write and read transition, read gate, read and write transition, refresh and refresh six kinds of state Warning Marks of protection;
Write when request when the MC main control unit sends to DRAM, the Status Flag of its positioning indicator is set to write, and the collaborative status unit of MC sends to the collaborative status unit of BC and writes collaborative indication simultaneously; The Status Flag of the collaborative status unit BC positioning indicator of BC is set to write gate; And gating whole write buffer queue, close whole buffer queues of reading, this moment, the MC main control unit can only respond the request of writing writing in the time period of configuration; Do not handle read request; Write the time period finish after the Status Flag of MC positioning indicator be set to write transition, after each was write request and sends, the Status Flag of this BC positioning indicator is set to write read transition;
When the Status Flag of MC positioning indicator when writing transition; The collaborative status unit of MC sends to the collaborative status unit of BC and writes the collaborative indication of transition; The Status Flag of the collaborative status unit BC positioning indicator of BC is set to write reads transition, and the remaining buffer queue of writing of gating, closes whole buffer queues of reading; Wait all remaining writing after request all handles; The MC main control unit sends read request to DRAM, and its Status Flag is set to read, and the Status Flag of all BC positioning indicators all is set to read;
When the Status Flag of MC positioning indicator when reading; The collaborative status unit of MC sends to the collaborative status unit of BC and reads collaborative indication, and the Status Flag of the collaborative status unit BC positioning indicator of BC is set to read, and gating whole read buffer queue; Close whole buffer queues of writing; This moment, the MC main control unit can only respond read request in the read time section of configuration, processing write requests not, and the Status Flag of MC positioning indicator was set to read transition after the read time section finished; After each read request was sent, the Status Flag of this BC positioning indicator is set to read write transition;
When the Status Flag of MC positioning indicator when reading transition; The collaborative status unit of MC sends to the collaborative status unit of BC and reads the collaborative indication of transition; The Status Flag of the collaborative status unit BC positioning indicator of BC is set to read writes transition; Wait after all remaining read requests all handle, the Status Flag of MC positioning indicator is set to write, and the Status Flag of all BC positioning indicators all is set to write gate;
When the Status Flag of BC positioning indicator when refreshing; The Status Flag of BC positioning indicator is set to refresh protection; Simultaneously the collaborative status unit of BC sends the protection instruction to the collaborative status unit of MC, and MC main control unit cell response refresh command is after waiting refresh command to carry out to finish; The collaborative status unit of BC sends to the collaborative status unit of MC and refreshes protection releasing instruction, and the MC main control unit was in and received the reading and writing solicited status this moment.
10. DRAM memory control device as claimed in claim 8; It is characterized in that; Be provided with the collaborative status unit of MC positioning indicator and MC in the MC main control unit; This MC positioning indicator has to be write, writes transition, read, read transition, refreshes protection and refresh six kinds of state Warning Marks of protection releasing; Be provided with the collaborative status unit of BC in the BC control module and to each reading and writing request one BC positioning indicator be set all, this BC positioning indicator has write gate, write and read transition, read gate, read and write transition, refresh and refresh six kinds of state Warning Marks of protection;
When the MC main control unit when DRAM sends read request, the Status Flag of its positioning indicator is set to read, simultaneously the collaborative status unit of MC sends to the collaborative status unit of BC and reads collaborative indication; The Status Flag of the collaborative status unit BC positioning indicator of BC is set to read gate; And gating whole read buffer queue, close whole buffer queues of writing, this moment, the MC main control unit can only respond read request in the read time section of configuration; Processing write requests not; The Status Flag of MC positioning indicator was set to read transition after the read time section finished, and after each read request was sent, the Status Flag of this BC positioning indicator is set to read write transition;
When the Status Flag of MC positioning indicator when reading transition; The collaborative status unit of MC sends to the collaborative status unit of BC and reads the collaborative indication of transition; The Status Flag of the collaborative status unit BC positioning indicator of BC is set to read writes transition, and the remaining buffer queue of reading of gating, closes whole buffer queues of writing; Wait after all remaining read requests all handle; The MC main control unit sends the request of writing to DRAM, and its Status Flag is set to write, and the Status Flag of all BC positioning indicators all is set to write;
When the Status Flag of MC positioning indicator when writing; The collaborative status unit of MC sends to the collaborative status unit of BC and writes collaborative indication, and the Status Flag of the collaborative status unit BC positioning indicator of BC is set to write, and gating whole write buffer queue; Close whole buffer queues of reading; This moment, the MC main control unit can only respond the request of writing writing in the time period of configuration, did not handle read request, write the time period finish after the Status Flag of MC positioning indicator be set to write transition; After each was write request and sends, the Status Flag of this BC positioning indicator is set to write read transition;
When the Status Flag of MC positioning indicator when writing transition; The collaborative status unit of MC sends to the collaborative status unit of BC and writes the collaborative indication of transition; The Status Flag of the collaborative status unit BC positioning indicator of BC is set to write reads transition; Wait all remaining writing after request all handles, the Status Flag of MC positioning indicator is set to read, and the Status Flag of all BC positioning indicators all is set to read gate;
When the Status Flag of BC positioning indicator when refreshing; The Status Flag of BC positioning indicator is set to refresh protection; Simultaneously the collaborative status unit of BC sends the protection instruction to the collaborative status unit of MC, and MC main control unit cell response refresh command is after waiting refresh command to carry out to finish; The collaborative status unit of BC sends to the collaborative status unit of MC and refreshes protection releasing instruction, and the MC main control unit was in and received the reading and writing solicited status this moment.
11. like claim 9 or 10 described DRAM memory control devices; It is characterized in that also comprising data partitioning unit; Whether this data partitioning unit is whether basis for estimation obtains the judged result to cutting apart this reading and writing requested data block greater than DRAM interface data bit wide with the data width of a reading and writing request of client; When judged result shows need cut apart this reading and writing requested data block the time; This reading and writing request msg is cut apart according to DRAM interface data bit wide, calculated and cut apart corresponding data block size and the start address of each request of back, and send the read-write requests after cutting apart to DRAM by the mode continuous of same page.
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| CN102855195B (en) * | 2011-06-30 | 2015-05-27 | 重庆重邮信科通信技术有限公司 | Second generation low power double-rate storage controller and access command processing method |
| CN102436429A (en) * | 2011-11-14 | 2012-05-02 | 盛科网络（苏州）有限公司 | Dynamic random access memory (DRAM) and method for improving DRAM data access bandwidth |
| US8792294B2 (en) | 2012-01-09 | 2014-07-29 | Mediatek Inc. | DRAM and access and operating method thereof |
| CN105912270B (en) * | 2016-04-12 | 2019-01-18 | 上海交通大学 | A kind of access request resolver and method towards PM |
| CN108108148B (en) * | 2016-11-24 | 2021-11-16 | 舒尔电子(苏州)有限公司 | Data processing method and device |
| CN106874222B (en) * | 2016-12-26 | 2020-12-15 | 深圳市紫光同创电子有限公司 | Instruction delay control method, controller and memory |
| JP6883764B2 (en) * | 2018-09-28 | 2021-06-09 | パナソニックＩｐマネジメント株式会社 | Command control system, vehicle, command control method and program |
| CN109582615B (en) * | 2018-11-27 | 2022-04-12 | 浙江双成电气有限公司 | DDR3 control system |
| JP6894459B2 (en) * | 2019-02-25 | 2021-06-30 | 華邦電子股▲ふん▼有限公司Ｗｉｎｂｏｎｄ Ｅｌｅｃｔｒｏｎｉｃｓ Ｃｏｒｐ． | Pseudo-static random access memory and how it works |
| CN111273888B (en) * | 2020-03-06 | 2022-03-11 | 中国人民解放军国防科技大学 | Method and device for maintaining order of address-related read-write queue |
| CN112069095B (en) * | 2020-09-09 | 2022-01-28 | 北京锐马视讯科技有限公司 | DDR3 read-write transmission method and device |
| WO2022174367A1 (en) * | 2021-02-18 | 2022-08-25 | Micron Technology, Inc. | Improved implicit ordered command handling |
| CN115148253B (en) * | 2021-03-31 | 2024-05-17 | 长鑫存储技术有限公司 | Memory circuit, memory precharge control method and apparatus |
| US11670349B2 (en) | 2021-03-31 | 2023-06-06 | Changxin Memory Technologies, Inc. | Memory circuit, memory precharge control method and device |
| US11705167B2 (en) | 2021-03-31 | 2023-07-18 | Changxin Memory Technologies, Inc. | Memory circuit, method and device for controlling pre-charging of memory |
| CN116627857B (en) * | 2023-05-25 | 2023-11-24 | 合芯科技有限公司 | Processor out-of-core cache model and simulation method |
| CN117012266A (en) * | 2023-06-30 | 2023-11-07 | 珠海妙存科技有限公司 | Performance test method and device based on EMMC (EMMC management computer) and storage medium thereof |
| CN117009088A (en) * | 2023-09-25 | 2023-11-07 | 上海芯高峰微电子有限公司 | Memory management method, memory management device, chip, electronic equipment and readable storage medium |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5630096A (en) * | 1995-05-10 | 1997-05-13 | Microunity Systems Engineering, Inc. | Controller for a synchronous DRAM that maximizes throughput by allowing memory requests and commands to be issued out of order |
| US5950219A (en) * | 1996-05-02 | 1999-09-07 | Cirrus Logic, Inc. | Memory banks with pipelined addressing and priority acknowledging and systems and methods using the same |
| US6615326B1 (en) * | 2001-11-09 | 2003-09-02 | Lsi Logic Corporation | Methods and structure for sequencing of activation commands in a high-performance DDR SDRAM memory controller |
| US7069399B2 (en) * | 2003-01-15 | 2006-06-27 | Via Technologies Inc. | Method and related apparatus for reordering access requests used to access main memory of a data processing system |
| CN101118523B (en) * | 2006-08-01 | 2011-10-19 | 飞思卡尔半导体公司 | Memory accessing control device and method thereof, and memory accessing controller and method thereof |
| CN101216751B (en) * | 2008-01-21 | 2010-07-14 | 戴葵 | DRAM device with data handling capacity based on distributed memory structure |
| CN101257626B (en) * | 2008-01-31 | 2010-11-03 | 炬力集成电路设计有限公司 | Method, apparatus for access DRAM and medium player |
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