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CN101740392A - LDMOS (Laterally Diffused Metal Oxide Semiconductor) transistor, semiconductor device and manufacture method thereof - Google Patents

LDMOS (Laterally Diffused Metal Oxide Semiconductor) transistor, semiconductor device and manufacture method thereof Download PDF

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Publication number
CN101740392A
CN101740392A CN200810203538A CN200810203538A CN101740392A CN 101740392 A CN101740392 A CN 101740392A CN 200810203538 A CN200810203538 A CN 200810203538A CN 200810203538 A CN200810203538 A CN 200810203538A CN 101740392 A CN101740392 A CN 101740392A
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dopant well
doped region
ion doped
type
dark
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CN101740392B (en
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郑大燮
王东立
陈德艳
陈良成
崔崟
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Semiconductor Manufacturing International Shanghai Corp
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Semiconductor Manufacturing International Shanghai Corp
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Abstract

The invention relates to an LDMOS (Laterally Diffused Metal Oxide Semiconductor) transistor, a semiconductor device and a manufacture method thereof, wherein the manufacture method of the LDMOS transistor comprises the steps of: forming a deep-doped well in a semiconductor substrate; forming an isolation structure in the deep-doped well, wherein the isolation structure is arranged between a source electrode and a drain electrode and is close to the drain electrode; forming a first ion doping area in the deep-doped well; and forming a second ion doping area in the deep-doped well, wherein a space is reserved between the first ion doping area and the second ion doping area. By forming the deep-doped well which has the same channel conduction type with the LDMOS transistor to be formed in the semiconductor substrate, the invention can obtain higher breakdown voltage.

Description

Ldmos transistor, semiconductor device and manufacture method thereof
Technical field
The present invention relates to technical field of semiconductors, particularly ldmos transistor, semiconductor device and manufacture method thereof with ldmos transistor.
Background technology
In the development of power integrated circuit, for the single-chip processing procedure that power switch and control circuit is combined and develop, especially at present be used to make horizontal secondary diffused metal oxide emiconductor (the lateral double diffusion MOS of monolithic integrated circuit, LDMOS) processing procedure is a main flow trend.The LDMOS processing procedure is to carry out planar diffusion (planar diffusion) in the surface of semiconductor substrate so that form horizontal main current path, because LDMOS is with the manufacturing of typical IC processing procedure, therefore control circuit and LDMOS can be incorporated on the single-chip power supply IC, the LDMOS processing procedure adopts surface field reduction (reduced surface electric field, RESURE) technology and low thickness extension (EPI) or N type well region (N-well) can reach the target of high voltage and low conduction impedance.
The LDMOS device is a kind of FET device (FET) that is similar to traditional F ET device, all be included in and form a pair of source/drain region of being separated in the Semiconductor substrate by channel region, and form gate electrode in the channel region top successively, yet, the LDMOS device is different with traditional F ET device is that pair of source territory in the traditional FET device is made with gate electrode symmetrical, and the drain region in the LDMOS device forms further from gate electrode than the source region, and the drain region is formed at simultaneously in order in the dopant well (having and the drain region identical polar) of separating channel region and drain region.
Prior art discloses a kind of LDMOS of having integrated circuit technique, and concrete structure comprises as shown in Figure 1: the N-trap 112 of silicon is by border 113 and 111 insulation of P-trap.P-trap 111 is extended downwards by the surface, top and comprises N+ zone 117, and with 117 and the interface of P-trap 112 between distance L 110 determine this raceway groove; N+ zone 117 provides source electrode 125 and has drained 130 both contact areas, along with applying of polysilicon gate 116 (below the gate oxide that is not represented for clarity) positive voltage VG, electric current can be passed raceway groove and be flowed into N+117, P-trap 111 and N-trap 112 by source electrode 125, and is gathered in N+117 by drain electrode 130; Metal Contact window 115 gives short circuit to carry out ohmic contact with N+ zone 117 with P+ zone 119, so will allow source current by P-trap 111, and is cooled off by fin (heat sink).Most LDMOS structure builds on the substrate with one or more other device architectures, and in high-voltage applications, the effect of oxide in field 14 provides insulation and by reducing electric field density to improve puncture voltage.
In being 200510001857.6 Chinese patent application, application number can also find more information relevant with technique scheme.
Prior art also discloses a kind of p-LDMOS structure, as shown in Figure 2, comprises the dark n type dopant well 201 that is positioned on the Semiconductor substrate, wherein is formed with fleet plough groove isolation structure 202, N-zone 203, P-zone 204, source electrode 208 and drains 209; Be positioned at the gate dielectric layer 205 on the Semiconductor substrate; Polysilicon gate 206 and the side wall 207 that is positioned at polysilicon gate 206 both sides.Along with applying of positive voltage VG on the polysilicon gate 206, electric current can be passed raceway groove and be flowed into N-zone 203, dark n type dopant well 201, P-zone 204 by source electrode 208, and is gathered in drain electrode 209.
In this technical scheme, 204 drift regions, P-zone as drain electrode 209, length of effective channel is among Fig. 2 shown in the DLL, under grid voltage, form back-biased diode between P-zone 204 and the P-zone 204, depletion region is narrower, and the withstand voltage degree of ldmos transistor is lower, causes can occurring snap back (snapback) phenomenon very soon in the I-V characteristic curve of ldmos transistor; And, form in 204 processes of P-zone, if mask has deviation, do not surround fleet plough groove isolation structure 202 fully such as P-zone 204, cause threshold voltage too high and influence is actual uses easily; Simultaneously, form P-zone 204 and need inject separately and independent mask plate, cost is higher.
Summary of the invention
The problem that the present invention solves provides a kind of ldmos transistor, has the semiconductor device and the manufacture method thereof of ldmos transistor, with the withstand voltage degree that improves ldmos transistor with reduce cost.
For addressing the above problem, the invention provides a kind of manufacture method of ldmos transistor, comprise the steps: to provide Semiconductor substrate; In described Semiconductor substrate, form dark dopant well, the conduction type of described dark dopant well is identical with the channel type of ldmos transistor to be formed in this dark dopant well, and ldmos transistor to be formed has source electrode, drain electrode and gate dielectric layer in described this dark dopant well; Form isolation structure in described dark dopant well, described isolation structure is between source electrode and drain electrode and near drain electrode; Form first ion doped region in described dark dopant well, the conduction type of described first ion doped region is identical with the channel type of ldmos transistor; The degree of depth of described first ion doped region greater than isolation structure bottom and cover drain electrode and cover isolation structure at least be trapped among subregion corresponding in the described dark dopant well outward; Form second ion doped region in described dark dopant well, the conduction type of described second ion doped region is opposite with the channel type of ldmos transistor; Described second ion doped region covers source electrode and covering gate dielectric layer corresponding subregion in described dark dopant well at least; Have between described second ion doped region and first ion doped region at interval.
Comprise that also annealing steps, described annealing temperature are 800 to 1100 ℃ after forming described dark dopant well, annealing atmosphere is N 2, annealing time is 1 to 3 hour.
Described first ion doped region injects by ion and forms, and described ion injects and the dopant well of voltage device carries out simultaneously.
The mask pattern that forms the ion mask pattern that injects and the dopant well that forms voltage device of described first ion doped region is positioned on the same mask.
The channel type of described ldmos transistor is the n type, the mask pattern that forms described first ion doped region with form in the mask pattern of n type dopant well of voltage device be positioned on the same mask, the mask pattern that forms described second ion doped region with form in the mask pattern of p type dopant well of voltage device be positioned on the same mask, described dark dopant well is the n type.
The channel type of described ldmos transistor is the p type, the figure that forms described first ion doped region with form in the mask pattern of p type dopant well of voltage device be positioned on the same mask, the mask pattern that forms described second ion doped region with form in the mask pattern of n type dopant well of voltage device be positioned on the same mask, described dark dopant well is the p type.
Also comprised forming dark n type dopant well step before forming described dark dopant well, the described dark n type dopant well degree of depth is greater than dark dopant well.
The present invention also provides a kind of ldmos transistor, comprising: the source electrode, drain electrode and the gate dielectric layer that are positioned at Semiconductor substrate; Isolation structure is between source electrode and drain electrode and near drain electrode; First ion doped region is positioned at described Semiconductor substrate, and the conduction type of described first ion doped region is identical with the conduction type of the raceway groove of ldmos transistor; The degree of depth of described first ion doped region greater than isolation structure bottom and cover drain electrode and cover isolation structure at least be trapped among subregion corresponding in the described Semiconductor substrate outward; Second ion doped region is positioned at described Semiconductor substrate, the conductivity type opposite of the conduction type of described second ion doped region and the raceway groove of ldmos transistor; Described second ion doped region covers source electrode and covering gate dielectric layer corresponding subregion in described Semiconductor substrate at least; Have between described second ion doped region and first ion doped region at interval; Also comprise: dark dopant well, the conduction type of described dark dopant well is identical with the conduction type of the raceway groove of ldmos transistor, and covers the subregion of described first ion doped region, second ion doped region and gate dielectric layer correspondence in described Semiconductor substrate.
Also comprise the dark n type dopant well that is positioned at Semiconductor substrate, the described dark n type dopant well degree of depth is greater than dark dopant well.
The present invention also provides a kind of manufacture method with semiconductor device of ldmos transistor, comprising: Semiconductor substrate is provided, and described Semiconductor substrate contains high tension apparatus zone and middle voltage device zone; In the Semiconductor substrate in high tension apparatus zone, form dark dopant well, the conduction type of described dark dopant well is identical with the channel type of ldmos transistor to be formed in this dark dopant well, and ldmos transistor to be formed has source electrode, drain electrode and gate dielectric layer in described this dark dopant well; Form isolation structure in described dark dopant well, described isolation structure is between source electrode and drain electrode and near drain electrode; Form first ion doped region in described dark dopant well, the conduction type of described first ion doped region is identical with the channel type of described ldmos transistor; The degree of depth of described first ion doped region is greater than the isolation structure bottom; And the outer subregion that is trapped among correspondence in the described dark dopant well that covers drain electrode and cover isolation structure at least; Form second ion doped region in described dark dopant well, the conduction type of described second ion doped region is opposite with the channel type of described ldmos transistor; Described second ion doped region covers source electrode and covering gate dielectric layer corresponding subregion in described dark dopant well at least; Have between described second ion doped region and first ion doped region at interval.
Comprise that also annealing steps, described annealing temperature are 800 to 1100 ℃ after forming described dark dopant well, annealing atmosphere is N 2, annealing time is 1 to 3 hour.
Described first ion doped region injects by ion and forms, and described ion injects and the dopant well of voltage device carries out simultaneously.
The mask pattern that forms the ion mask pattern that injects and the dopant well that forms voltage device of described first ion doped region is positioned on the same mask.
The channel type of described ldmos transistor is the n type, the mask pattern that forms described first ion doped region with form in the mask pattern of n type dopant well of voltage device be positioned on the same mask, the mask pattern that forms described second ion doped region with form in the mask pattern of p type dopant well of voltage device be positioned on the same mask, described dark dopant well is the n type.
The channel type of described ldmos transistor is the p type, the figure that forms described first ion doped region with form in the mask pattern of p type dopant well of voltage device be positioned on the same mask, the mask pattern that forms described second ion doped region with form in the mask pattern of n type dopant well of voltage device be positioned on the same mask, described dark dopant well is the p type.
Also comprised forming dark n type dopant well step before forming described dark dopant well, the described dark n type dopant well degree of depth is greater than dark dopant well.
A kind of semiconductor device of aforesaid manufacturing.
Compared with prior art, the technical program has the following advantages: by form the identical dark dopant well of channel type with ldmos transistor to be formed in Semiconductor substrate, in dark the doping, form first ion doped region and second ion doped region of isolating mutually then, described first ion doped region is identical with channel type, second ion doped region and channel type are opposite, the raceway groove of ldmos transistor is second corresponding under the gate dielectric layer ion doped region, raceway groove is shorter, under grid voltage, form back-biased diode between dark dopant well and first ion doped region and second ion doped region, this district exhausts entirely before puncturing, can obtain higher puncture voltage, be that snap back phenomenon in the I-V curve of ldmos transistor moves to right, improve the withstand voltage degree of ldmos transistor; Simultaneously, by increasing the doping content of first ion doped region, can reduce opening resistor (rdson); And, because first ion doped region that forms is identical with the conduction type of dark dopant well, even because when forming first ion doped region, mask in the photoetching process has deviation, do not surround isolation structure fully even do not surround the isolation structure part such as first ion doped region, the too high and actual problem of using of influence of the threshold value that can not cause prior art;
The technical program is also injected to inject with the dopant well ion that forms voltage device by the ion that forms first ion doped region and is carried out simultaneously, avoids in the prior art the extra injection process that increases in order to form the drift region, has reduced the technology cost;
The technical program also is arranged on the same mask by the mask pattern of the ion that will form described first ion doped region mask pattern that injects and the dopant well that forms voltage device, avoid in the prior art the extra mask plate that increases in order to form the drift region, can carry out simultaneously with the dopant well in voltage device zone in the formation simultaneously, reduced the cycle period of technology cost and product;
The technical program is annealed into N by being 800 to 1100 ℃ in temperature after forming dark dopant well 2Annealing is 1 to 3 hour under the atmosphere, makes the ion distribution in it more even, and can repair the damage in the injection process.
Description of drawings
Fig. 1 is the structural representation of ldmos transistor of the formation of prior art;
Fig. 2 is the structural representation of the another kind of ldmos transistor of prior art;
Fig. 3 is the schematic flow sheet of formation ldmos transistor of the present invention;
Fig. 4 is the transistorized schematic flow sheet of formation p-LDMOS of one embodiment of the present of invention;
Fig. 5 to 8 is transistorized structural representations of formation p-LDMOS of one embodiment of the present of invention;
Fig. 9 is the transistorized I-V characteristic curve of p-LDMOS that adopts structure shown in Figure 2 of the prior art;
Figure 10 is the transistorized I-V characteristic curve of p-LDMOS that adopts method of the present invention to form;
Figure 11 is the transistorized schematic flow sheet of formation n-LDMOS of one embodiment of the present of invention;
Figure 12 to 15 is transistorized structural representations of formation n-LDMOS of one embodiment of the present of invention;
Figure 16 is the transistorized I-V characteristic curve of n-LDMOS that adopts structure shown in Figure 2 of the prior art;
Figure 17 is the transistorized I-V characteristic curve of n-LDMOS that the method for employing forms;
Figure 18 is the structural representation that the formation of one embodiment of the present of invention has the semiconductor device of ldmos transistor.
Embodiment
The present invention is by forming the identical dark dopant well of channel type with ldmos transistor to be formed in Semiconductor substrate, in dark the doping, form first ion doped region and second ion doped region of isolating mutually then, described first ion doped region is identical with channel type, second ion doped region and channel type are opposite, the raceway groove of ldmos transistor is second corresponding under the gate dielectric layer ion doped region, raceway groove is shorter, under grid voltage, form back-biased diode between dark dopant well and first ion doped region and second ion doped region, this district exhausts entirely before puncturing, can obtain higher puncture voltage, be that snap back phenomenon in the I-V curve of ldmos transistor moves to right, improve the withstand voltage degree of ldmos transistor; Simultaneously, by increasing the doping content of first ion doped region, can reduce opening resistor (Rdson); And, because first ion doped region that forms is identical with the conduction type of dark dopant well, even because when forming first ion doped region, mask in the photoetching process has deviation, do not surround isolation structure fully even do not surround the isolation structure part such as first ion doped region, the too high and actual problem of using of influence of the threshold value that can not cause prior art.
The present invention also injects to inject with the dopant well ion that forms voltage device by the ion that forms first ion doped region and carries out simultaneously, avoids in the prior art the extra injection process that increases in order to form the drift region, has reduced the technology cost.
The present invention also is arranged on the same mask by the mask pattern of the ion that will form described first ion doped region mask pattern that injects and the dopant well that forms voltage device, avoid in the prior art the extra mask plate that increases in order to form the drift region, can carry out simultaneously with the dopant well in voltage device zone in the formation simultaneously, reduced the cycle period of technology cost and product.
The present invention is annealed into N by being 800 to 1100 ℃ in temperature after forming dark dopant well 2Annealing is 1 to 3 hour under the atmosphere, makes the ion distribution in it more even, and can repair the damage in the injection process.
Below describe specific embodiment in detail by the foundation accompanying drawing, above-mentioned purpose and advantage of the present invention will be clearer:
The present invention at first provides a kind of manufacture method of ldmos transistor, with reference to Fig. 3, comprise: execution in step S11, Semiconductor substrate is provided, be formed with dark dopant well in the described Semiconductor substrate, the conduction type of described dark dopant well is identical with the channel type of ldmos transistor to be formed in this dark dopant well, and ldmos transistor to be formed has source electrode, drain electrode and gate dielectric layer in described this dark dopant well; Execution in step S13 forms isolation structure in described dark dopant well, described isolation structure is between source electrode and drain electrode and near drain electrode; Execution in step S15 forms first ion doped region in described dark dopant well, the conduction type of described first ion doped region is identical with the channel type of ldmos transistor; The degree of depth of described first ion doped region is greater than isolation structure bottom and the peripheral profile that covers drain electrode and cover isolation structure at least corresponding subregion in described dark dopant well; Execution in step S17 forms second ion doped region in described dark dopant well, the conduction type of described second ion doped region is opposite with the channel type of ldmos transistor; Described second ion doped region covers source electrode and covering gate dielectric layer corresponding subregion in described dark dopant well at least; Have between described second ion doped region and first ion doped region at interval.
Described first ion doped region injects by ion and forms, and described ion injects and the dopant well of voltage device carries out simultaneously.
The mask pattern that forms the ion mask pattern that injects and the dopant well that forms voltage device of described first ion doped region is positioned on the same mask.
The channel type of described ldmos transistor can be the n type, also can be the p type, the present invention at first provides a kind of p-LDMOS transistorized formation method, with reference to Fig. 4, comprise: execution in step S101, Semiconductor substrate is provided, is formed with the dark dopant well of p type in the described Semiconductor substrate, ldmos transistor to be formed has source electrode, drain electrode and gate dielectric layer in described this dark dopant well; Execution in step S103 forms isolation structure in described dark dopant well, described isolation structure is between source electrode and drain electrode and near drain electrode; Execution in step S105 forms p type first ion doped region in described dark dopant well; The degree of depth of described first ion doped region is greater than isolation structure bottom and the peripheral profile that covers drain electrode and cover isolation structure at least corresponding subregion in described dark dopant well; Execution in step S107, second ion doped region of formation n type in described dark dopant well; Described second ion doped region covers source electrode and covering gate dielectric layer corresponding subregion in described dark dopant well at least; Have between described second ion doped region and first ion doped region at interval.
5 to 8 pairs of formation p-LDMOS transistor technologies of the present invention are described in detail with reference to the accompanying drawings.At first with reference to Fig. 5, provide Semiconductor substrate 301, be formed with the dark dopant well 303 of p type in the described Semiconductor substrate, ldmos transistor to be formed has source electrode, drain electrode and gate dielectric layer in described this dark dopant well.Also comprised forming dark n type dopant well 302 steps before forming described dark dopant well 303, described dark n type dopant well 302 degree of depth are greater than dark dopant well.
Described Semiconductor substrate 301 adopts p type silicon usually, since form described dark dopant well purpose for between the semiconductor device on the Semiconductor substrate and and Semiconductor substrate between isolate, in dark dopant well, forming semiconductor device then, therefore generally at first forming dark n type dopant well 302 so that and form PN junction between the Semiconductor substrate and isolate.
Simultaneously, the structure of dark dopant well can also comprise multiple, is not limited to the structure of illustrated dark dopant well in the present embodiment, such as being structures such as triple-well, the trap that falls back.
The concrete technology that forms dark n type dopant well 302 is, forms described dark n type dopant well 302 and injects by ion and form, and the ion of injection is a phosphonium ion, and the injection energy range is 2000Ke to 2500KeV, and the dosage range of injection is 1E13 to 2E13/cm 2, the angular range of injection is 0 to 7 °.
The concrete technology that forms the dark dopant well 303 of p type is, the dark dopant well 303 that forms described p type injects by ion and forms, and the ion of injection is the boron ion, and the injection energy range is 400KeV to 450KeV, and the dosage range of injection is 1.5E13/cm 2To 2.0E13/cm 2, the angular range of injection is 0 to 7 °.
Then, the dark dopant well 303 that forms described p type comprises that also annealing steps, described annealing temperature are 800 to 1100 ℃ afterwards, and annealing atmosphere is N 2, annealing time is 1 to 3 hour, annealing way is common boiler tube annealing.
As an embodiment, after forming described dark dopant well 303, adopt common boiler tube annealing, annealing temperature is 1000 ℃, annealing atmosphere is N 2, annealing time is 2 hours, air pressure is 1 atmospheric pressure in the time of annealing.
The technical program is passed through after forming dark dopant well at 800 to 1100 ℃ of temperature, N 2Annealing is 1 to 3 hour under the atmosphere, can make the ion distribution of injection repair the damage that the ion injection is caused more evenly, simultaneously.
In dark n type dopant well 302, form the dark dopant well 303 of p type among the present invention, its conduction type is identical with the channel type of ldmos transistor to be formed in this zone, purpose is for shortening the raceway groove of ldmos transistor, strengthen the width of depletion region simultaneously, help to improve the voltage endurance capability of ldmos transistor, this advantage can be below as can be seen.
Then, form isolation structure 304 in the dark dopant well 303 of described p type, described isolation structure 304 is between the source electrode of ldmos transistor to be formed and drain electrode and near drain electrode.Described isolation structure 304 adopts an oxidation (FOX), selective oxidation (LOCOS) or shallow trench isolation to form from (STI) usually, and the employing shallow trench isolation of relatively optimizing is from (STI) structure herein.Be similarly the puncture voltage that improves ldmos transistor in the effect that forms isolation structure near drain electrode end.
The defective that after forming isolation structure 304, need anneal usually and in forming the isolation structure process, produce to repair, therefore under the prerequisite of the performance that does not influence semiconductor device, above-mentioned annealing steps after the dark dopant well 303 that forms described p type carries out after can also staying and forming isolation structure 304 simultaneously, be the annealing afterwards of shared formation isolation structure 304, its annealing process is same as described above, is not described in detail in this.
With reference to Fig. 6, in the dark dopant well 303 of described p type, form first ion doped region 305 of p type; The degree of depth of described first ion doped region 305 is greater than the isolation structure bottom; And the subregion that covers drain electrode and cover peripheral profile correspondence in described dark dopant well of isolation structure 304 at least.The coverage of first ion doped region 305 is according to the threshold voltage of pipe, opening resistor (Rdson) or the like is chosen, such as first ion doped region 305 can cover drain electrode and the peripheral profile of isolation structure 304 in described dark dopant well corresponding whole zone or the peripheral profile that covers drain electrode and isolation structure 304 in described dark dopant well corresponding subregion in addition can cover drain electrode and exceed isolation structure 304 peripheral profile correspondence in described dark dopant well whole zone and to source electrode direction extension.
The doping content of first ion doped region 305 of described p type is greater than the doping content of the dark doping 303 of p type.
Described first ion doped region 305 inject to form by ion, comparative optimization be that the p type dopant well that described ion injects with voltage device carries out simultaneously.Such as the mask of the p type dopant well of mask that adopt to form first ion doped region 305 simultaneously and middle voltage device, can avoid in the prior art the extra injection process that increases like this in order to form the drift region, reduced the technology cost.
More preferably, the mask pattern of the ion of described first ion doped region 305 of formation of the present invention mask pattern that injects and the p type dopant well that forms voltage device is positioned on the same mask.Additionally increase mask with the needs of prior art and compare, can reduce the cycle period of technology cost and reduction product greatly by the mask that adopts the p type dopant well of voltage device in the formation, and can carry out simultaneously with the dopant well in voltage device zone in the formation.Because well-known, in semiconductor technology, the expense of making mask is normally high, and time-consuming.And prior art since the process conditions that form the drift region with form in the condition of dopant well in voltage device zone have big difference and can't with form in the p type dopant well of voltage device inject simultaneously.
The ion of described injection can be the boron ion, injects energy range and be 25 to 280KeV, and the dosage range of injection is 1.4E12 to 2E13/cm 2
As an embodiment, form described first ion doped region 305 and inject formation by ion, the ion of injection can be the boron ion, and the injection energy is 100KeV, and the dosage of injection is 6E12/cm 2
Then, in the dark dopant well 303 of described p type, form second ion doped region 306 of n type; The subregion that described second ion doped region 306 covers the source electrode of ldmos transistor to be formed and covers gate dielectric layer correspondence in described dark dopant well 303 of ldmos transistor to be formed at least; Have between described second ion doped region 306 and first ion doped region 305 at interval.The coverage of described second ion doped region 306 is chosen based on ldmos transistor basic parameter to be formed, such as threshold voltage, and opening resistor (Rdson) or the like.
The doping content of second ion doped region 306 of described n type is greater than the doping content of the dark doping 303 of p type, and the doping content of first ion doped region 305 and second ion doped region 306 is basic identical.
Forming described second ion doped region 306 adopts ion to inject formation, relatively optimize be the mask pattern that forms described second ion doped region 306 with form in the mask pattern of n type dopant well of voltage device be positioned on the same mask, promptly can inject formation simultaneously with the n type dopant well of middle voltage device, additionally increasing mask with the needs of prior art compares, can reduce the cycle period of technology cost and reduction product greatly by the mask that adopts the n type dopant well of voltage device in the formation, and can carry out simultaneously with the dopant well in voltage device zone in the formation.Because well-known, in semiconductor technology, the expense of making mask is normally high, and time-consuming.And prior art since the process conditions that form the drift region with form in the condition of dopant well in voltage device zone have big difference and can't with form in the n type dopant well of voltage device inject simultaneously.
The ion of described injection can be phosphonium ion, injects energy range and be 90 to 440KeV, and the dosage range of injection is 9.5E12 to 1.5E13/cm 2
As an embodiment, form described first ion doped region 305 and inject formation by ion, the ion of injection is a phosphonium ion, and the injection energy is 140KeV, and the dosage of injection is 5.0E12/cm 2
The order of above-mentioned formation first ion doped region 305 and second ion doped region 306 can be put upside down, and should too much not limit protection scope of the present invention at this.
With reference to Fig. 7, the side wall 309 that on Semiconductor substrate 301, forms gate dielectric layer 307 and polysilicon gate 308 and be positioned at polysilicon gate 308 both sides, these structures of described formation are those skilled in the art's known technology, do not add detailed description at this.Described gate dielectric layer 307 extends to isolation structure
With reference to Fig. 8, form source electrode 310, drain electrode 311 in the dark dopant well 303 of the p type in Semiconductor substrate 301.Described source electrode 310 is positioned at second ion doped region 306 of n type, and described drain electrode 311 is positioned at first ion doped region 305 of p type.Described source electrode 310 and drain electrode 311 specifically also comprise source electrode extension area, the drain electrode extension areas of formation, form described source electrode extension area, the drain electrode extension area is a technology as well known to those skilled in the art, does not add detailed description at this.
Through above-mentioned technology, form p-LDMOS transistor of the present invention, with reference to Fig. 8, comprising: the source electrode 310, drain electrode 311 and the gate dielectric layer 307 that are positioned at Semiconductor substrate 301; Isolation structure 304 is at source electrode 310 with drain between 311 and near drain electrode 311; First ion doped region 305 is positioned at described Semiconductor substrate 301, and the conduction type of described first ion doped region 305 is identical with the conduction type of the raceway groove of ldmos transistor, is the p type; The degree of depth of described first ion doped region 305 is greater than isolation structure bottom and the subregion that covers drain electrode 311 and cover peripheral profile correspondence described Semiconductor substrate 301 in of isolation structure 304 at least; Second ion doped region 306 is positioned at described Semiconductor substrate 301, and the conductivity type opposite of the conduction type of described second ion doped region 306 and the raceway groove of ldmos transistor is the n type; Described second ion doped region 306 covers the source electrodes 310 and the subregion of covering gate dielectric layer 307 correspondence described Semiconductor substrate 301 at least; Have between described second ion doped region 306 and first ion doped region 305 at interval; Also comprise: dark dopant well 303, the conduction type of described dark dopant well 303 is identical with the conduction type of the raceway groove of ldmos transistor, be the p type, described dark dopant well 303 covers the zone of described first ion doped region 305, second ion doped region 306 and gate dielectric layer 307 correspondence in described Semiconductor substrate 301.
In the p-LDMOS of above-mentioned technology and formation thereof transistor, in Semiconductor substrate 301, form the p moldeed depth dopant well 303 identical with the transistorized channel type of p-LDMOS to be formed, form first ion doped region 305 and second ion doped region 306 of isolating mutually at p moldeed depth dopant well 303 then, described first ion doped region 305 is identical with the transistorized channel type of p-LDMOS, second ion doped region 306 is opposite with channel type, therefore the transistorized raceway groove of p-LDMOS that forms is the second ion doped region part of gate dielectric layer 307 correspondences, therefore compared with prior art raceway groove is shorter, under grid voltage, form back-biased diode between the dark dopant well 303 of p type and first ion doped region 305 and second ion doped region 306, this depletion region exhausts entirely before puncturing, can obtain higher puncture voltage, be that snap back phenomenon in the I-V curve of ldmos transistor moves to right, improve the withstand voltage degree of ldmos transistor; Simultaneously, the doping content of first ion doped region 305 by increasing the p type among the present invention can reduce the opening resistor (Rdson) of ldmos transistor; And, because first ion doped region 305 of the p type that forms is identical with the conduction type of the dark dopant well 303 of p type, even because when forming first ion doped region 305, mask in the photoetching process has deviation, when not surrounding isolation structure 304 fully even not surrounding isolation structure 304 parts such as first ion doped region 305, the too high and actual situation about using of influence of the threshold value that can not cause prior art.
Simultaneously, mask pattern by will forming described first ion doped region 305 with form in the mask pattern of p type dopant well of voltage device be arranged on the same mask, the mask pattern that forms described second ion doped region 306 with form in the mask pattern of n type dopant well of voltage device be arranged on the same mask, can reduce the technology cost greatly and reduce the cycle period of product.
Fig. 9 adopts the transistorized output characteristic curve of p-LDMOS shown in Figure 2 of the prior art, abscissa is drain voltage (Vd), ordinate is drain current (Id), and the Medici software of this (Synopsys) company of the snop of this The data U.S. is simulated acquisition.Wherein, the implantation dosage of the P-zone 204 of the ldmos transistor of curve I～III correspondence (i.e. Lou Ji drift region) successively decreases 25% successively.All the other conditions are identical, on behalf of the condition of the p type dopant well of voltage device in regional 204 employings of the P-of ldmos transistor, curve IV inject, all the other process conditions of four pipes are all identical among Fig. 9, threshold voltage is-1.1V, through simulation, the puncture voltage of the ldmos transistor of curve I～IV representative is respectively-22.5 ,-25.0 ,-27.0 ,-19.4V, drain saturation current Ids is respectively-41 ,-40 ,-38 ,-67 μ A/ μ m, by the characteristic of I～III curve as can be seen, along with reducing of implantation dosage, the puncture voltage of the ldmos transistor of formation reduces.
Figure 10 is the transistorized I-V characteristic curve of p-LDMOS that adopts method of the present invention to form.Ordinate is drain voltage (Vd), and abscissa is drain current (Id), and the Medici software of this (Synopsys) company of the snop of this The data U.S. is simulated acquisition.Wherein, the dark n type dopant well of the ldmos transistor of curve I～II correspondence is different with the implantation dosage of the dark dopant well of p type.The dark n type dopant well implantation dosage of curve I is 1E13, and the injection ion is a phosphorus; The implantation dosage of the dark dopant well of p type is 1.3E13, and the injection ion is a boron.The dark n type dopant well implantation dosage of curve II is 1.5E13, and the injection ion is a phosphorus; The implantation dosage of the dark dopant well of p type is 2.0E13, and the injection ion is a boron.Other technologies of the ldmos transistor that forms are all identical, threshold voltage is-1.8V, through simulation, the puncture voltage of the ldmos transistor of curve I～II representative is respectively-28 ,-23V, drain saturation current Ids is respectively-46 ,-47 μ A/ μ m, by the characteristic of I～II curve as can be seen, along with the increase of implantation dosage, the puncture voltage of the ldmos transistor of formation reduces.
Simultaneously, can analogize, when adopting method of the present invention to make threshold voltage be-during the manufacturing ldmos transistor of 1.1V, owing to can reduce the concentration of dopant well, therefore its puncture voltage can be-pipe of 1.8V higher than threshold voltage, and this illustrates that method of the present invention has certain advantage for the voltage endurance capability of raising ldmos transistor.
The present invention gives the transistorized formation method of a kind of n-LDMOS, with reference to Figure 11, comprise: execution in step S201, Semiconductor substrate is provided, be formed with the dark dopant well of n type in the described Semiconductor substrate, ldmos transistor to be formed has source electrode, drain electrode and gate dielectric layer in described this dark dopant well; Execution in step S203 forms isolation structure in described dark dopant well, described isolation structure is between source electrode and drain electrode and near drain electrode; Execution in step S205 forms n type first ion doped region in described dark dopant well; The degree of depth of described first ion doped region is greater than the isolation structure bottom; And the subregion that covers drain electrode and cover peripheral profile correspondence in described dark dopant well of isolation structure at least; Execution in step S207, second ion doped region of formation p type in described dark dopant well; Described second ion doped region covers source electrode and covering gate dielectric layer corresponding subregion in described dark dopant well at least; Have between described second ion doped region and first ion doped region at interval.
12 to 15 pairs of formation n-LDMOS transistor technologies of the present invention are described in detail with reference to the accompanying drawings, at first with reference to Figure 12, Semiconductor substrate 401 is provided, be formed with the dark dopant well 402 of n type in the described Semiconductor substrate, 402 ldmos transistors to be formed have source electrode, drain electrode and gate dielectric layer in described this dark dopant well.
The structure of described dark dopant well can also comprise multiple, is not limited to illustrated dark dopant well structure in the present embodiment, such as being structures such as triple-well, the trap that falls back.
The dark dopant well 402 that forms the n type injects by ion and forms, and specifically technology is, the ion of injection is a phosphonium ion, and the injection energy range is 2000KeV to 2500KeV, and the dosage range of injection is 1E13 to 2E13/cm 2, the angular range of injection is 0 to 7 °.
Then, the dark dopant well 402 that forms described n type comprises that also annealing steps, described annealing temperature are 800 to 1100 ℃ afterwards, and annealing atmosphere is N 2, annealing time is 1 to 3 hour.
As an embodiment, after forming described dark dopant well 303, adopt common tube furnace mode to anneal, annealing temperature is 1100 ℃, annealing atmosphere is N 2, annealing time is 2 hours, air pressure is 1 atmospheric pressure in the time of annealing.
The technical program is passed through after forming dark dopant well at 800 to 1100 ℃, N 2Annealing is 1 to 3 hour under the atmosphere, makes the ion distribution in it more even, can repair ion simultaneously and inject the damage that is caused.
In Semiconductor substrate 401, form the dark dopant well 402 of n type among the present invention, its conduction type is identical with the transistorized channel type of n-LDMOS to be formed in this zone, purpose is for shortening the raceway groove of ldmos transistor, strengthen the width of depletion region simultaneously, help to improve the voltage endurance capability of ldmos transistor.
Then, form isolation structure 403 in described n moldeed depth dopant well 402, described isolation structure 403 is between the source electrode of ldmos transistor to be formed and drain electrode and near drain electrode.Described isolation structure 403 adopts an oxidation (FOX), selective oxidation (LOCOS) or shallow trench isolation to form from (STI) usually, and the employing shallow trench isolation of relatively optimizing is from (STI) structure herein.Be similarly the puncture voltage that improves ldmos transistor in the effect that forms isolation structure near drain electrode end.
After forming isolation structure 403, need anneal usually, to eliminate the defective that in forming isolation structure 403 processes, produces, under the prerequisite of the performance that does not influence semiconductor device, above-mentioned annealing steps after the dark dopant well 402 that forms described n type carries out after can also staying and forming isolation structure 403 simultaneously, be the annealing afterwards of shared formation isolation structure 403, its annealing process is same as described above, is not described in detail in this.
With reference to Figure 13, in described n moldeed depth dopant well 402, form first ion doped region 404 of n type; The degree of depth of described first ion doped region 404 is greater than isolation structure 403 bottoms; And the outer subregion that is trapped among correspondence in the described n moldeed depth dopant well 402 that covers drain electrode and cover isolation structure 403 at least.The coverage of first ion doped region 404 is chosen according to the threshold voltage of pipe and opening resistor (Rdson) or the like basic parameter, can cover the whole zone of peripheral profile correspondence in described dark dopant well 402 of drain electrode and isolation structure 403 such as first ion doped region 404 of n type, perhaps cover the subregion of peripheral profile correspondence in described dark dopant well 402 of drain electrode and isolation structure 403, even the whole zone of peripheral profile correspondence described dark dopant well 402 in that can cover drain electrode and exceed isolation structure 403 and to source electrode direction extension.
The doping content of first ion doped region 404 of described n type is greater than the doping content of the dark doping 402 of n type.
Described first ion doped region 404 inject to form by ion, comparative optimization be that n type dopant well with middle voltage device carries out simultaneously.Such as the mask of the n type dopant well of mask that adopt to form first ion doped region 404 simultaneously and middle voltage device, can avoid in the prior art the extra injection process that increases like this in order to form the drift region, reduced the technology cost.
More preferably, the ion of described first ion doped region 404 of formation of the present invention mask pattern that injects and the n type dopant well mask pattern that forms voltage device is positioned on the same mask.Additionally increase mask with the needs of prior art and compare, can reduce the cycle period of technology cost and reduction product greatly by the mask that adopts the n type dopant well of voltage device in the formation, and can carry out simultaneously with the dopant well in voltage device zone in the formation.Because well-known, in semiconductor technology, the expense of making mask is normally high, and time-consuming.And prior art since the process conditions that form the drift region with form in the condition of dopant well in voltage device zone have big difference and can't with form in the p type dopant well of voltage device inject simultaneously.
The ion of described injection can be phosphonium ion, injects energy range and be 90 to 440KeV, and the dosage range of injection is 9.5E12 to 1.5E13/cm 2
As an embodiment, form described first ion doped region 305 and inject formation by ion, the ion of injection is a phosphonium ion, and the injection energy is 140KeV, and the dosage of injection is 5.0E12/cm 2
Then, in the dark dopant well 402 of described n type, form second ion doped region 405 of p type; The subregion that described second ion doped region 405 covers the source electrode of ldmos transistor to be formed and covers gate dielectric layer correspondence in described dark dopant well 402 of ldmos transistor to be formed at least; Have between described second ion doped region 405 and first ion doped region 404 at interval.The coverage of described second ion doped region 405 is chosen based on ldmos transistor basic parameter to be formed, such as threshold voltage or the like.
The doping content of second ion doped region 306 of described p type is greater than the doping content of the dark doping 402 of n type, and the doping content of first ion doped region 404 and second ion doped region 405 is basic identical.
Forming described second ion doped region 405 adopts ion to inject formation, the mask pattern that forms described second ion doped region 405 with form in the mask pattern of p type dopant well of voltage device be positioned on the same mask, promptly can inject formation simultaneously with the p type dopant well of middle voltage device, additionally increasing mask with the needs of prior art compares, can reduce the cycle period of technology cost and reduction product greatly by the mask that adopts the p type dopant well of voltage device in the formation, and can carry out simultaneously with the dopant well in voltage device zone in the formation.Because well-known, in semiconductor technology, the expense of making mask is normally high, and time-consuming.And prior art since the process conditions that form the drift region with form in the condition of dopant well in voltage device zone have big difference and can't with form in the p type dopant well of voltage device inject simultaneously.
The ion of described injection can be the boron ion, injects energy range and be 25 to 280KeV, and the dosage range of injection is 1.4E12 to 2E13/cm 2
As an embodiment, form described first ion doped region 404 and inject formation by ion, the ion of injection is the boron ion, and the injection energy is 100KeV, and the dosage of injection is 6E12/cm 2
The order of above-mentioned formation first ion doped region 404 and second ion doped region 405 can be put upside down, and should too much not limit protection scope of the present invention at this.
With reference to Figure 14, the side wall 408 that on Semiconductor substrate 401, forms gate dielectric layer 406 and polysilicon gate 407 and be positioned at polysilicon gate 407 both sides, these structures of described formation are those skilled in the art's known technology, do not add detailed description at this.Described gate dielectric layer 406 extends to isolation structure.
With reference to Figure 15, form source electrode 409, drain electrode 410 in the n moldeed depth dopant well 402 in Semiconductor substrate 401.Described source electrode 409 is positioned at second ion doped region 405 of p type, and described drain electrode 410 is positioned at first ion doped region 402 of n type.Described source electrode 409 and drain electrode 410 specifically also comprise source electrode extension area, the drain electrode extension area of formation, owing to be not emphasis of the present invention, do not add detailed description.
Through above-mentioned technology, form ldmos transistor of the present invention, with reference to Figure 15, comprising: the source electrode 409, drain electrode 410 and the gate dielectric layer 406 that are positioned at Semiconductor substrate 401; Isolation structure 403 is at source electrode 409 with drain between 410 and near drain electrode 410; First ion doped region 404 is positioned at described Semiconductor substrate 401, and the conduction type of described first ion doped region 404 is identical with the conduction type of the raceway groove of ldmos transistor, is the n type; The degree of depth of described first ion doped region 404 is greater than isolation structure bottom and the subregion that covers drain electrode 410 and cover peripheral profile correspondence described Semiconductor substrate 401 in of isolation structure 403 at least; Second ion doped region 405 is positioned at described Semiconductor substrate 401, and the conductivity type opposite of the conduction type of described second ion doped region 405 and the raceway groove of ldmos transistor is the p type; Described second ion doped region 405 covers the source electrodes 409 and the subregion of covering gate dielectric layer 406 correspondence described Semiconductor substrate 401 at least; Have between described second ion doped region 405 and first ion doped region 404 at interval; Also comprise: dark dopant well 402, the conduction type of described dark dopant well 402 is identical with the conduction type of the raceway groove of ldmos transistor, be the n type, described dark dopant well 402 covers the zone of described first ion doped region 404, second ion doped region 405 and gate dielectric layer 406 correspondence in described Semiconductor substrate 401.
In the n-LDMOS of above-mentioned technology and formation thereof transistor, in Semiconductor substrate 401, form the n moldeed depth dopant well 402 identical with the transistorized channel type of n-LDMOS to be formed, form n type first ion doped region 404 and p type second ion doped region 405 of isolating mutually at n moldeed depth dopant well 402 then, described first ion doped region 404 is identical with the transistorized channel type of n-LDMOS, second ion doped region 405 is opposite with channel type, therefore the transistorized raceway groove of n-LDMOS that forms is second ion doped region, 405 parts of gate dielectric layer 406 correspondences, therefore compared with prior art raceway groove is shorter, under grid voltage, form back-biased diode between first ion doped region 404 of the dark dopant well 402 of n type and n type and second ion doped region 405 of p type, this depletion region exhausts entirely before puncturing, can obtain higher puncture voltage, be that snap back phenomenon in the transistorized I-V curve of n-LDMOS moves to right, improve the transistorized withstand voltage degree of n-LDMOS; Simultaneously, the doping content of first ion doped region 404 by increasing the n type among the present invention can reduce the transistorized opening resistor of n-LDMOS (rdson); And, because first ion doped region 404 of the n type that forms is identical with the conduction type of the dark dopant well 402 of n type, even because when forming first ion doped region 404, mask in the photoetching process has deviation, when not surrounding isolation structure 403 fully even not surrounding isolation structure 403 parts such as first ion doped region 404, the too high and actual situation about using of influence of the threshold value that can not cause prior art.
Simultaneously, mask pattern by will forming described first ion doped region 404 with form in the mask pattern of n type dopant well of voltage device be arranged on the same mask, the mask pattern that forms described second ion doped region 405 with form in the mask pattern of p type dopant well of voltage device be arranged on the same mask, can reduce the technology cost greatly and reduce the cycle period of product.
Figure 16 is the transistorized output characteristic curve of n-LDMOS that adopts similar p-LDMOS transistor arrangement shown in Figure 2 in the prior art, only be the conductivity type opposite in each district with Fig. 2 difference, become p N-type semiconductor N substrate, N-zone 203 such as dark n type dopant well 201 and become p type, P-zone 204 and become n type, source electrode 208 and drain and 209 be N +
Abscissa is drain voltage (Vd) among Figure 16, and ordinate is drain current (Id), and the Medici software of this (Synopsys) company of the snop of this The data U.S. is simulated acquisition.Wherein, the implantation dosage in the transistorized n-of the n-LDMOS zone 204 (i.e. Lou Ji drift region) of curve I～III correspondence successively decreases 25% successively.All the other conditions are identical, on behalf of the condition of the n type dopant well of voltage device in the transistorized n-of n-LDMOS zone 204 employings, curve IV inject, all the other conditions are all identical, article four, the transistorized threshold voltage of n-LDMOS of curve representative is 1.0V, through simulation, the transistorized puncture voltage of n-LDMOS of curve I～IV representative is respectively 22.3,23.0,26.5,19.2V, drain saturation current Ids is respectively 165,160,150,229 μ A/ μ m, as can be seen along with the reducing of implantation dosage, the puncture voltage of the ldmos transistor of formation reduces by the characteristic of I～IV curve.
Figure 17 is the transistorized I-V characteristic curve of n-LDMOS that adopts method of the present invention to form.Abscissa is drain voltage (Vd), and ordinate is drain current (Id), and the Medici software of this (Synopsys) company of the snop of this The data U.S. is simulated acquisition.Wherein, the dark n type dopant well of the ldmos transistor of curve I～II correspondence is different with the implantation dosage of the dark dopant well of p type.The technology of curve I is 1.0e13/cm 2, the technology of curve II is 1.5e13/cm 2Other technologies of the ldmos transistor that forms are all identical, threshold voltage is 0.7V, through simulation, the puncture voltage of the ldmos transistor of curve I～II representative is respectively 28,26V, drain saturation current Ids is respectively 203,253 μ A/ μ m, as can be seen along with the increase of implantation dosage, the puncture voltage of the ldmos transistor of formation reduces, the corresponding increase of the saturation current that obtains by the characteristic of I～II curve.
Simultaneously, can analogize, when adopting the n-LDMOS transistor of method manufacturing of the present invention and threshold voltage identical (1.0V) among Figure 16, its puncture voltage can reduce a little because improving the concentration of dopant well, but it still is the same order of magnitude, can not influence actual use, and because it adopts the mask in middle voltage device zone, for reducing cost, this defective is negligible.
The present invention also provides a kind of manufacture method that has the semiconductor device of ldmos transistor, comprising: Semiconductor substrate is provided, and described Semiconductor substrate contains high tension apparatus zone (HV) and middle voltage device zone (MV); In the Semiconductor substrate in described high tension apparatus zone, form dark dopant well, the conduction type of described dark dopant well is identical with the channel type of ldmos transistor to be formed in this dark dopant well, and ldmos transistor to be formed has source electrode, drain electrode and gate dielectric layer in described this dark dopant well; Form isolation structure in described dark dopant well, described isolation structure is between source electrode and drain electrode and near drain electrode; Form first ion doped region in described dark dopant well, the conduction type of described first ion doped region is identical with the channel type of described ldmos transistor; The degree of depth of described first ion doped region is greater than the isolation structure bottom; And the subregion that covers drain electrode and cover peripheral profile correspondence in described dark dopant well of isolation structure at least; Form second ion doped region in described dark dopant well, the conduction type of described second ion doped region is opposite with the channel type of described ldmos transistor; Described second ion doped region covers source electrode and covering gate dielectric layer corresponding subregion in described dark dopant well at least; Have between described second ion doped region and first ion doped region at interval.
The formation that Figure 18 provides one embodiment of the present of invention has the structural representation of the semiconductor device of ldmos transistor.Comprise:
Semiconductor substrate 1, described Semiconductor substrate 1 contain high tension apparatus zone HV and middle voltage device zone MV; Described high tension apparatus zone HV comprises i zone and ii zone, and described i contains p-LDMOS in the zone, and described ii contains n-LDMOS in the zone; Voltage device zone MV comprises iii zone and iv zone in described, and described iii contains p-MOS in the zone, and described iv contains n-MOS in the zone;
I zone and the ii zone of described high tension apparatus zone HV also are formed with dark dopant well 3a and 3b respectively, and described dark dopant well 3a is the p type, and dark dopant well 3b is the n type, and be identical with the channel type of ldmos transistor of formation in the zone separately respectively; The i of voltage device zone MV zone and ii zone also are formed with dark dopant well 3c and 3d respectively in described, and described dark dopant well 3c is the n type, and described dark dopant well 3d is the p type, and be opposite with the channel type of MOS transistor of formation in the zone separately respectively;
I zone at HV also is formed with isolation structure 4a, and described isolation structure 4a is between the source electrode of ldmos transistor to be formed and drain electrode and near drain electrode; Ii zone at HV also is formed with isolation structure 4b, and described isolation structure 4b is between the source electrode of ldmos transistor to be formed and drain electrode and near drain electrode;
In the dark dopant well 3a in the i zone of HV, also be formed with the first ion doped region 5a, the described first ion doped region 5a is identical with the channel type of ldmos transistor to be formed, therefore be the p type, the degree of depth of the described first ion doped region 5a is greater than isolation structure 4a bottom, and the subregion that covers the drain electrode of ldmos transistor to be formed and cover peripheral profile correspondence in described dark dopant well 3a of isolation structure at least; Also be formed with the first ion doped region 5b at the ii of HV, the described first ion doped region 5b is identical with the channel type of ldmos transistor to be formed, therefore be the n type, the degree of depth of the described first ion doped region 5b is greater than isolation structure 4a bottom, and the subregion that covers the drain electrode of ldmos transistor to be formed and cover peripheral profile correspondence in described dark dopant well 3b of isolation structure at least;
In the dark dopant well 3a in the i zone of HV, also be formed with the second ion doped region 6a, the conduction type of the described second ion doped region 6a is opposite with the channel type of described ldmos transistor, therefore be the n type, the described second ion doped region 6a covers the source electrode of ldmos transistor to be formed and covering gate dielectric layer corresponding subregion in described dark dopant well at least, has between the described second ion doped region 6a and the first ion doped region 5a at interval; In the dark dopant well 3b in the ii zone of HV, also be formed with the second ion doped region 6b, the conduction type of the described second ion doped region 6b is opposite with the channel type of described ldmos transistor, therefore be the p type, the described second ion doped region 6b covers the source electrode of ldmos transistor to be formed and covering gate dielectric layer corresponding subregion in described dark dopant well at least, has between the described second ion doped region 6b and the first ion doped region 5b at interval;
Be formed with gate dielectric layer 7a, 7b, 7c and 7d respectively on the i of described Semiconductor substrate 1, ii, iii, the iv zone, described gate dielectric layer 7a, 7b, 7c and 7d are in HV zone and can be different at the thickness of MV;
On gate dielectric layer 7a, 7b, 7c and 7d, be formed with polysilicon gate 8a, 8b, 8c, 8d respectively, and side wall 9a, the 9b, 9c, the 9d that are formed at each polysilicon gate both sides respectively.
Be formed with source electrode 10a, 10b and drain electrode 11a, 11b in the i of described Semiconductor substrate 1, ii, iii, the iv zone respectively, described source electrode 10a, 10b lay respectively in the second ion doping trap 6a, the 6b in i, ii zone, and described drain electrode 11a, 11b lay respectively in the first ion doping trap 5a, the 5b in i, ii zone; Described source electrode 10c, 10d and drain electrode 11c, 11d lay respectively in dark dopant well 3c in iii, iv zone and the 3d.
Form the described first ion doped region 5a comparative optimization be with form in the dark dopant well 3d in iv zone of voltage device zone MV carry out simultaneously.More preferably, can with the mask pattern that forms the described first ion doped region 5a with form in the mask pattern of dark dopant well 3d in iv zone of voltage device zone MV be arranged on the same mask.
Form the described first ion doped region 5b comparative optimization be with form in the dark dopant well 3c in iii zone of voltage device zone MV carry out simultaneously.More preferably, the mask pattern that forms the described first ion doped region 5b mask pattern with the dark dopant well 3c in the iii zone of the regional MV of middle voltage device can be arranged on the same mask.
Form the described second ion doped region 6a comparative optimization be with form in the dark dopant well 3c in iii zone of voltage device zone MV carry out simultaneously.More preferably, the mask pattern that forms the described second ion doped region 6a mask pattern with the dark dopant well 3c in the iii zone of the regional MV of middle voltage device can be arranged on the same mask.
Form the described second ion doped region 6b comparative optimization be with form in the dark dopant well 3d in iv zone of voltage device zone MV carry out simultaneously.More preferably, the mask pattern that forms the described second ion doped region 6b mask pattern with the dark dopant well 3d in the iv zone of the regional MV of middle voltage device can be arranged on the same mask.
If Semiconductor substrate 1 is the p type, before forming dark dopant well 3a, the i zone of HV also comprises the step that forms dark n type dopant well 2a, before forming dark dopant well 3c, the iii zone of MV also comprises the step that forms dark n type dopant well 2c.
Form after described dark dopant well 3a, 3b, 3c and 3d and dark n type dopant well 2a, the 2c, also comprise that annealing steps, described annealing temperature are 800 to 1100 ℃, annealing atmosphere is N 2, annealing time is 2 hours.Through this step annealing, can make ion distribution in it more even and repair ion implantation damage.
Equally, the annealing of this step is carried out after can being placed on and forming isolation structure 4a, 4b, and is promptly shared with formation isolation structure annealing steps afterwards.
Remaining forms the above-mentioned method that has the semiconductor device of ldmos transistor and please refer to above-mentioned formation p-LDMOS and the transistorized method of n-LDMOS.
The above-mentioned semiconductor device of ldmos transistor and forming method thereof that has, have and aforesaid p-LDMOS and the similar advantage of n-LDMOS transistor, can improve its voltage endurance capability, and the mask of the formation dopant well in voltage device zone comes first ion doped region of corresponding formation ldmos transistor and the cycle period that second ion doped region can reduce technology cost and product in adopting.
Though the present invention discloses as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art without departing from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.

Claims (17)

1. the manufacture method of a ldmos transistor comprises the steps:
Semiconductor substrate is provided;
In described Semiconductor substrate, form dark dopant well, the conduction type of described dark dopant well is identical with the channel type of ldmos transistor to be formed in this dark dopant well, and ldmos transistor to be formed has source electrode, drain electrode and gate dielectric layer in described this dark dopant well;
Form isolation structure in described dark dopant well, described isolation structure is between source electrode and drain electrode and near drain electrode;
Form first ion doped region in described dark dopant well, the conduction type of described first ion doped region is identical with the channel type of ldmos transistor; The degree of depth of described first ion doped region greater than isolation structure bottom and cover drain electrode and cover isolation structure at least be trapped among subregion corresponding in the described dark dopant well outward;
Form second ion doped region in described dark dopant well, the conduction type of described second ion doped region is opposite with the channel type of ldmos transistor; Described second ion doped region covers source electrode and covering gate dielectric layer corresponding subregion in described dark dopant well at least; Have between described second ion doped region and first ion doped region at interval.
2. the manufacture method of ldmos transistor according to claim 1 forms described dark dopant well and comprises that also annealing steps, described annealing temperature are 800 to 1100 ℃ afterwards, and annealing atmosphere is N 2, annealing time is 1 to 3 hour.
3. the manufacture method of ldmos transistor according to claim 1, described first ion doped region are injected by ion and are formed, and the dopant well that described ion injects with voltage device carries out simultaneously.
4. the manufacture method of ldmos transistor according to claim 3, the mask pattern that forms the ion mask pattern that injects and the dopant well that forms voltage device of described first ion doped region is positioned on the same mask.
5. the manufacture method of ldmos transistor according to claim 4, the channel type of described ldmos transistor is the n type, the mask pattern that forms described first ion doped region with form in the mask pattern of n type dopant well of voltage device be positioned on the same mask, the mask pattern that forms described second ion doped region with form in the mask pattern of p type dopant well of voltage device be positioned on the same mask, described dark dopant well is the n type.
6. the manufacture method of ldmos transistor according to claim 4, the channel type of described ldmos transistor is the p type, the figure that forms described first ion doped region with form in the mask pattern of p type dopant well of voltage device be positioned on the same mask, the mask pattern that forms described second ion doped region with form in the mask pattern of n type dopant well of voltage device be positioned on the same mask, described dark dopant well is the p type.
7. the manufacture method of ldmos transistor according to claim 6 also comprised forming dark n type dopant well step before forming described dark dopant well, and the described dark n type dopant well degree of depth is greater than dark dopant well.
8. ldmos transistor comprises:
Be positioned at source electrode, drain electrode and the gate dielectric layer of Semiconductor substrate;
Isolation structure is between source electrode and drain electrode and near drain electrode;
First ion doped region is positioned at described Semiconductor substrate, and the conduction type of described first ion doped region is identical with the conduction type of the raceway groove of ldmos transistor; The degree of depth of described first ion doped region greater than isolation structure bottom and cover drain electrode and cover isolation structure at least be trapped among subregion corresponding in the described Semiconductor substrate outward;
Second ion doped region is positioned at described Semiconductor substrate, the conductivity type opposite of the conduction type of described second ion doped region and the raceway groove of ldmos transistor; Described second ion doped region covers source electrode and covering gate dielectric layer corresponding subregion in described Semiconductor substrate at least; Have between described second ion doped region and first ion doped region at interval;
It is characterized in that, also comprise: dark dopant well, the conduction type of described dark dopant well is identical with the conduction type of the raceway groove of ldmos transistor, and covers the subregion of described first ion doped region, second ion doped region and gate dielectric layer correspondence in described Semiconductor substrate.
9. ldmos transistor according to claim 8 also comprises the dark n type dopant well that is positioned at Semiconductor substrate, and the described dark n type dopant well degree of depth is greater than dark dopant well.
10. manufacture method with semiconductor device of ldmos transistor comprises:
Semiconductor substrate is provided, and described Semiconductor substrate contains high tension apparatus zone and middle voltage device zone; In the Semiconductor substrate in high tension apparatus zone, form dark dopant well, the conduction type of described dark dopant well is identical with the channel type of ldmos transistor to be formed in this dark dopant well, and ldmos transistor to be formed has source electrode, drain electrode and gate dielectric layer in described this dark dopant well;
Form isolation structure in described dark dopant well, described isolation structure is between source electrode and drain electrode and near drain electrode;
Form first ion doped region in described dark dopant well, the conduction type of described first ion doped region is identical with the channel type of described ldmos transistor; The degree of depth of described first ion doped region is greater than the isolation structure bottom; And the outer subregion that is trapped among correspondence in the described dark dopant well that covers drain electrode and cover isolation structure at least;
Form second ion doped region in described dark dopant well, the conduction type of described second ion doped region is opposite with the channel type of described ldmos transistor; Described second ion doped region covers source electrode and covering gate dielectric layer corresponding subregion in described dark dopant well at least; Have between described second ion doped region and first ion doped region at interval.
11. the manufacture method of semiconductor device according to claim 10 forms described dark dopant well and comprises that also annealing steps, described annealing temperature are 800 to 1100 ℃ afterwards, annealing atmosphere is N 2, annealing time is 1 to 3 hour.
Form 12. the manufacture method of semiconductor device according to claim 11, described first ion doped region are injected by ion, described ion injects and the dopant well of voltage device carries out simultaneously.
13. the manufacture method of semiconductor device according to claim 12, the mask pattern that forms the ion mask pattern that injects and the dopant well that forms voltage device of described first ion doped region is positioned on the same mask.
14. the manufacture method of semiconductor device according to claim 13, the channel type of described ldmos transistor is the n type, the mask pattern that forms described first ion doped region with form in the mask pattern of n type dopant well of voltage device be positioned on the same mask, the mask pattern that forms described second ion doped region with form in the mask pattern of p type dopant well of voltage device be positioned on the same mask, described dark dopant well is the n type.
15. the manufacture method of semiconductor device according to claim 13, the channel type of described ldmos transistor is the p type, the figure that forms described first ion doped region with form in the mask pattern of p type dopant well of voltage device be positioned on the same mask, the mask pattern that forms described second ion doped region with form in the mask pattern of n type dopant well of voltage device be positioned on the same mask, described dark dopant well is the p type.
16. the manufacture method of semiconductor device according to claim 15 comprised also before forming described dark dopant well forming dark n type dopant well step that the described dark n type dopant well degree of depth is greater than dark dopant well.
17. semiconductor device as claim 10 manufacturing.
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