CN101726299A - Sun sensor simulator for satellite closed cycle simulation test - Google Patents
Sun sensor simulator for satellite closed cycle simulation test Download PDFInfo
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- CN101726299A CN101726299A CN200910311102A CN200910311102A CN101726299A CN 101726299 A CN101726299 A CN 101726299A CN 200910311102 A CN200910311102 A CN 200910311102A CN 200910311102 A CN200910311102 A CN 200910311102A CN 101726299 A CN101726299 A CN 101726299A
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Abstract
The invention relates to a sun sensor simulator for satellite closed cycle simulation test, belonging to the field of satellite test; the sun sensor simulator simulates the signal output of three kinds of the sun sensors simultaneously; a normal instruction control computer and a fault instruction control computer transmit a normal work instruction and a fault work instruction to a FPGA field programmable gate array, a module in the FPGA field programmable gate array receives and processes the two instructions respectively, a data selection module ensures the preferential execution of the fault work instruction, and an error frame counting module counts the number of the fault work instructions in the normal work instruction and transmits to the fault instruction control computer, and the FPGA field programmable gate array outputs control data to a 0-1 sun signal source unit, a simulation signal source unit and a digital sun signal source unit respectively to lead the corresponding sun signal source unit to output the current. The sun sensor simulator is applied to the satellite closed cycle simulation test.
Description
Technical field
The present invention relates to a kind of sun sensor simulator that is used for satellite closed cycle simulation test, belong to the satellite test field.
Background technology
Sun sensor (sun sensor) is the class sensor in the satellite fields widespread use, all is equipped with sun sensor on nearly all satellite.It is to determine the orientation of solar vector in the celestial body coordinate by the orientation of responsive solar vector, thereby obtains the optical attitude sensor of satellite with respect to solar azimuth information.Satellite transit is in outer space track, because the radiation of the sun is strong, profile is clear, and sun sensor is easy to experience solar radiation and obtains the orientation of satellite with respect to the sun thus.Sun sensor has usually that simple in structure, detectable field range is wide, reliable operation, low in energy consumption and characteristics that quality is little, its resolution from the several years to several rads.Sun sensor generally includes optical system, detector and three parts of signal processing circuit, generally the combination of optical system and detector is called optic probe.Sun sensor has three kinds of fundamental types:
One, " 0-1 " formula sun sensor: this " 0-1 " formula sun sensor claims sun presence sensor again, is mainly used in sun acquisition.Each " 0-1 " formula sun sensor is a semisphere, is divided into 5 zones, and a solar cell is arranged in each zone, and output signal is 1 when being sunlighted, otherwise is 0.
Two, analog sun sensor: analog sun sensor is the photocurrent combination results output signal by photoelectric cell output.Photronic arrangement mode makes the solar radiation of reception change with the sensor attitude.What analog sun sensor was exported is continuous quantity, and its size combines the incident angle that the function of setting up can be determined the sun with symbol.When solar incident angle equaled 0, the output current difference of sun sensor equaled 0, and this position is called sun sensor zero point; When solar incident angle was not equal to 0, the difference of output current was not equal to 0, utilized the current symbol and the current value of output can determine incident angle.
Three, digital sun sensor: the output signal of digital sun sensor is the discrete function of the coding form of solar incident angle.Digital sun sensor is made up of inlet seam, code-disc, photoelectric cell, amplifier and impact damper.Utilize a narrow slit and a Gray code, the emittance that is transmitted to (being each numeral) on every Gray code is converted to photocurrent by a silion cell.Sign bit is used for determining the sun is positioned at which limit of sensor reference field, and bits of coded provides the digital quantity that sunshine departs from reference field.Photronic input signal is amplified into buffer register through amplifier, forms the binary digit amount that records.In signal processing circuit, adopt the numerical coding subdivide technology, just the simulating signal of code-disc lowest order output is segmented with analog to digital conversion circuit, can improve the resolution of sensor, the sun sensor of around this principle making precision in very big field range can reach 0.025 degree.Also have a kind of digital sun sensor that adopts array device as detector, its precision can reach pin level second.
Above-mentioned sun sensor all is mounted on the real satellite, and when satellite being carried out the ground simulation test, the signal output that also needs the simulated solar sensor is to obtain the information of satellite with respect to solar azimuth.Existing satellite used sun sensor when ground simulation is tested is based on the mode of scene drive, and the irradiation that only is subjected to light could be exported corresponding signal, complicated operation, cost height.
Summary of the invention
The invention provides a kind of sun sensor simulator that is used for satellite closed cycle simulation test, it realizes the signal output simulation simultaneously of three class sun sensors.
The present invention is made up of normal instruction control computing machine, fault instruction control computing machine, a RS422 chip, the 2nd RS422 chip, FPGA field programmable gate array, 0-1 sun signal source unit, simulated solar signal source unit, digital sun signal source unit and general supply treatment circuit
The control signal output ends of normal instruction control computing machine is by the normal instruction control signal input part of RS422 chip connection FPGA field programmable gate array, and the fault instruction control signal input output end of FPGA field programmable gate array connects the fault-signal I/O of fault instruction control computing machine by the 2nd RS422 chip; The 0-1 sun control signal output ends of FPGA field programmable gate array connects the signal input end of 0-1 sun signal source unit, the simulated solar control signal output ends of FPGA field programmable gate array connects the signal input end of simulated solar signal source unit, and the digital sun control signal output ends of FPGA field programmable gate array connects the signal input end of digital sun signal source unit; The power input of FPGA field programmable gate array connects the power output end of general supply treatment circuit;
The FPGA field programmable gate array is by the normal data receiver module, the normal data first-in first-out is deposited module, the normal data processing module, normal data is deposited module, the erroneous frame counting module, misdata number sending module, the fault data receiver module, the fault data first-in first-out is deposited module, the fault data processing module, fault data is deposited module, data are selected module, 0-1 sun data are deposited module, the simulated solar data deposit module and digital sun data are deposited the module composition
The normal data input end of normal data receiver module is the normal instruction control signal input part of FPGA field programmable gate array, the normal data output terminal of normal data receiver module connects the normal data first-in first-out and deposits the normal data input end of module, the normal data first-in first-out is deposited the normal data input end of the normal data output terminal connection normal data processing module of module, the normal data output terminal of normal data processing module connects normal data and deposits the normal data input end of module, and the normal data output terminal that normal data is deposited module connects the normal data input end that data are selected module; The misdata input end of the misdata output terminal connection error frame count module of normal data processing module, the misdata input end of the misdata output terminal connection error data number sending module of erroneous frame counting module, the misdata output terminal of misdata number sending module is the fault instruction control signal output part of FPGA field programmable gate array; The fault data input end of fault data receiver module is the fault instruction control signal input part of FPGA field programmable gate array, the fault data output terminal of fault data receiver module connects the fault data first-in first-out and deposits the fault data input end of module, the fault data first-in first-out is deposited the fault data input end of the fault data output terminal connection fault data processing module of module, the fault data output terminal of fault data processing module connects fault data and deposits the fault data input end of module, the fault data output terminal that fault data is deposited module connects the fault data input end that data are selected module, the switch data output terminal of fault data processing module connects the switch data input end that data are selected module, the switch data control data of fault data processing module is selected module, make preferential execution fault instruction when the fault data input is arranged, data are selected the control data output terminal of module to connect 0-1 sun data and are deposited the control data input end of module, the simulated solar data are deposited the control data input end and the digital sun data of module and are deposited the control data input end of module; The control data output terminal that 0-1 sun data are deposited module is the 0-1 sun control signal output ends of FPGA field programmable gate array, the control data output terminal that the simulated solar data are deposited module is the simulated solar control signal output ends of FPGA field programmable gate array, and the control data output terminal that digital sun data are deposited module is the digital sun control signal output ends of FPGA field programmable gate array.
Advantage of the present invention is: the output of the electric signal of direct modeling sun sensor of the present invention, and lay particular emphasis on the electrical characteristics of simulated solar sensor and adopt the mode of data-driven, make development cost reduce, control more flexible; Secondly, needn't use real sun sensor just can carry out the emulation and the test of satellite behind the employing sun sensor simulator, can shorten the satellite lead time; At last, the present invention adopts two-way RS422 Communication Control, the simultaneously normal operating conditions and the fail operation state of simulated solar sensor, and guarantee that by the logic control of FPGA internal module data select module preferentially to control and carry out the fault instruction that fault instruction control computing machine sends, make total system have very strong stability and versatility.
Description of drawings
Fig. 1 is an entire block diagram of the present invention, Fig. 2 is the internal logic control block diagram of FPGA field programmable gate array, Fig. 3 is that the present invention concerns block diagram in satellite ground closed cycle simulation test equipment, Fig. 4 is the structured flowchart of 0-1 sun signal source unit, Fig. 5 is the structured flowchart of simulated solar signal source unit, Fig. 6 is the structured flowchart of digital sun signal source unit, Fig. 7 is the circuit diagram of voltage controlled current source circuit among the present invention, Fig. 8 is a process flow diagram of carrying out the operate as normal instruction in the embodiment seven, and Fig. 9 is a process flow diagram of carrying out the fault instruction in the embodiment seven.
Embodiment
Embodiment one: present embodiment is described below in conjunction with Fig. 1-Fig. 3, present embodiment is made up of normal instruction control computing machine 1, fault instruction control computing machine 2, a RS422 chip 3, the 2nd RS422 chip 4, FPGA field programmable gate array 5,0-1 sun signal source unit 6, simulated solar signal source unit 7, digital sun signal source unit 8 and general supply treatment circuit 9
The control signal output ends of normal instruction control computing machine 1 is by the normal instruction control signal input part of a RS422 chip 3 connection FPGA field programmable gate arrays 5, and the fault instruction control signal input output end of FPGA field programmable gate array 5 connects the fault-signal I/O of fault instruction control computing machines 2 by the 2nd RS422 chip 4; The 0-1 sun control signal output ends of FPGA field programmable gate array 5 connects the signal input end of 0-1 sun signal source unit 6, the simulated solar control signal output ends of FPGA field programmable gate array 5 connects the signal input end of simulated solar signal source unit 7, and the digital sun control signal output ends of FPGA field programmable gate array 5 connects the signal input end of digital sun signal source unit 8; The power input of FPGA field programmable gate array 5 connects the power output end of general supply treatment circuit 9;
FPGA field programmable gate array 5 is by normal data receiver module 5-1, the normal data first-in first-out is deposited module 5-2, normal data processing module 5-3, normal data is deposited module 5-4, erroneous frame counting module 5-5, misdata number sending module 5-6, fault data receiver module 5-7, the fault data first-in first-out is deposited module 5-8, fault data processing module 5-9, fault data is deposited module 5-10, data are selected module 5-11,0-1 sun data are deposited module 5-12, the simulated solar data deposit module 5-13 and digital sun data are deposited module 5-14 composition
The normal data input end of normal data receiver module 5-1 is the normal instruction control signal input part of FPGA field programmable gate array 5, the normal data output terminal of normal data receiver module 5-1 connects the normal data input end that the normal data first-in first-out is deposited module 5-2, the normal data first-in first-out is deposited the normal data input end of the normal data output terminal connection normal data processing module 5-3 of module 5-2, the normal data output terminal of normal data processing module 5-3 connects the normal data input end that normal data is deposited module 5-4, and the normal data output terminal that normal data is deposited module 5-4 connects the normal data input end that data are selected module 5-11; The misdata input end of the misdata output terminal connection error frame count module 5-5 of normal data processing module 5-3, the misdata input end of the misdata output terminal connection error data number sending module 5-6 of erroneous frame counting module 5-5, the misdata output terminal of misdata number sending module 5-6 is the fault instruction control signal output part of FPGA field programmable gate array 5; The fault data input end of fault data receiver module 5-7 is the fault instruction control signal input part of FPGA field programmable gate array 5, the fault data output terminal of fault data receiver module 5-7 connects the fault data input end that the fault data first-in first-out is deposited module 5-8, the fault data first-in first-out is deposited the fault data input end of the fault data output terminal connection fault data processing module 5-9 of module 5-8, the fault data output terminal of fault data processing module 5-9 connects the fault data input end that fault data is deposited module 5-10, the fault data output terminal that fault data is deposited module 5-10 connects the fault data input end that data are selected module 5-11, the switch data output terminal of fault data processing module 5-9 connects the switch data input end that data are selected module 5-11, the switch data control data of fault data processing module 5-9 is selected module 5-11, make preferential execution fault instruction when the fault data input is arranged, data select the control data output terminal of module 5-11 to connect the control data input end that 0-1 sun data are deposited module 5-12, the simulated solar data are deposited the control data input end of module 5-13 and the control data input end that digital sun data are deposited module 5-14; The control data output terminal that 0-1 sun data are deposited module 5-12 is the 0-1 sun control signal output ends of FPGA field programmable gate array 5, the control data output terminal that the simulated solar data are deposited module 5-13 is the simulated solar control signal output ends of FPGA field programmable gate array 5, and the control data output terminal that digital sun data are deposited module 5-14 is the digital sun control signal output ends of FPGA field programmable gate array 5.
General supply treatment circuit 9 is made up of power supply and DC-to-dc isolation conversion chip DC-DC in the present embodiment, because power supply is a uphole equipment, and the electric current of last output is to satellite, in order to prevent that ground system from influencing on-board equipment, isolate conversion chip so added DC-to-dc.
The course of work: at first, normal instruction control computing machine 1 sends one group of operate as normal instruction, this group instruction comprises the job information of three kinds of sun signal sources, for example if want to allow 0-1 sun signal source unit 6 that the words of information output are arranged, the instruction that then relates to other sun signal source unit in this group instruction is 0 just can realize, the operate as normal instruction sends out the employing difference scheme from computing machine, be converted to the TTL form by a RS422 chip 3 after having arrived sun signal source unit, instruct then and come out to enter into FPGA field programmable gate array 5 from a RS422 chip 3.
Control with FPGA inside shown in Figure 2 is divided into each module.Upper left corner S_RS485 is normal control command passage, and the steering order that normal instruction control computing machine 1 sends has just entered this passage after through a RS422 chip 3.After entering this passage, at first be sent to normal data receiver module 5-1 the inside, being put into the normal data first-in first-out after it receives one one director data deposits among the module 5-2, normal data processing module 5-3 deposits the module 5-2 the judgement of taking out of a byte of a byte of director data from the normal data first-in first-out then, after having got all bytes, judge the verification of last byte and whether correct, verification and correct, this group instruction that then can judge transmission is put into normal data to the data of three sun signal source unit of control then and deposits module 5-4 the inside for correct; If verification and to judge this group instruction incorrect then makes the counting of erroneous frame counting module 5-5 add 1, the erroneous frame number that in the satellite ground test, needs to add up the operate as normal instruction, this moment, this group instruction no longer continued to transmit downwards.
The 2 transmission fault instructions of fault instruction control computing machine are the G_RS485 fail-safe control command channels by the upper right corner among Fig. 2, deliver in the FPGA field programmable gate array 5 through the 2nd RS422 chip 4 again, the signal flow that the fault instruction enters behind the FPGA field programmable gate array 5 is identical with above-mentioned normal steering order flow process, at last, the data of three sun signal source unit of control are kept at fault data and deposit in the module 5-10.
It is to receive normal data respectively to deposit the data that module 5-4 and fault data are deposited module 5-10 output that data are selected the function of module 5-11, and to three kinds of sun signal source unit selection transmission operate as normal instructions or fault instruction, it selects module 5-11 to control by the switch data output of fault data processing module 5-9 to data, when the fault instruction sends over, the switch data control data of fault data processing module 5-9 selects module 5-11 preferentially to carry out the fault instruction, fault data is sent to three kinds of following sun signal source unit, if there is not the fault instruction, just carry out the operate as normal instruction, it can be guaranteed in the implementation of operate as normal instruction, if fault instruction input is arranged, also preferentially carry out the fault instruction, when the fault instruction is finished, return again and carry out the operate as normal instruction.The setting of fault instruction is the output situation when breaking down for the simulated solar sensor.When instruction is carried out on the operate as normal passage, need to calculate the number of false command on the normal channel; The execution of fault instruction limits if having time, after the time of meeting the requirements of, can go back to normal command mode again.The number of false command passes to fault instruction control computing machine 2 by the fault instruction path on the normal channel.
The major function of FPGA field programmable gate array 5 is the steering orders that receive two control computer among the present invention, makes corresponding judgement, controls each functional module then, makes it produce corresponding output.When normal instruction control computing machine 1 sending controling instruction, the receiver module of FPGA field programmable gate array 5 receives instruction and handles, if but this moment, fault instruction control computing machine 2 also had the fault instruction to send out, then the data of FPGA field programmable gate array 5 inside are selected module 5-11 to control to stop to carry out previous normal instruction then are carried out present fault instruction.Specific as follows:
In satellite closed cycle test in ground is used, the current signal of three kinds of sun signal source unit outputs all can be transferred to signal processor, as shown in Figure 3, be transferred in the central computer again through the current signal after the signal processor, obtain the orientation of satellite with respect to the sun thereby convert these current signals to angle by central computer then.
Embodiment two: present embodiment is described below in conjunction with Fig. 4 and Fig. 7, the difference of present embodiment and embodiment one is that described 0-1 sun signal source unit 6 is made up of the first power supply processing circuit 6-1, voltage transitions chip 6-2, reverse attenuation circuit 6-3, five first relay 6-4 and five tunnel first voltage controlled current source circuit 6-5
The power output end of the first power supply processing circuit 6-1 connects the power input of voltage transitions chip 6-2, the power output end of voltage transitions chip 6-2 connects the power input of reverse attenuation circuit 6-3, the power output end of reverse attenuation circuit 6-3 connects the power input of five first relay 6-4, and the power output end of each first relay 6-4 connects the power input of one tunnel first voltage controlled current source circuit 6-5; The signal input end of five first relay 6-4 connects the 0-1 sun control signal output ends of FPGA field programmable gate array 5.Other composition and annexation are identical with embodiment one.
The data that data select module 5-11 to send comprise the data of three kinds of sun signal source unit, it can be assigned to three kinds of sun data to data accordingly and deposit in the module, each data deposit module respectively corresponding a plurality of output pins of FPGA, wherein 0-1 sun data are deposited the output pin that module 5-12 correspondence 5 FPGA, 0-1 sun data are deposited data in the module 5-12, and to control these 5 pins respectively still be low output for height, and promptly the 0-1 sun data control signal of depositing module 5-12 is converted to the data of controlling these 5 pin high-low levels at last and sends.The control signal of these 5 pins is controlled five first relay 6-4 respectively again, be output as the first corresponding relay 6-4 adhesive of high level with the pin of FPGA, it is added on the corresponding first voltage controlled current source circuit 6-5 voltage of reverse attenuation circuit 6-3 output, make the first voltage controlled current source circuit 6-5 produce corresponding electric current output, the first voltage controlled current source circuit 6-5 mainly is the output switching current, and which face that can be used for the rough calculation satellite has been subjected to the irradiation of the sun.
The composition of the first power supply processing circuit 6-1 is identical with the composition of general supply treatment circuit 9 in the embodiment one in the present embodiment.
The first voltage controlled current source circuit 6-5 as shown in Figure 7, U
iBe control voltage, I
0Be output current, R
LBe load, U
0Be the in-phase input end voltage of output voltage exclusive disjunction amplifier A2, U
3Be the inverting input voltage of operational amplifier A 2, U
1Be the output end voltage of operational amplifier A 1, U
2Inverting input voltage for operational amplifier A 1.Suppose A1, A2 is an ideal operational amplifier, and its positive-negative input end input current is zero, and level is identical.A2 is a voltage follower, and the input current of its positive input terminal can think zero, and electric current all outputs in the load, and U is then arranged
3=U
O,
A1 is the ratio amplifying circuit, then has:
Get R
1=R
2=R
3=R
4=10k can be obtained by above-mentioned formula:
U
i＝U
1-U
O
Then:
This shows that the control voltage U is only depended in the output of electric current
iAnd sampling resistor R
s, and irrelevant with load, can realize constant current output.So, by added voltage U
iWith sampling resistor R
s, can export the electric current of any size in theory.
Embodiment three: below in conjunction with Fig. 5 present embodiment is described, the difference of present embodiment and embodiment two is that described simulated solar signal source unit 7 is made up of analog-digital chip 7-1 and four tunnel second voltage controlled current source circuit 7-2,
The digital signal input end of analog-digital chip 7-1 connects the simulated solar control signal output ends of FPGA field programmable gate array 5, and the analog signal output of analog-digital chip 7-1 connects the power input of four tunnel second voltage controlled current source circuit 7-2.Other composition and annexation are identical with embodiment two.
Simulated solar signal source unit 7 is different with 0-1 sun signal source unit 6, and what simulated solar signal source unit 7 will obtain is the continuous output of electric current.So, adopt analog-digital chip 7-1 at the front end of the second voltage controlled current source circuit 7-2.The implementation of the second voltage controlled current source circuit 7-2 is identical with the first voltage controlled current source circuit 6-5.The electric current output of simulated solar signal source unit 7 can calculate the angle of solar illuminated satellite more accurately than the output of 0-1 sun signal source unit 6.
Embodiment four: present embodiment is described below in conjunction with Fig. 6, the difference of present embodiment and embodiment three is that described digital sun signal source unit 8 produces chip 8-3 by second source treatment circuit 8-1, the second relay 8-2 and electric current and forms
The power output end of second source treatment circuit 8-1 connects the power input of the second relay 8-2, the power output end of the second relay 8-2 connects the power input that electric current produces chip 8-3, and the signal input end of the second relay 8-2 connects the digital sun control signal output ends of FPGA field programmable gate array 5.Other composition and annexation are identical with embodiment three.
The output current of numeral sun signal source unit 8 can accurately calculate the angle of solar illuminated satellite.
Embodiment five: the difference of present embodiment and embodiment four is that the model of described electric current generation chip 8-3 is REF200.Other composition and annexation are identical with embodiment four.
8 the tunnel of the 8 main realizations of digital sun signal source unit is the switch output of 0/-100uA in the present embodiment.Because its output current is less and current value is fixed, so adopt chip REF200 to realize.Current source chip REF200 is the high-precision current source chip of American TI Company, and it can export the electric current of different sizes such as 50uA, 100uA, 200uA.Voltage by-15 volts of second source treatment circuit 8-1 outputs, when the second relay 8-2 adhesive, the termination of REF200 is led to-15V, only needs other end ground connection, the electric current of promptly exportable-100uA adopts REF200 that output current is reached ± accuracy requirement of 10uA.
Embodiment six: the difference of present embodiment and embodiment five is that the model of described analog-digital chip 7-1 is DAC7734.Other composition and annexation are identical with embodiment five.
It is 0 to-100uA continuous output that present embodiment requires the output current of simulated solar signal source unit 7, so front end at the second voltage controlled current source circuit 7-2, adopt high-precision DA chip DAC7734, this chip is 16, can export-10V is to the voltage of+10V.Control the size of its output voltage by FPGA.
Embodiment seven: below in conjunction with Fig. 8 and Fig. 9 present embodiment is described, present embodiment and embodiment two, three, four, five or sixs' difference is that the model of described voltage transitions chip 6-2 is REFO2.Other composition and annexation are identical with embodiment two, three, four, five or six.
0-1 sun signal source unit 6 needs to produce the electric current output of 5 road 0/-35mA in the present embodiment, accuracy requirement ± 1mA, at first make the voltage of the first power supply processing circuit 6-1 output+15V, the voltage of output+5V after voltage transitions chip 6-2REFO2 conversion, again through the voltage of reverse attenuation circuit 6-3 output-2.5V, when the pin of corresponding FPGA is a high level, then control the corresponding first relay 6-4 adhesive, make-2.5V voltage is added on the first voltage controlled current source circuit 6-5 corresponding with it, produces corresponding electric current output then.Adopt REFO2 voltage transitions chip 6-2 can satisfy the requirement of current precision.
Concrete logical design when providing operate as normal below in the FPGA field programmable gate array 5:
Steering order during operate as normal is provided by normal instruction control computing machine 1.This instructs preceding two bytes to be the frame head byte; The byte of back is the data that are used for controlling the output of sun signal source, wherein 0-1 sun signal source and digital sun signal source are all exported with 0/1 current source form, in the byte of their output of control, corresponding position if 0 expression electric current do not export, if 1 expression electric current output.The output of simulated solar is the continuous electric flow, is that every byte is a signless integer 0 to 255 so control the data of their output, equivalent-100uA/256, maximum output-100uA electric current.Last byte of steering order be verification and, be used for judging this byte correctness.
During operate as normal, if the instruction that receives is correct, then take out this several bytes relevant, and the value of corresponding positions is sent to execution module, make it produce corresponding output with sun signal source unit.
After FPGA field programmable gate array 5 is received operate as normal instruction, judge whether the frame head byte correct earlier, and if correctly would receive byte and judge verification and, until verification and correct, this moment is just real at last frame data are received is complete.After receiving instruction, take out the corresponding position in corresponding byte and the byte and send on each functional module, make 0-1 sun signal source unit 6, simulated solar signal source unit 7 and digital sun signal source unit 8 produce corresponding output according to agreement.
Concrete logical design when providing the fail operation state below in the FPGA field programmable gate array 5:
The fail operation instruction is provided by fault instruction control computing machine 2, instruction length is not fixed, the form and the operate as normal instruction of fail operation instruction are roughly the same, just there is a guiding word front of data in the fail operation instruction, there is a time byte back of data, the guiding word is intended for that address search uses, and all there is the guiding word of oneself each sun signal source unit in the fault command protocols.When fault instruction after sending on the bus, each sun signal source unit all will all receive instruction, searches the guiding word then, finds behind the own pairing guiding word relevant parameter with its back to intercept, and exports to each functional module.Added a byte in the back of data in order to the expression fault execution time.This byte is a signless integer, and numerical value is between 0 to 255, and it is 50ms that expression has what cycles, each cycle.
The fault instruction is with the difference of operate as normal instruction, the operate as normal instruction is when closed cycle simulation test, the instruction of sending for the normal duty of analog satellite, with 0-1 sun signal source is example, under normal operation, satellite only has one side or several times are shined upon, and can not all be 1 so issue the data of 0-1 sun signal source in the operate as normal instruction, represents each face of satellite all to be shone like that.And this situation might appear in that the fault mode situation is next, and be 1 entirely so the fault instruction then might be issued the data of 0-1 sun signal source, the working condition when breaking down in order to analog satellite.In addition, the time byte of data back then is the time span that analog satellite breaks down in the fault instruction.
Claims (7)
1. sun sensor simulator that is used for satellite closed cycle simulation test, it is characterized in that: it is made up of normal instruction control computing machine (1), fault instruction control computing machine (2), a RS422 chip (3), the 2nd RS422 chip (4), FPGA field programmable gate array (5), 0-1 sun signal source unit (6), simulated solar signal source unit (7), digital sun signal source unit (8) and general supply treatment circuit (9)
The control signal output ends of normal instruction control computing machine (1) is by the normal instruction control signal input part of a RS422 chip (3) connection FPGA field programmable gate array (5), and the fault instruction control signal input output end of FPGA field programmable gate array (5) connects the fault-signal I/O of fault instruction control computing machine (2) by the 2nd RS422 chip (4); The 0-1 sun control signal output ends of FPGA field programmable gate array (5) connects the signal input end of 0-1 sun signal source unit (6), the simulated solar control signal output ends of FPGA field programmable gate array (5) connects the signal input end of simulated solar signal source unit (7), and the digital sun control signal output ends of FPGA field programmable gate array (5) connects the signal input end of digital sun signal source unit (8); The power input of FPGA field programmable gate array (5) connects the power output end of general supply treatment circuit (9);
FPGA field programmable gate array (5) is by normal data receiver module (5-1), the normal data first-in first-out is deposited module (5-2), normal data processing module (5-3), normal data is deposited module (5-4), erroneous frame counting module (5-5), misdata number sending module (5-6), fault data receiver module (5-7), the fault data first-in first-out is deposited module (5-8), fault data processing module (5-9), fault data is deposited module (5-10), data are selected module (5-11), 0-1 sun data are deposited module (5-12), the simulated solar data deposit module (5-13) and digital sun data are deposited module (5-14) composition
The normal data input end of normal data receiver module (5-1) is the normal instruction control signal input part of FPGA field programmable gate array (5), the normal data output terminal of normal data receiver module (5-1) connects the normal data first-in first-out and deposits the normal data input end of module (5-2), the normal data first-in first-out is deposited the normal data input end of the normal data output terminal connection normal data processing module (5-3) of module (5-2), the normal data output terminal of normal data processing module (5-3) connects normal data and deposits the normal data input end of module (5-4), and the normal data output terminal that normal data is deposited module (5-4) connects the normal data input end that data are selected module (5-11); The misdata input end of the misdata output terminal connection error frame count module (5-5) of normal data processing module (5-3), the misdata input end of the misdata output terminal connection error data number sending modules (5-6) of erroneous frame counting module (5-5), the misdata output terminal of misdata number sending module (5-6) are the fault instruction control signal output parts of FPGA field programmable gate array (5); The fault data input end of fault data receiver module (5-7) is the fault instruction control signal input part of FPGA field programmable gate array (5), the fault data output terminal of fault data receiver module (5-7) connects the fault data first-in first-out and deposits the fault data input end of module (5-8), the fault data first-in first-out is deposited the fault data input end of the fault data output terminal connection fault data processing module (5-9) of module (5-8), the fault data output terminal of fault data processing module (5-9) connects fault data and deposits the fault data input end of module (5-10), the fault data output terminal that fault data is deposited module (5-10) connects the fault data input end that data are selected module (5-11), the switch data output terminal of fault data processing module (5-9) connects the switch data input end that data are selected module (5-11), the switch data control data of fault data processing module (5-9) is selected module (5-11), make preferential execution fault instruction when the fault data input is arranged, data are selected the control data output terminal of module (5-11) to connect 0-1 sun data and are deposited the control data input end of module (5-12), the simulated solar data are deposited the control data input end and the digital sun data of module (5-13) and are deposited the control data input end of module (5-14); The control data output terminal that 0-1 sun data are deposited module (5-12) is the 0-1 sun control signal output ends of FPGA field programmable gate array (5), the control data output terminal that the simulated solar data are deposited module (5-13) is the simulated solar control signal output ends of FPGA field programmable gate array (5), and the control data output terminal that digital sun data are deposited module (5-14) is the digital sun control signal output ends of FPGA field programmable gate array (5).
2. the sun sensor simulator that is used for satellite closed cycle simulation test according to claim 1, it is characterized in that: described 0-1 sun signal source unit (6) is made up of first power supply processing circuit (6-1), voltage transitions chip (6-2), reverse attenuation circuit (6-3), five first relays (6-4) and five tunnel first voltage controlled current source circuits (6-5)
The power output end of first power supply processing circuit (6-1) connects the power input of voltage transitions chip (6-2), the power output end of voltage transitions chip (6-2) connects the power input of reverse attenuation circuit (6-3), the power output end of reverse attenuation circuit (6-3) connects the power input of five first relays (6-4), and the power output end of each first relay (6-4) connects the power input of one tunnel first voltage controlled current source circuit (6-5); The signal input end of five first relays (6-4) connects the 0-1 sun control signal output ends of FPGA field programmable gate array (5).
3. the sun sensor simulator that is used for satellite closed cycle simulation test according to claim 2 is characterized in that: described simulated solar signal source unit (7) is made up of analog-digital chip (7-1) and four tunnel second voltage controlled current source circuits (7-2),
The digital signal input end of analog-digital chip (7-1) connects the simulated solar control signal output ends of FPGA field programmable gate array (5), and the analog signal output of analog-digital chip (7-1) connects the power input of four tunnel second voltage controlled current source circuits (7-2).
4. the sun sensor simulator that is used for satellite closed cycle simulation test according to claim 3, it is characterized in that: described digital sun signal source unit (8) produces chip (8-3) by second source treatment circuit (8-1), second relay (8-2) and electric current and forms
The power output end of second source treatment circuit (8-1) connects the power input of second relay (8-2), the power output end of second relay (8-2) connects the power input that electric current produces chip (8-3), and the signal input end of second relay (8-2) connects the digital sun control signal output ends of FPGA field programmable gate array (5).
5. the sun sensor simulator that is used for satellite closed cycle simulation test according to claim 4 is characterized in that: the model that described electric current produces chip (8-3) is REF200.
6. the sun sensor simulator that is used for satellite closed cycle simulation test according to claim 5 is characterized in that: the model of described analog-digital chip (7-1) is DAC7734.
7. according to claim 2,3,4, the 5 or 6 described sun sensor simulators that are used for satellite closed cycle simulation test, it is characterized in that: the model of described voltage transitions chip (6-2) is REF02.
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