CN101714204A - Multiplier and power factor correction controller with same - Google Patents

Abstract

The invention discloses a multiplier and a power factor correction controller with the same. The multiplier comprises a first differential input level, a second differential input level and an output level, wherein the first differential input level is provided with an amplitude limiter circuit which limits the amplitude of input signals of the multiplier and comprises a first transistor Q1 and a thirteenth transistor Q13; the base of the first transistor Q1 is used as an input end for receiving input voltage signals of the multiplier; the base of the thirteenth transistor Q13 is offset at a direct current voltage Vth of a zero-temperature coefficient, namely, at an amplitude limiting voltage value; and the emitter and the collector of the first transistor Q1 are connected with the emitter and the collector of the thirteenth transistor Q13 respectively. According to the invention, the output of the multiplier with the amplitude limiter circuit is used as a reference voltage of a current sampling and comparing circuit, which can limit the amplitude of the input signals of the multiplier under the condition of not influencing the input signals of a chip and can effectively solve the problem of the total harmonic distortion of a system in high-voltage input.

Description

A kind of multiplier and have the power factor correction controller of this multiplier

Technical field

The present invention relates to a kind of multiplier and have the power factor correction controller of this multiplier, more particularly, relate to a kind of power factor correction controller that has the multiplier of amplitude limiter circuit and have this multiplier.

Background technology

Circuit of power factor correction is widely used in electric power conversion apparatus, its objective is that making the rectification circuit input current is sinusoidal waveform, thereby makes power factor approach 1.

Fig. 1 is an exemplary power factor correcting circuit.As shown in Figure 1, this circuit mainly comprises Boost inductance L 2, switch MOS FET, diode D2, output capacitance C7 and control chip IC1 (power factor correction controller).Control chip IC1 gauge tap MOSFET is under the high-frequency work state, adjust the switch conduction dutycycle according to input voltage and output, making the switching current peak value is sinusoidal envelope, after Boost inductance L 2 electric currents process electromagnetic interface filter L1, C1 and the C2 filtering, input current becomes sinusoidal waveform, and, thereby make power factor approach 1 with the input ac voltage homophase.

Generally, inner integrated error amplifier, multiplier, current sample comparer, MOSFET driving circuit, start-up circuit, zero current detection circuit, reference voltage source and other protection circuit of critical conduction mode power factor correcting control chip.The principle of work of critical conduction mode power factor correcting control chip is as follows: after system powered on, alternating voltage was by producing a DC voltage behind the rectifier bridge.This DC voltage is given the Vcc electric capacity charging of chip through starting resistance.After the voltage on the Vcc electric capacity surpassed the under-voltage protection thresholding of chip, chip was started working.The work of Power Factor Correction Control chip is at first begun by start-up circuit.Start-up circuit provides a small-pulse effect signal to the MOSFET driving circuit in the fixing cycle, and the MOSFET in the system will carry out switch motion with fixing frequency and dutycycle like this.After this, each conducting of MOSFET all be to trigger by the zero current detection circuit, and the shutoff of MOSFET then is to be triggered by current sample and comparator circuit.The reference voltage of current comparator is a sinusoidal signal.Sinusoidal wave current reference is to realize by the output multiplication of input ac voltage and error amplifier

The reference voltage signal of MOSFET shutoff is exactly an AC signal that is subjected to the input exchange signal modulation like this, at every turn.After the electric current of each conducting of MOSFET carried out low frequency filtering, just can obtain sinusoidal current signal, and then promote the power factor of total system.

Cause the total harmonic distortion (THD) of system to mainly contain two sources, one is intermodulation distortion, and another one is the output ripple of error amplifier.General rectification output end all is connected to high-frequency filter capacitor, there is body capacitance in the power switch pipe drain node simultaneously, also there is forward conduction voltage drop in the commutation diode of full-wave rectification, and when all these all can cause the AC-input voltage zero passage of bridge rectifier, full wave rectified signal produced intermodulation distortion.And high-frequency filter capacitor increases along with the increase of input ac voltage in the residual voltage value of input ac voltage during through zero crossing.Therefore, in high input voltage, the THD of system can worsen because of the increase of intermodulation distortion.

So, just need a kind of circuit to compensate AC-input voltage when high, the situation that causes intermodulation distortion to increase.

Summary of the invention

The objective of the invention is to solve the aforementioned problems in the prior, correspondingly, the invention provides a kind of multiplier, comprise first differential input stage, second differential input stage and output stage, wherein first differential input stage has the amplitude limiter circuit of the multiplier input signal being carried out amplitude limit.

In an exemplary embodiment, amplitude limiter circuit comprises the first transistor Q1 and the 13 transistor Q13, the base stage of the first transistor Q1 is brought in as input and is received the multiplier input voltage signal, the base stage of the 13 transistor Q13 is biased in the DC voltage Vth of zero-temperature coefficient, be the limiting voltage value, and the emitter and collector of the first transistor Q1 is connected with the emitter and collector of the 13 transistor Q13 respectively.

Preferably, the first transistor Q1 and the 13 transistor Q13 are PNP transistor.

First differential input stage also can comprise transistor seconds Q2, the 3rd transistor Q3, the 4th transistor Q4, the 11 transistor Q11, the tenth two-transistor Q12 and emitter resistance Ra, the 11 transistor Q11 base stage links to each other with amplitude limiter circuit, first differential input stage becomes the voltage transitions at the 11 transistor Q11 base stage place the differential signal between the emitter of the 3rd transistor Q3 and the 4th transistor Q4, imports second differential input stage then.

Second differential input stage can comprise the 5th transistor Q5, the 6th transistor Q6, the 7th transistor Q7 and the 8th transistor Q8, and second differential input stage receives from the differential signal of first differential input stage and produces the output current that exports output stage to.

Output stage can comprise current mirror, output transistor Q14 and the output resistance Rb that is made of the 9th transistor Q9 and the tenth transistor Q10, and this output stage will be converted to voltage and output from the output current of second differential input stage.

The present invention also provides a kind of power factor correction controller, and it comprises multiplier, error amplifier, current sample comparer, MOSFET driving circuit, start-up circuit, zero current detection circuit, reference voltage source and other the holding circuit with amplitude limiter circuit.

Wherein, error amplifier is used to feed back the output voltage amplitude variation; Multiplier carries out the product coupling with the output signal of error amplifier and the line voltage input signal after dividing potential drop; The current sample comparer is sampled by sampling resistor R9 and voltage that sampling is obtained and the voltage of multiplier output compare, and the result controls the MOSFET driving circuit based on the comparison; Conducting and the shutoff of MOSFET driving circuit control MOSFET; Start-up circuit is used for the work of starting power factor correcting controller; Reference voltage source provides the reference voltage of zero-temperature coefficient for the current sample comparer.

According to the present invention, detect the size of ac input signal by resistance pressure-dividing network, after the ac input signal amplitude surpasses some thresholdings, reduce the output signal of multiplier by multiplier, thereby reduce the reference value of current sample comparer with amplitude limiter circuit.Near the peak value of ac input signal, because the reference value of the sampling circuit of current sample comparer reduces, the output power of system also reduces accordingly.In one-period, the output error of system is amplified by error amplifier, and a part of output power of this that reduces will compensate by the reference value that increases the current sample circuit when AC-input voltage is less than above-mentioned thresholding.Therefore, when AC-input voltage was near zero crossing, the peak value that needs to increase input current compensated the power input that it reduces near peak value.Therefore, the residual voltage on the high-frequency filter capacitor can reduce.The intermodulation distortion of system also can reduce thereupon.

Description of drawings

Fig. 1 shows a kind of typical circuit of power factor correction;

Fig. 2 is existing multiplier circuit;

Fig. 3 is the bias current generating circuit that is used for multiplier shown in Figure 2;

Fig. 4 shows the multiplier with amplitude limiter circuit according to one preferred embodiment of the present invention;

Input current and waveform amplification thereof when Fig. 5 uses existing multiplier when showing the fully loaded 90W of input AC 230V, output;

Fig. 6 shows input AC 230V, input current and waveform amplification thereof when using multiplier according to one preferred embodiment of the present invention when 90W is fully loaded with in output;

Fig. 7 shows input AC 230V, output when using existing multiplier semi-load during 45W input current and waveform amplification thereof;

Fig. 8 shows input AC 230V, output when using according to one preferred embodiment of the present invention multiplier semi-load during 45W input current and waveform amplification thereof;

MULT input terminal voltage and CS end waveform when Fig. 9 uses according to one preferred embodiment of the present invention multiplier when showing the fully loaded 90W of input AC 90V, output;

MULT input terminal voltage and CS end waveform when Figure 10 uses according to one preferred embodiment of the present invention multiplier when showing the fully loaded 90W of input AC 265V, output.

Embodiment

Below, describe in detail according to a preferred embodiment of the invention in conjunction with the accompanying drawings.

Fig. 2 shows existing multiplier circuit, and Fig. 3 is the bias current generating circuit that is used for multiplier shown in Figure 2.

With reference to Fig. 2, because: V _BeN3+ V _BeN1=V _BeN4+ V _BeN2

So,

$\frac{I_1+I_2}{I_1-I_2}=\frac{I_3+I_4}{I_3-I_4}$

I _a＝I ₃+I ₄ 6)

I _b＝I ₁+I ₂ 7)

I _c＝I ₁-I ₂ 8)

$I_3-I_4=\frac{V_A-3V_{\mathrm{be}}}{R_a}-\frac{V_A-3V_{\mathrm{be}}-V_{\mathrm{Mult}}}{R_a}=\frac{V_{\mathrm{Mult}}}{R_a}$

Can derive from top formula:

$\frac{I_b}{I_c}=\frac{I_a}{\frac{V_{\mathrm{Mult}}}{R_a}},$ Therefore, the output voltage V refcs of multiplier can be expressed as:

$\mathrm{Vrefcs}=K\·V_{\mathrm{Mult}}\·\frac{R_b}{R_a}\·\frac{I_b}{I_a}$

Wherein, Ib is the bias current of multiplier, with reference to Fig. 3, and the size of Ib electric current, can try to achieve by following calculating:

Because, V _BeN4+ V _BeN2=V _BeN5+ V _BeN3

So, $\frac{\mathrm{kT}}{q}\ln \frac{I_{\mathrm{out}}}{\mathrm{Is}}+\frac{\mathrm{kT}}{q}\ln \frac{I_{\mathrm{out}}}{3\mathrm{Is}}=\frac{\mathrm{kT}}{q}\ln \frac{I_4}{2\mathrm{Is}}+\frac{\mathrm{kT}}{q}\ln \frac{I_b}{\mathrm{Is}}$

Then, $I_b=\frac{2}{3}\&CenterDot;\frac{I_{\mathrm{out}}^2}{{\mathrm{<figure-callout\; id="4"\; label="I"\; filenames="H2009101697479E00021.png"\; state="\{\{state\}\}">I</figure-callout>}}_4}$

Again because: $I_2=\frac{1}{3}{I}_{\mathrm{out}}$

${\mathrm{<figure-callout\; id="4"\; label="I"\; filenames="H2009101697479E00021.png"\; state="\{\{state\}\}">I</figure-callout>}}_4=4{\mathrm{<figure-callout\; id="2"\; label="I"\; filenames="H2009101697479E00021.png"\; state="\{\{state\}\}">I</figure-callout>}}_2+\frac{1}{6}{I}_3,$ $I_1=\frac{1}{2}{I}_{\mathrm{bias}}$

Can separate I3 out

$I_3=\frac{1}{5}{I}_1{e}^{\frac{I_1\&CenterDot;R_d}{U_T}}$

So,

$I_b=\frac{4\&CenterDot;{\left(\frac{V_{\mathrm{error}}}{R_c}\right)}^2}{8\&CenterDot;\frac{V_{\mathrm{error}}}{R_c}+\frac{1}{5}{I}_1{e}^{\frac{I_{\mathrm{bias}}\&CenterDot;R_d}{2U_T}}}$

So, total output voltage of multiplier can be expressed as:

$\mathrm{Vrefcs}=K\&CenterDot;\frac{R_b}{R_a}\&CenterDot;\frac{1}{I_a}\&CenterDot;V_{\mathrm{Mult}}\&CenterDot;I_b$

$\&DoubleRightArrow;\mathrm{Vrefcs}=K\&CenterDot;\frac{R_b}{R_a}\&CenterDot;\frac{1}{I_a}\&CenterDot;V_{\mathrm{Mult}}\&CenterDot;\frac{\frac{1}{2}\&CenterDot;\frac{V_{\mathrm{<figure-callout\; id="1"\; label="error\; R\; c"\; filenames="H2009101697479E00011.png,H2009101697479E00021.png"\; state="\{\{state\}\}">error</figure-callout>}}}{R_c}}{1+\frac{\mathrm{\&Delta;I}}{8\&CenterDot;\frac{V_{\mathrm{error}}}{R_c}}}$

$\&DoubleRightArrow;\mathrm{Vrefcs}=\frac{1}{2}\&CenterDot;K\&CenterDot;\frac{R_b}{R_a\&CenterDot;R_c}\&CenterDot;\frac{1}{1+\frac{\mathrm{\&Delta;I}}{8\&CenterDot;\frac{V_{\mathrm{error}}}{R_c}}}\&CenterDot;\frac{1}{I_a}\&CenterDot;V_{\mathrm{Mult}}\&CenterDot;V_{\mathrm{error}}$

So the gain of multiplier is:

$\mathrm{Gain}=\frac{1}{2}\&CenterDot;K\&CenterDot;\frac{R_b}{R_a\&CenterDot;R_c}\&CenterDot;\frac{1}{I_a}\&CenterDot;\frac{1}{1+\frac{\mathrm{\&Delta;I}}{8\&CenterDot;\frac{V_{\mathrm{error}}}{R_c}}}$

Learnt by top formula: the output voltage of multiplier is approximately equal to the voltage of MULT and the product of COMP-Vref.

VMULT=KVac, wherein Vac is an AC-input voltage.

It needs to be noted, multiplier circuit as shown in Figures 2 and 3 has further detailed description in Chinese patent application 200710045858.X and 200520122350.1, the content of these two pieces of patented claims all is incorporated into this by reference, constitute the application's a part, for easy,, repeat no more the concrete syndeton between transistor among Fig. 2 and Fig. 3 and the resistance at this.

In order under the situation of high AC-input voltage, to reduce the output signal of multiplier, promptly the multiplier input signal is carried out amplitude limitation.Fig. 4 shows the multiplier with amplitude limiter circuit according to one preferred embodiment of the present invention.

With reference to Fig. 4, amplitude limiter circuit comprises the first transistor Q1 and the 13 transistor Q13, the base stage of the first transistor Q1 receives the multiplier input voltage signal as input end Mult, and the base stage of the 13 transistor Q13 is biased in the DC voltage Vth of a zero-temperature coefficient, it is the limiting voltage value, and the emitter and collector of the first transistor Q1 is connected with the emitter and collector of the 13 transistor Q13 respectively, constitutes a pair of difference pipe.Be pointed out that, though the first transistor Q1 and the 13 transistor Q13 shown in Figure 4 be PNP transistor, this is not restrictive, it also can adopt NPN transistor according to concrete application.The output signal of this amplitude limiter circuit, be that the voltage of the emitter of transistor Q1 and Q13 two pipes mainly contains the low end decision of base voltage, its amplitude adds lower that among Mult end input signal and the bias voltage Vth for the forward conduction voltage of transistor BE knot.Like this, when the voltage of Mult end surpassed Vth, the input signal of multiplier was an internal bias voltage Vth.Internal bias voltage Vth is a voltage signal with zero-temperature coefficient characteristic, so limiting voltage can not change because of the change of temperature.Thereby the output signal of this circuit is when VMult＞Vth, and its amplitude is limited to Vth+Vbe.

As shown in Figure 4, except amplitude limiter circuit, first differential input stage also comprises transistor seconds Q2, the 3rd transistor Q3, the 4th transistor Q4, the 11 transistor Q11, the tenth two-transistor Q12 and emitter resistance Ra, the 11 transistor Q11 base stage links to each other with amplitude limiter circuit, first differential input stage becomes the voltage transitions at the 11 transistor Q11 base stage place the differential signal between the emitter of the 3rd transistor Q3 and the 4th transistor Q4, imports second differential input stage then.

Second differential input stage comprises the 5th transistor Q5, the 6th transistor Q6, the 7th transistor Q7 and the 8th transistor Q8, and second differential input stage receives from the differential signal of first differential input stage and produces the output current that exports output stage to.

Output stage comprises current mirror, output transistor Q14 and the output resistance Rb that is made of the 9th transistor Q9 and the tenth transistor Q10, and this output stage will be converted to voltage and output from the output current of second differential input stage.

About the concrete syndeton between these transistors and the resistance, since consistent with existing circuit as shown in Figures 2 and 3, so no longer describe in detail.

Multiplier according to one preferred embodiment of the present invention as shown in Figure 4 can be applied in the power factor correction controller, and can be embodied as control chip IC1, and then is applied in as shown in Figure 1 the circuit of power factor correction.

Another preferred embodiment according to the present invention; a kind of power factor correction controller is provided, and it has error amplifier, according to multiplier of the present invention, current sample comparer, MOSFET driving circuit, start-up circuit, zero current detection circuit, reference voltage source and other protection circuit.What adopt except multiplier is that remaining circuit parts and existing in full accord are so be not described in detail in this according to the multiplier with amplitude limiter circuit of the present invention.

It is pointed out that power factor correction controller according to the present invention may be embodied as integrated circuit (IC) chip, in this chip, for example:

Error amplifier: INV pin (pin 1) connects the negative terminal of error amplifier, and the positive termination reference voltage (2.5V) of error amplifier is used to feed back output voltage amplitude and changes, and its output terminal is COMP pin (pin 2);

Multiplier with amplitude limiter circuit: the voltage (that is, the line voltage input signal after dividing potential drop) of COMP pin (pin 2) and MULT pin (pin 3) is carried out the product coupling, and output signal inserts the negative terminal of current sample comparer;

Current sample comparer: by the sample current amplitude of CS pin (pin 4) of the voltage magnitude on the R9, and the anode of access current sample comparer, through and relatively have output voltage and the voltage magnitude on the R9 of the multiplier of amplitude limiter circuit, the shutoff of MOSFET driving circuit is controlled in its output;

MOSFET driving circuit: the conducting and the shutoff of the outer switch mosfet pipe of driving chip;

Start-up circuit: detect the voltage of VCC pin (pin 8), when it is higher than certain amplitude, the output enable signal makes chip operation;

The zero current detection circuit: the electric current on the magnetic test coil L2, when electric current was zero, by ZCD pin (pin 5) input chip, and control MOSFET driving circuit was opened;

Reference voltage source: the reference voltage that zero-temperature coefficient is provided for the current sample comparer of chip internal.

Below, further describe in conjunction with Fig. 5-10 multiplier with amplitude limiter circuit according to the present invention is applied in the circuit shown in Figure 1 to compare the beneficial technical effects that is realized with using existing traditional multiplier.

Input current and waveform amplification thereof when Fig. 5 uses existing multiplier when being the fully loaded 90W of input AC 230V, output, the Dead Time of input current is 648 μ s as seen from the figure, and at this moment the THD of system is 14.28%, and power factor is 0.9759.Input current and waveform amplification thereof when Fig. 6 uses according to the multiplier with amplitude limiter circuit of the present invention when being the fully loaded 90W of input AC 230V, output, the Dead Time of input current shortens to 529 μ s, the content of third harmonic is reduced to 5.83% from 12.85%, at this moment the THD of system is reduced to 7.60%, and power factor brings up to 0.9823.

Fig. 7 is input AC 230V, output input current and the waveform amplification thereof when using existing multiplier semi-load during 45W, and the Dead Time of input current is 1.12ms as seen from the figure, and at this moment the THD of system is 12.06%, and power factor is 0.9561.Fig. 8 is input AC 230V, output 45W output semi-load input current and the waveform amplification thereof when using according to the multiplier with amplitude limiter circuit of the present invention, the Dead Time of input current shortens to 1.02ms, the content of third harmonic from 10.23% be reduced to 6.92% at this moment the THD of system be reduced to 9.31%, power factor brings up to 0.9598.

According to the present invention, output with multiplier of amplitude limiter circuit is used for to the current sample comparator circuit as reference voltage, can be under the state that does not influence the chip input signal, the amplitude of restriction multiplier input signal, the problem of system's total harmonic distortion in the time of can effectively solving the high pressure input.

Described in this instructions is preferred specific embodiment of the present invention, and above embodiment is only in order to illustrate technical scheme of the present invention but not limitation of the present invention.All those skilled in the art are under this invention's idea by the available technical scheme of logical analysis, reasoning, or a limited experiment, all should be within as the scope of the present invention that claim defined.

Claims (6)

1. a multiplier comprises first differential input stage, second differential input stage and output stage, it is characterized in that, described first differential input stage has the amplitude limiter circuit of the multiplier input signal being carried out amplitude limit.

2. multiplier as claimed in claim 1, it is characterized in that, described amplitude limiter circuit comprises the first transistor (Q1) and the 13 transistor (Q13), the base stage of the first transistor (Q1) is brought in as input and is received the multiplier input voltage signal, the base stage of the 13 transistor (Q13) is biased in the DC voltage Vth of zero-temperature coefficient, be the limiting voltage value, and the emitter and collector of the first transistor (Q1) is connected with the emitter and collector of the 13 transistor (Q13) respectively.

3. multiplier as claimed in claim 2 is characterized in that, the first transistor (Q1) and the 13 transistor (Q13) are PNP transistor.

4. multiplier as claimed in claim 2 is characterized in that,

Described first differential input stage also comprises transistor seconds (Q2), the 3rd transistor (Q3), the 4th transistor (Q4), the 11 transistor (Q11), the tenth two-transistor (Q12) and emitter resistance (Ra), the 11 transistor (Q11) base stage links to each other with described amplitude limiter circuit, first differential input stage becomes the voltage transitions at the 11 transistor (Q11) base stage place the differential signal between the emitter of the 3rd transistor (Q3) and the 4th transistor (Q4), imports described second differential input stage then;

Described second differential input stage comprises the 5th transistor (Q5), the 6th transistor (Q6), the 7th transistor (Q7) and the 8th transistor (Q8), and second differential input stage receives from the differential signal of first differential input stage and produces the output current that exports described output stage to;

Described output stage comprises current mirror, output transistor (Q14) and the output resistance (Rb) that is made of the 9th transistor (Q9) and the tenth transistor (Q10), and this output stage will be converted to voltage and output from the output current of second differential input stage.

5. power factor correction controller that has as each described multiplier among the claim 1-4; it is characterized in that described power factor correction controller further comprises error amplifier, current sample comparer, MOSFET driving circuit, start-up circuit, zero current detection circuit, reference voltage source and other holding circuit.

6. power factor correction controller as claimed in claim 5 is characterized in that,

Described error amplifier is used to feed back output voltage amplitude to be changed;

Described multiplier carries out the product coupling with the output signal of described error amplifier and the line voltage input signal after dividing potential drop;

Described current sample comparer is sampled by sampling resistor (R9) and voltage that sampling is obtained and the voltage of described multiplier output compare, and the result controls described MOSFET driving circuit based on the comparison;

Conducting and the shutoff of described MOSFET driving circuit control MOSFET;

Described start-up circuit is used for the work of starting power factor correcting controller;

Described reference voltage source provides the reference voltage of zero-temperature coefficient for described current sample comparer.

Images