CN101706763B - Method and device for serialization and deserialization - Google Patents
Method and device for serialization and deserialization Download PDFInfo
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Abstract
The invention discloses a method for serialization and deserialization, comprising the following steps: the number N of channels is taken as variable, a frame format encoding serial data is set; a local reception end determines the frame head of the received serial data according to the set frame format and converts the serial data into N-bit parallel data; the parallel data is analyzed according to the set frame format so as to obtain a link state and the N-bit parallel data is output; a local transmission end encodes the local parallel data according to the set frame format, and the parallel data corresponding to the frame format is output according to the link state resulted from the analysis of the local reception end; and the parallel data is converted into the serial data and frequency-doubling high-speed clock is utilized to output the serial data. The invention further discloses a device for serialization and deserialization; by adopting the method and the device, chips with the single-chip SERDES function can be used for the mutual conversion between parallel signals and serial signals of the different number of channels, and meanwhile, consumptive cost of users is reduced.
Description
Technical Field
The present invention relates to serial communication technologies, and in particular, to a method and an apparatus for serial communication and deserialization.
Background
With the development of communication technology, people's demand for information traffic is increasing, and the traditional parallel interface technology becomes a bottleneck for further increasing the data transmission rate. With the increase of the processing speed of chips and the development and wide application of high-speed optical fiber communication technology, the serial communication technology, i.e., serializer/deserializer (SERDES), is gradually replacing the conventional parallel interface technology and becomes the popular high-speed interface technology at present.
The SERDES technology is a time division multiplexing and point-to-point communication technology, in which, at the transmitting end, multi-channel low-speed parallel signals are converted into high-speed serial signals according to a certain protocol or framing method, and the high-speed serial signals are transmitted out through optical fibers or other media, and the receiving end converts the received high-speed serial signals into low-speed parallel signals. The signal sent by the sending end carries a frame indication signal required in serial-parallel conversion, and the frame indication signal is used for a receiving end to solve the frame header of the serial signal, and the receiving end firstly solves the frame header of the serial signal according to a protocol or a framing method according to the sending end, then decomposes the serial signal according to bits of the frame header, and solves the parallel signal corresponding to each channel. The point-to-point serial communication technology fully utilizes the characteristics of high capacity, high chip processing speed and the like of the existing transmission media, thereby being widely applied to the industries of communication, industrial design and the like.
Currently, many chip manufacturers have developed various chips implementing SERDES functionality for serial-to-parallel conversion of data links with different N: 1 ratios, namely: the method is used for the interconversion of the low-speed parallel signals and the high-speed serial signals with different channel numbers. Wherein N is the number of channels, N is more than or equal to 2 and is usually an even number; the N: 1 ratio can be: 8: 1, or 10: 1, or 16: 1, etc., for interconversion of low-speed parallel signals and high-speed serial signals for 8-lane, or 10-lane, or 16-lane, etc. However, a certain chip with SERDES function produced by a chip manufacturer can only satisfy the serial-to-parallel conversion of a data link with a certain fixed ratio, and does not support the serial-to-parallel conversion of a data link with other ratios, for example, a chip with SERDES function is used for the serial-to-parallel conversion of an 8: 1 data link, if a user wants to change an 8-channel parallel signal into a 10-channel parallel signal, the user can only buy a chip with SERDES function of 10: 1 again, and the original chip with SERDES function of 8: 1 cannot be used any more, which means that the applicable range of the chip with SERDES function in the prior art is not flexible enough, and the consumption cost of the user is very high.
Disclosure of Invention
In view of the above, the main objective of the present invention is to provide a method and an apparatus for serialization and deserialization, so that a chip with a single SERDES function can be used for interconversion between parallel signals and serial signals with different channel numbers, thereby reducing the consumption cost of users.
In order to achieve the purpose, the technical scheme of the invention is realized as follows:
the invention provides a method for serialization and deserialization, which comprises the following steps:
setting a frame format for coding serial data by taking the channel number N as a variable; the local receiving end positions the received serial data out of the frame head according to the set frame format and converts the serial data into N-bit parallel data; analyzing the parallel data according to a set frame format to obtain a link state, and outputting N-bit parallel data;
the local sending end encodes the local parallel data according to a set frame format, and outputs the parallel data of a corresponding frame format according to the link state analyzed by the local receiving end; and converting the parallel data into serial data, and outputting the serial data by using the high-speed clock after frequency multiplication.
Wherein, before locating the received serial data out of the frame header, the method further comprises: and extracting the clock in the serial data transmitted by the other party to be used as the sampling clock of the serial data for converting the serial data into the parallel data.
Wherein before outputting the N-bit parallel data, further comprising: and adjusting the local clock by referring to the clock in the serial data transmitted by the opposite side to ensure that the local clock is synchronous with the clock in the serial data transmitted by the opposite side.
The converting the parallel data into serial data and outputting the serial data by using the frequency-doubled high-speed clock specifically comprises:
converting local N-bit parallel data and four-bit control domain data into serial data, multiplying the frequency of a clock to be N +4 times of the local parallel data clock, and transmitting the serial data corresponding to the high-speed clock to the opposite side.
The invention also provides a device for serialization and deserialization, which comprises: the device comprises a setting module, a frame serial-parallel conversion module, a frame format decoding module, a frame format coding module, a frame parallel-serial conversion module and a clock frequency doubling module; wherein,
the setting module is used for setting a frame format for coding the serial data by taking the channel number N as a variable;
the frame serial-parallel conversion module is used for positioning the received serial data out of a frame head according to the frame format set by the setting module, converting the serial data into N-bit parallel data and sending the data to the frame format decoding module;
the frame format decoding module is used for analyzing the parallel data according to the frame format set by the setting module to obtain a link state, informing the frame format coding module and outputting N-bit parallel data;
the frame format coding module is used for coding the local parallel data according to the frame format set by the setting module, outputting the parallel data corresponding to the frame format according to the link state obtained by the analysis of the frame format decoding module and sending the parallel data to the frame parallel-serial module;
the frame parallel-serial module is used for converting parallel data into serial data and outputting the serial data by using a frequency-doubled high-speed clock; and the clock frequency doubling module is used for doubling the frequency of the local clock into a high-speed clock and sending the high-speed clock to the frame parallel-serial module.
The device further comprises a clock recovery module, a frame serial-parallel conversion module and a frame parallel-serial conversion module, wherein the clock recovery module is used for extracting a clock in serial data transmitted by the opposite side and transmitting the clock to the frame serial-parallel conversion module; correspondingly, the frame serial-to-parallel module is specifically configured to convert serial data into N-bit parallel data according to a set frame format by using a clock in the serial data.
The device further comprises a clock adjusting module which is used for adjusting the local clock to be synchronous with the clock in the serial data transmitted by the opposite party by referring to the clock in the serial data transmitted by the opposite party before the frame format decoding module outputs the N-bit parallel data.
The invention provides a method and a device for serialization and deserialization.A frame format for coding serial data is set by taking the channel number N as a variable; the local receiving end positions the received serial data out of the frame head according to the set frame format and converts the serial data into N-bit parallel data; the local receiving end analyzes the parallel data according to the set frame format to obtain a link state and outputs N-bit parallel data; the local sending end encodes the local parallel data according to a set frame format, and outputs the parallel data of a corresponding frame format according to the link state analyzed by the local receiving end; and the local sending end converts the parallel data into serial data and outputs the serial data by utilizing the high-speed clock after frequency multiplication. The invention sets the channel number N as a variable for the realization process of the serial and de-serial processes, can realize the interconversion between the parallel signals and the serial signals with different channel numbers, saves the research and development cost of developers, and further reduces the consumption cost of users. In addition, when analyzing the parallel data to obtain the link state, the invention can realize the monitoring of any received data, thereby achieving the effect of monitoring the link state between the opposite side and the local, and being convenient for maintaining the link in time.
Drawings
FIG. 1 is a schematic diagram of a serial data to parallel data conversion implementation process in the serial and deserializing method of the present invention;
FIG. 2 is a schematic flow chart illustrating the process of converting parallel data into serial data according to the serial and deserializing method of the present invention;
FIG. 3 is a schematic diagram of the serial and deserialized device structure of the present invention.
Detailed Description
The basic idea of the invention is: setting a frame format for coding serial data by taking the channel number N as a variable; the local receiving end positions the received serial data out of a frame head according to the set frame format, converts the serial data into N-bit parallel data, analyzes the parallel data according to the set frame format to obtain a link state and outputs the N-bit parallel data;
the local sending end encodes the local parallel data according to a set frame format, and outputs the parallel data of a corresponding frame format according to the link state analyzed by the local receiving end; and converting the parallel data into serial data, and outputting the serial data by using the high-speed clock after frequency multiplication.
In the invention, N is the number of channels, and N is more than or equal to 2; the frame format for encoding serial data includes: positioning frames, data frames and error frames; accordingly, the link status may be: the beginning of a reset, the receipt of a positioning frame, the receipt of a data frame, the receipt of an error frame, etc.
The invention is described in further detail below with reference to the figures and the embodiments.
The method for serialization and deserialization of the invention is mainly carried out in a Field Programmable Gate Array (FPGA) module, fig. 1 is a schematic diagram of the realization process of converting serial data into parallel data in the method for serialization and deserialization of the invention, as shown in fig. 1, the process comprises the following steps:
step 101: setting a frame format for coding serial data by taking the channel number N as a variable;
specifically, the FPGA module sets a frame format for encoding serial data by using the number of channels N as a variable, where the frame format for encoding serial data has three types, including: the data transmission method comprises the steps of positioning frames, data frames and error frames, wherein each frame comprises a data field and a control field, the control field is four bits of control signals, the data field is N bits, and each frame comprises N +4 bits, so that the transmission rate of serial data is calculated to be N +4 times of parallel data.
The following lists describe the three frame formats in detail, respectively, and the positioning frame is shown in table 1:
TABLE 1
As shown in table 1, there are two positioning frames, namely a positioning frame a and a positioning frame B, and it can be seen that the positioning frame a is a signal having the same frequency as the parallel data and a duty ratio of 50%, and the positioning frame B is a signal having the same frequency as the parallel data and a duty ratio of not 50% but a higher level than a lower level by one bit.
The data frames are four in number, as shown in table 2:
| data field | Control domain | |
| Truth value | D0～D(N-1) | 1101 |
| Get the contrary | /(D0～D(N-1)) | 0010 |
| Truth value | D0～D(N-1) | 1011 |
| Get the contrary | /(D0～D(N-1)) | 0100 |
TABLE 2
Here, "/" indicates that bits are inverted, four kinds of data frames are used for alternate transmission of data, and the problem that the receiving end cannot recover the clock when the data is 0 or 1 in succession is prevented.
The error frames are eight kinds, as shown in table 3:
TABLE 3
Wherein "x" represents 0 or 1; the one to eight indicate the kinds of error frames, that is, eight kinds in total.
In the invention, a sending end of an opposite side sends serial data with a frame format of a positioning frame A first, a phase-locked loop sends the serial data with a format of a positioning frame B after being in a stable state, namely, the local receiving end sends the serial data with the frame format of the positioning frame A before determining the position of a frame header, and sends the serial data with the frame format of the positioning frame B to the opposite side after determining the position of the frame header so as to inform the opposite side that the process of framing the frame header is finished locally, the phase-locked loop sends the serial data with the frame format of a data frame after being stabilized again, and in the process of sending the serial data with the frame format of the data frame, the serial data with the.
Step 102: the local receiving end positions the received serial data out of the frame head according to the set frame format;
specifically, the receiving end in the local FPGA module locates the received serial data in the frame header according to the set frame format, and here, as can be seen from the three frame formats set in step 101, only when the other side sends the locating frame, the position of the frame header in the data stream can be determined. Because there is only one falling edge and one rising edge in the data stream when the opposite side sends the positioning frame, and for the positioning frames of two formats, the positions of the rising edges are fixed between the second bit and the third bit of the control field, the invention uses the position of the rising edge to perform frame positioning, and the frame header is located at the position of the third bit after the rising edge. If the frame header is not located, the local receiving end will continuously search for the rising edge of the serial data until the frame header is located.
Furthermore, before positioning the frame head, the invention also comprises extracting the clock in the serial data sent by the other party as the sampling clock of the serial data for converting the serial data into the parallel data. Wherein the clock is the clock of the other party.
Step 103: the local receiving end converts the serial data into N-bit parallel data;
the method specifically comprises the following steps: after the frame header of the serial data is positioned by a receiving end in the local FPGA module, the clock in the serial data is utilized to convert the subsequently received serial data into N-bit parallel data according to the set frame format, namely the data consisting of the N-bit parallel data and the four-bit control domain data.
In the invention, before establishing the links of both sides, the specific numerical value of N in the serial-parallel conversion of the N: 1 data link is firstly determined, and then the serial data and the parallel data are mutually converted so as to establish the links of both sides.
Step 104: the local receiving end analyzes the parallel data according to the set frame format to obtain a link state and informs the local transmitting end, and then outputs N-bit parallel data;
the method specifically comprises the following steps: the receiving end in the local FPGA module analyzes the data composed of the converted N-bit parallel data and the four-bit control domain data to obtain the current link state and notify the local transmitting end, for example: if the frame format corresponding to the data composed of the N-bit parallel data and the four-bit control field data is a data frame, the current link state is as follows: receiving a data frame, and then outputting N-bit parallel data; if the frame format corresponding to the data composed of the N-bit parallel data and the four-bit control field data is a positioning frame, the current link state is as follows: receiving a positioning frame, and then outputting N-bit parallel data; if the frame format corresponding to the data composed of the N-bit parallel data and the four-bit control field data is an error frame, the current link state is as follows: receiving an error frame, and then outputting N-bit parallel data; before the link between the two parties is established, the current link state is as follows: when the reset starts, the local sending end sends a positioning frame to the opposite side to start establishing the link, and in addition, the local receiving end returns to the reset starting state to reestablish the link after receiving the error frame.
Here, the output parallel data is not all valid data, and the output parallel data is valid data only when the link state is that a data frame is received, and if a positioning frame is received, the data corresponding to the positioning frame does not contain data information to be transmitted, and therefore is not valid data; if the error frame is received, the data information corresponding to the error frame is error information, and the transmission is proved to be an error code, so that the data is not valid data.
Furthermore, before outputting the N-bit parallel data, the local clock needs to be adjusted with reference to the opposite side clock, so as to ensure that the local clock is synchronized with the opposite side clock.
In the invention, if the error frame is received, the step 102 is returned to reestablish the link between the local and the opposite side, thereby achieving the effect of monitoring the link state all the time and being convenient for maintaining the link between the local and the opposite side in time.
FIG. 2 is a schematic flow chart illustrating the process of converting parallel data into serial data according to the serial and deserializing method of the present invention;
step 201: the local sending end encodes the local parallel data according to the set frame format;
the method specifically comprises the following steps: and the sending end in the local FPGA module encodes the local N-bit parallel data and the four-bit control domain data according to three frame formats corresponding to the link state analyzed by the local receiving end.
Step 202: outputting parallel data of a corresponding frame format according to the link state analyzed by the local receiving end;
here, the sending end in the local FPGA module sends parallel data in different frame formats according to the link state obtained by analyzing the parallel data by the local receiving end in step 104, and outputs the parallel data in the positioning frame format if the current link state is reset start or if the link state obtained by analyzing the parallel data is received positioning frame; if the link state obtained by analyzing the parallel data is that the data frame is received, the parallel data in the data frame format is output, so that the link between the local side and the opposite side is established in two directions. More specifically, when the link obtained by analysis is in a reset starting state or before a phase-locked loop of a receiving end is in a stable state, sending parallel data with a frame format of a positioning frame A; when a phase-locked loop of a receiving end is in a stable state and before a link receives a data frame, sending parallel data with a frame format of a positioning frame B; and when the link state obtained by analysis is the received data frame, sending the parallel data with the frame format of the data frame.
Here, the reason why the local transmitting end outputs the parallel data in the corresponding frame format based on the link status analyzed by the local receiving end is as follows: the method of the invention is mainly used for the establishment process of the link between the local and the opposite side, therefore, the data frame format sent to the opposite side by the local sending end is corresponding to the data frame format received by the local receiving end, so as to facilitate the establishment of the link between the two sides.
Step 203: the local sending end converts the parallel data into serial data and outputs the serial data by utilizing the high-speed clock after frequency multiplication;
the method specifically comprises the following steps: the sending end in the local FPGA module converts local N-bit parallel data and four-bit control domain data into serial data, multiplies the frequency of the clock by a high-speed clock which is N +4 times of the local parallel data clock, and then transmits the serial data corresponding to the high-speed clock to the opposite side.
Fig. 3 is a schematic structural diagram of a serial and deserialized device of the present invention, as shown in fig. 2, the device includes: the device comprises a setting module, a frame serial-parallel conversion module, a frame format decoding module, a frame format coding module, a frame parallel-parallel serial-parallel conversion module and a clock frequency doubling module, wherein the setting module, the frame serial-parallel conversion module, the frame format decoding module, the frame format coding module, the frame parallel-parallel serial-parallel conversion module and the clock frequency doubling module are integrated in a Field Programmable Gate Array (FPGA) module except the clock frequency doubling module; wherein,
the setting module is used for setting a frame format for coding the serial data by taking the channel number N as a variable;
the frame serial-parallel conversion module is used for positioning the received serial data out of a frame head according to the frame format set by the setting module, converting the serial data into N-bit parallel data and sending the data to the frame format decoding module;
the frame format decoding module is used for analyzing the parallel data according to the frame format set by the setting module to obtain a link state, informing the frame format coding module and outputting N-bit parallel data;
the frame format coding module is used for coding the local parallel data according to the frame format set by the setting module, outputting the parallel data corresponding to the frame format according to the link state obtained by the analysis of the frame format decoding module and sending the parallel data to the frame parallel-serial module;
the frame parallel-serial module is used for converting parallel data into serial data and outputting the serial data by utilizing a frequency-doubled high-speed clock;
and the clock frequency doubling module is used for doubling the frequency of the local clock into a high-speed clock and sending the high-speed clock to the frame parallel-serial module.
The device further comprises a clock recovery module, a frame serial-to-parallel conversion module and a frame parallel-to-serial conversion module, wherein the clock recovery module is used for extracting a clock in the serial data transmitted by the opposite side and transmitting the clock to the frame serial-to-parallel conversion module; correspondingly, the frame serial-to-parallel module is specifically configured to convert serial data into N-bit parallel data according to a set frame format by using a clock in the serial data.
The device further comprises a clock adjusting module which is used for adjusting the local clock to be synchronous with the opposite side clock by referring to the opposite side clock before the frame format decoding module outputs the N-bit parallel data.
The above description is only exemplary of the present invention and should not be taken as limiting the scope of the present invention, and any modifications, equivalents, improvements, etc. that are within the spirit and principle of the present invention should be included in the present invention.
Claims (7)
1. A method of serialization and deserialization, the method comprising:
setting a frame format for coding serial data by taking the channel number N as a variable; the local receiving end positions the received serial data out of the frame head according to the set frame format and converts the serial data into N-bit parallel data; analyzing the parallel data according to a set frame format to obtain a link state, and outputting N-bit parallel data;
the local sending end encodes the local parallel data according to a set frame format, and outputs the parallel data of a corresponding frame format according to the link state analyzed by the local receiving end; and converting the parallel data into serial data, and outputting the serial data by using the high-speed clock after frequency multiplication.
2. The method according to claim 1, wherein the locating the received serial data before the frame header further comprises: and extracting the clock in the serial data transmitted by the other party to be used as the sampling clock of the serial data for converting the serial data into the parallel data.
3. The method for serialization and deserialization according to claim 1 or 2, wherein before outputting the N-bit parallel data, further comprising: and adjusting the local clock by referring to the clock in the serial data transmitted by the opposite side to ensure that the local clock is synchronous with the clock in the serial data transmitted by the opposite side.
4. The method for serialization and deserialization according to claim 1 or 2, wherein the converting parallel data into serial data and outputting the serial data by using the high-speed clock after frequency multiplication is specifically as follows:
converting local N-bit parallel data and four-bit control domain data into serial data, multiplying the frequency of a clock to be N +4 times of the local parallel data clock, and transmitting the serial data corresponding to the high-speed clock to the opposite side.
5. An apparatus for serialization and deserialization, comprising: the device comprises a setting module, a frame serial-parallel conversion module, a frame format decoding module, a frame format coding module, a frame parallel-serial conversion module and a clock frequency doubling module; wherein,
the setting module is used for setting a frame format for coding the serial data by taking the channel number N as a variable;
the frame serial-parallel conversion module is used for positioning the received serial data out of a frame head according to the frame format set by the setting module, converting the serial data into N-bit parallel data and sending the data to the frame format decoding module;
the frame format decoding module is used for analyzing the parallel data according to the frame format set by the setting module to obtain a link state, informing the frame format coding module and outputting N-bit parallel data;
the frame format coding module is used for coding the local parallel data according to the frame format set by the setting module, outputting the parallel data corresponding to the frame format according to the link state obtained by the analysis of the frame format decoding module and sending the parallel data to the frame parallel-serial module;
the frame parallel-serial module is used for converting parallel data into serial data and outputting the serial data by using a frequency-doubled high-speed clock;
and the clock frequency doubling module is used for doubling the frequency of the local clock into a high-speed clock and sending the high-speed clock to the frame parallel-serial module.
6. The device for serial and deserialization according to claim 5, wherein the device further comprises a clock recovery module for extracting a clock from the serial data transmitted by the other party and transmitting the clock to the frame serial-to-parallel module;
correspondingly, the frame serial-to-parallel module is specifically configured to convert serial data into N-bit parallel data according to a set frame format by using a clock in the serial data.
7. The apparatus for serialization and deserialization according to claim 5 or 6, wherein the apparatus further comprises a clock adjusting module for adjusting a local clock to be synchronized with a clock in the serial data transmitted by the counterpart with reference to the clock in the serial data transmitted by the counterpart before the frame format decoding module outputs the N-bit parallel data.
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| WO2012119561A1 (en) * | 2011-03-08 | 2012-09-13 | 浙江彩虹鱼通讯技术有限公司 | Device, method, serializer/deserializer and processor for signal processing |
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| CN112910467B (en) * | 2019-12-03 | 2022-09-09 | 烽火通信科技股份有限公司 | NRZ coding circuit, encoder and high-speed interface circuit |
| CN116257484A (en) * | 2021-12-10 | 2023-06-13 | 华为技术有限公司 | Data transmission chip and electronic equipment |
| CN115080477B (en) * | 2022-05-30 | 2024-01-30 | 杭州初灵信息技术股份有限公司 | Method and system for serial communication |
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| US6112276A (en) * | 1997-10-10 | 2000-08-29 | Signatec, Inc. | Modular disk memory apparatus with high transfer rate |
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| US6288656B1 (en) * | 1999-12-21 | 2001-09-11 | Lsi Logic Corporation | Receive deserializer for regenerating parallel data serially transmitted over multiple channels |
| US7286572B2 (en) * | 2003-01-10 | 2007-10-23 | Sierra Monolithics, Inc. | Highly integrated, high-speed, low-power serdes and systems |
| CN100440875C (en) * | 2004-05-13 | 2008-12-03 | 中兴通讯股份有限公司 | A baseband data transmission apparatus and frame synchronization method thereof |
| CN1798117A (en) * | 2004-12-22 | 2006-07-05 | 华为技术有限公司 | Synchronization method and synchronization circuit for serial signal in high speed |
| TWI360964B (en) * | 2006-11-08 | 2012-03-21 | Finisar Corp | Serialization/deserialization for use in optoelect |
| CN101706763B (en) * | 2009-11-20 | 2011-11-30 | 中兴通讯股份有限公司 | Method and device for serialization and deserialization |
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| US6112276A (en) * | 1997-10-10 | 2000-08-29 | Signatec, Inc. | Modular disk memory apparatus with high transfer rate |
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| JP特开2002-217742A 2002.08.02 |
| JP特开2008-283331A 2008.11.20 |
| JP特开平8-163081A 1996.06.21 |
| JP特开平8-335127A 1996.12.17 |
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| CN101706763A (en) | 2010-05-12 |
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