CN101582454B - Double bit U-shaped memory structure and manufacturing method thereof - Google Patents
Double bit U-shaped memory structure and manufacturing method thereof Download PDFInfo
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- CN101582454B CN101582454B CN2008101002032A CN200810100203A CN101582454B CN 101582454 B CN101582454 B CN 101582454B CN 2008101002032 A CN2008101002032 A CN 2008101002032A CN 200810100203 A CN200810100203 A CN 200810100203A CN 101582454 B CN101582454 B CN 101582454B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- 238000007667 floating Methods 0.000 claims abstract description 56
- 239000000758 substrate Substances 0.000 claims description 42
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 17
- 238000000034 method Methods 0.000 claims description 12
- 238000010276 construction Methods 0.000 claims description 9
- 239000000377 silicon dioxide Substances 0.000 claims description 7
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- 229910052814 silicon oxide Inorganic materials 0.000 claims 3
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 238000005516 engineering process Methods 0.000 description 12
- 150000002500 ions Chemical class 0.000 description 4
- 238000002360 preparation method Methods 0.000 description 4
- 239000002019 doping agent Substances 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 239000000047 product Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical group [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 2
- 230000005641 tunneling Effects 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- UMVBXBACMIOFDO-UHFFFAOYSA-N [N].[Si] Chemical compound [N].[Si] UMVBXBACMIOFDO-UHFFFAOYSA-N 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
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Abstract
The invention discloses a double bit U-shaped memory structure and a manufacturing method thereof. A memory disclosed in the invention is structurally characterized in that the bottom of a floating grid is in a U shape and is embedded in a base. The double bit U-shaped memory structure comprises the base, a control grid, floating grids, a first dielectric layer, a second dielectric layer, a third dielectric layer, a local doped region and a source electrode/drain electrode doped region, wherein the control grid is arranged on the surface of the base; the floating grids are arranged at both sides of the control grid, wherein each floating grid has a U-shaped bottom which is embedded in the base; the first dielectric layer is arranged between the control grid and the base; the second dielectric layer is arranged among the U-shaped bottoms of the floating grids and the base; the third dielectric layer is arranged among the control grid and the floating grids; the local doped region is arranged on a U-shaped floating grid channel under the floating grids; and the source electrode/drain electrode doped region is arranged in the base at one side of the floating grids.
Description
Technical field
The present invention relates to structure of a kind of memory and preparation method thereof, double-bit memory component structure of particularly a kind of floating grid with U type bottom and preparation method thereof.
Background technology
Flash memory has the characteristic non-volatile and read-write that can repeat to erase, add that transmission fast, so application is very extensive, make recent many portable products all adopt flash memory, in many information, communication and consumption electronic products, all it is treated as necessary element.For light and handy and high-quality electronic element products are provided, promote the element integrated level of flash memory and the emphasis that quality just becomes the information industry development.
See also Fig. 1, Fig. 1 is the structural representation of known dual-bit flash memory device unit.As shown in Figure 1, known flash memory cells comprises that substrate 10, control grid 12 is located in the substrate 10, two floating grid 14a, 14b are located at control grid 12 respectively both sides, dielectric layer 16 are located between control grid 12 and the substrate 10 and between floating grid 14a, 14b and the substrate 10, dielectric layer 18 be located at control between grid 12 and floating grid 14a, the 14b, substrate that source electrode 20 is positioned at floating grid 14a, 14b one side, pouch-type doped region 22 be in abutting connection with source electrode 20, and floating grid raceway groove 24.
The structure of above-mentioned known flash memory has the floating grid 14a, the 14b that are formed on control grid 12 two sides, can store the dibit data.Along with the size of element design is constantly dwindled, the floating grid raceway groove constantly shortens, yet the length of floating grid raceway groove has very big influence for the usefulness of flash memory.Generally speaking, the floating grid raceway groove is long more, and the usefulness of flash memory is good more.Can promote integrated level though dwindle component size, can cause the floating grid raceway groove of flash memory to shorten, cause element efficiency to descend, in addition, also can make the technology allowance reduce.
Moreover, its pouch-type doped region is to utilize heating process to make dopant lateral diffusion back form after injecting in the known flash memory, because the pouch-type doped region is in abutting connection with source electrode, make the pouch-type doped region be vulnerable to the influence of source electrode, cause the problem of technology controlling and process.Therefore, memory construction and technology that development makes new advances, and promote the usefulness of flash memory and improve the direction that the technology controlling and process problem is present semiconductor industry effort.
Summary of the invention
In view of this, the invention provides a kind of memory construction and preparation method thereof, utilization is arranged on the U-shaped floating grid bottom in the substrate, can when dwindling, element increase the length of floating grid raceway groove, promote the usefulness of flash memory, and the pouch-type doped region that local doped region replaces known technology is set under floating grid, can effectively avoids the problem of above-mentioned technology controlling and process.In addition, memory construction of the present invention can promote the phenomenon of the drain leakage (GIDL) of gate induced, increases the flash memory writing speed.
According to a preferred embodiment of the invention, a kind of memory cell structure of the present invention comprises: substrate, the control grid, be located at this substrate surface, floating grid, be located at the both sides of this control grid, wherein this floating grid has U-shaped bottom and is absorbed in this substrate, first dielectric layer, between this control grid and this substrate, second dielectric layer, between this U-shaped bottom and this substrate of this floating grid, the 3rd dielectric layer, between this control grid and this floating grid, local doped region, be located at the U-shaped floating grid raceway groove under this floating grid, and source electrode, be located in this substrate of a side of this floating grid.
According to a preferred embodiment of the invention, an aspect of of the present present invention provides a kind of manufacture method of flash memory component, include: substrate is provided, comprising first groove and second groove is located in this substrate, then, local doped region is formed on the bottom in this first groove and this second groove, then, form the surface that first dielectric layer covers this first groove, after the surface and this substrate surface of this second groove, form first conductive layer and fill up and cover this first groove and this second groove, then, form second dielectric layer in these first conductive layer both sides, then, form in this first conductive layer that is opened between this first groove and this second groove, at last, form in doped region this substrate between this first groove and this second groove.
Description of drawings
Fig. 1 is the structural representation of known dual-bit flash memory device unit.
Fig. 2 to 7 illustrates the manufacture method schematic diagram of memory component according to the preferred embodiment of the invention.
Description of reference numerals
10 substrates, 12 control grids
14 floating grids, 16,18 dielectric layers
20 source electrode, 22 pouch-type doped regions
50 substrates of 24 floating grid raceway grooves
52 dielectric layers, 54 hard mask layers
56 grooves, 58 local doped region
60 regional 62 dielectric layers
64 conductive layers, 66 grooves
68 dielectric layers, 70 conductive layers
72 openings, 74 floating grids
76 source electrode, 80 floating grid raceway grooves
57U type bottom
Embodiment
The manufacture method schematic diagram of the memory component that Fig. 2 to Fig. 7 is according to one preferred embodiment of the present invention to be illustrated.As shown in Figure 2, at first provide substrate 50, be covered with the hard mask layer 54 of dielectric layer 52 and patterning on it, wherein dielectric layer 52 comprises silica, and hard mask layer 54 comprises silicon nitride.
As shown in Figure 3, utilize hard mask layer 54 as mask, in substrate 50, form groove 56, wherein groove 56 has U type bottom 57, then in the substrate 50 around the U of the groove 56 type bottom 57, form local doped region 58, then utilize mask (figure does not show) to remove the hard mask 54 and the dielectric layer 52 that are positioned at zone 60, make that the substrate 50 in zone 60 is exposed to the open air out.
As shown in Figure 4, in the surface of groove 56 and the surface of zone 60 substrate 50, form dielectric layer 62, as tunneling dielectric layer.According to a preferred embodiment of the invention, dielectric layer 62 can utilize high-temperature oxidation to form.Then, form conductive layer 64 again, and make conductive layer 64 fill up groove 56.Then, utilize grinding technics to make the surface of conductive layer 64 and the surface of hard mask 54 trim.
As shown in Figure 5, remove remaining hard mask 54, form groove 66.Then, form dielectric layer 68, make dielectric layer 68 conformably cover the surface of conductive layer 64 and groove 66.According to a preferred embodiment of the invention, dielectric layer 68 can be oxide layer-nitrogen silicon layer-oxide layer (ONO) dielectric layer structure, its generation type for example is to utilize high-temperature oxidation (high temperature oxidation earlier, HTO) make oxide layer, utilize Low Pressure Chemical Vapor Deposition (LPCVD) to make the nitrogen silicon layer again.
As shown in Figure 6, dielectric layer 68 is partly removed, only stay the dielectric layer 68 that is positioned at groove 66 both sides.According to another preferred embodiment of the invention, the dielectric layer 68 that is positioned at groove 66 bottoms can also keep, and the dielectric layer 68 that only need will be positioned at the conductive layer top removes and gets final product.
As shown in Figure 7, in groove 66, insert conductive layer 70 as the control grid, then, use aforementioned usefulness to remove to be positioned at the mask (figure does not show) of the hard mask 54 in zone 60, in conductive layer 70, form opening 72, expose part dielectric layer 62, to form floating grid 74.Then, utilize ion to flow into and form source electrode 76 in the below substrate 50 of opening 72.When operation, can form floating grid raceway groove 80 in the U of floating grid 74 type bottom periphery.So far, memory component of the present invention is promptly finished, and can form dielectric layer in the both sides in opening 72 in follow-up technology afterwards, and remove the dielectric layer 62 of opening 72 bottoms, is to form in the opening 72 contact plunger then.
Fig. 7 illustrated is according to a preferred embodiment of the invention memory cell structure, memory component of the present invention comprises substrate 50, control grid 70, be located at substrate 50 surfaces, floating grid 74, be located at the both sides of control grid 70, wherein floating grid 74 has U-shaped bottom 57 and is embedded in the substrate 50, dielectric layer 52 is as the control gate dielectric, between control grid 70 and substrate 50, dielectric layer 62 is as tunneling dielectric layer, between the U-shaped bottom 57 and substrate 50 of floating grid 74, dielectric layer 68, between control grid 70 and floating grid 74, local doped region 58, be located at around the U-shaped floating grid raceway groove 80 under the floating grid 74 and source electrode 76, be located in the substrate 50 of a side of floating grid 74.Aforesaid dielectric layer 52 can be that silica and silica-silicon-nitride and silicon oxide structure (ONO) are formed, and for example, silica is as lower floor, and silica-silicon-nitride and silicon oxide structure then covers on the silica; Perhaps can also only be constituted by silica.
According to the preferred embodiment of the present invention, if the dopant in the source electrode 76 is the P type, boron for example, then the dopant in the local doped region 58 then is the N type, arsenic for example, wherein utilize the ion injection to form in the local doped region 58, employed ion dose is about 5E13, and ion energy is about 50KeV.
The function of local doped region 58 of the present invention mainly is to replace the pouch-type doped region in the known technology, be used for avoiding the source electrode and the threshold voltage difference that drains and abnormal perforation phenomenon takes place and increase the element switch state of switch storage, the advantage of local doped region 58 is not to be vulnerable in the technology influence of source electrode, and preferable technology controlling and process can be provided.
In addition, floating grid 74 of the present invention has the U type bottom 57 that embeds substrate, can increase and shorten along with the element integrated level compared to its floating grid raceway groove of traditional memory (seeing also Fig. 1), floating grid 74 of the present invention but can also provide longer floating grid raceway groove 80 when utmost point intensity increases, and the drain leakage flow phenomenon (GIDL) that can increase gate induced promotes and writes efficient, thus, memory can have better usefulness and also can promote the technology allowance.
The above only is the preferred embodiments of the present invention, and all equalizations of doing according to claim of the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (11)
1. memory cell structure comprises:
Substrate;
The control grid is located at this substrate surface;
Floating grid is located at the both sides of this control grid, and wherein this floating grid has the U-shaped bottom and is embedded in this substrate;
First dielectric layer is between this control grid and this substrate;
Second dielectric layer is between this U-shaped bottom and this substrate of this floating grid;
The 3rd dielectric layer is between this control grid and this floating grid;
Local doped region, be located at U-shaped floating grid raceway groove under this floating grid around; And
Source electrode is located in this substrate of a side of this floating grid.
2. memory construction as claimed in claim 1, wherein this first dielectric layer is a silica.
3. memory construction as claimed in claim 1, wherein this first dielectric layer is made up of silica and silica-silicon-nitride and silicon oxide.
4. memory construction as claimed in claim 1, wherein the 3rd dielectric layer comprises silica-silicon-nitride and silicon oxide.
5. memory construction as claimed in claim 1, when wherein this source electrode was the P type, this local doped region was the N type.
6. memory construction as claimed in claim 1, wherein second dielectric layer between this floating grid and this substrate is a U-shaped.
7. memory construction as claimed in claim 1, wherein the bottom of this local doped region is a U-shaped.
8. the manufacture method of a memory component comprises:
Substrate is provided, comprises first groove and second groove and be located in this substrate, wherein the bottom of this first groove is that the bottom of U type and this second groove is the U type;
Local doped region is formed on the bottom in this first groove and this second groove;
Form the surface that first dielectric layer covers this first groove, surface and this substrate surface of this second groove;
Form first conductive layer and fill up and cover this first groove and this second groove;
Form second dielectric layer in these first conductive layer both sides;
Form in this first conductive layer that is opened between this first groove and this second groove; And
Form in doped region this substrate between this first groove and this second groove.
9. the manufacture method of memory component as claimed in claim 8 after forming this opening, forms contact plunger in this opening.
10. the manufacture method of memory component as claimed in claim 8, wherein this second dielectric layer comprises silica-silicon-nitride and silicon oxide.
11. the manufacture method of memory component as claimed in claim 8, wherein this second dielectric layer defines sunk area in these conductive layer both sides, this manufacture method after forming this second dielectric layer with this opening of formation before, other includes following steps:
Insert second conductive layer in this sunk area; And
Grind away this second conductive layer partly, this second dielectric layer to expose this first conductive layer.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2008101002032A CN101582454B (en) | 2008-05-16 | 2008-05-16 | Double bit U-shaped memory structure and manufacturing method thereof |
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| CN2008101002032A CN101582454B (en) | 2008-05-16 | 2008-05-16 | Double bit U-shaped memory structure and manufacturing method thereof |
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| Publication Number | Publication Date |
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| CN101582454A CN101582454A (en) | 2009-11-18 |
| CN101582454B true CN101582454B (en) | 2011-03-16 |
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| CN103515391A (en) * | 2012-06-29 | 2014-01-15 | 南亚科技股份有限公司 | Nonvolatile memory unit and manufacturing method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5411905A (en) * | 1994-04-29 | 1995-05-02 | International Business Machines Corporation | Method of making trench EEPROM structure on SOI with dual channels |
| CN1333565A (en) * | 2000-06-30 | 2002-01-30 | 株式会社东芝 | Semiconductor device and making method thereof |
| CN1536675A (en) * | 2003-04-07 | 2004-10-13 | ��洢������˾ | Two-way fetching/programming nonvolatile floating gate storage unit with independent controllable control gate, its array and formation method |
| US6940121B2 (en) * | 2000-11-02 | 2005-09-06 | Infineon Technology Ag | Semiconductor memory cell |
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2008
- 2008-05-16 CN CN2008101002032A patent/CN101582454B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5411905A (en) * | 1994-04-29 | 1995-05-02 | International Business Machines Corporation | Method of making trench EEPROM structure on SOI with dual channels |
| CN1333565A (en) * | 2000-06-30 | 2002-01-30 | 株式会社东芝 | Semiconductor device and making method thereof |
| US6940121B2 (en) * | 2000-11-02 | 2005-09-06 | Infineon Technology Ag | Semiconductor memory cell |
| CN1536675A (en) * | 2003-04-07 | 2004-10-13 | ��洢������˾ | Two-way fetching/programming nonvolatile floating gate storage unit with independent controllable control gate, its array and formation method |
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| CN101582454A (en) | 2009-11-18 |
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