CN101572554B - Method and device for generating code-rate-compatible LDPC codes and HARQ scheme - Google Patents
Method and device for generating code-rate-compatible LDPC codes and HARQ scheme Download PDFInfo
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Abstract
The invention relates to the technical field of channel coding of mobile communication, in particular to a method and a device for generating code-rate-compatible quasi-cyclic LDPC codes. The method comprises the following steps: obtaining the low rate requirements of a system and the degree distribution of high rate quasi-cyclic LDPC codes and designing the degree distribution of low rate quasi-cyclic LDPC codes; determining check nodes needing decomposing and variation nodes needing extension in the high rate quasi-cyclic LDPC codes during constructing the low rate quasi-cyclic LDPC codes; constructing a check matrix of the low rate quasi-cyclic LDPC codes based on a construction method and the limitations of the low rate quasi-cyclic LDPC codes on the check part structure of the check matrix; weaving the obtained check bits of the quasi-cyclic LDPC codes and obtaining rate-compatible codes through deleting. The embodiment of the invention further provides a device for implementing the method, and provides a HARQ scheme based on the rate-compatible LDPC codes.
Description
Technical field
The present invention relates to the channel coding technology field of mobile communication, particularly method and the device of a kind of generating code-rate-compatible LDPC codes and generation HARQ scheme.
Background technology
Low-density parity check (LDPC, low density parity check) code is a kind of linear block codes that Gallager proposed in 1962, because in its check matrix " 1 " number less, therefore be called as low-density parity check code, then again proposed in 1996 also to be improved by Mackay.Except representing the LDPC code that with check matrix can also scheme with Tanner (seeing Fig. 1) expression LDPC code, Tanner figure and check matrix are directly corresponding, the limit of being connected by variable node, check-node and connection consists of.Each check-node z
iCorresponding to the delegation of check matrix, each variable node x
iRow corresponding to check matrix.When a certain bit in the code word is included in a certain check equations, namely corresponding position is 1 o'clock in the check matrix, has line between the check-node among Fig. 1 and the variable node.For each node, the limit number that is attached thereto is called this degree of node number.
The LDPC code is a kind of channel coding technology that adopts at present more function admirable, and its main feature is to support iterative decoding, so decoding performance is limit near Shannon capacity.The LDPC code has lower decoding complexity, and supports that parallel decoding improves the decoder throughput, is a kind of more excellent channel coding schemes in the high-speed communication system of future generation therefore.
Use at present the more quasi-cyclic LDPC code that is based on the cyclic shift matrices design, its check matrix H
M * nAs shown in Figure 2, n is code length, and m is the number of check bit in the code word, and the information bit number is k=n-m.P wherein
I, jCyclic shift matrices or the null matrix of z * z.Check matrix H
M * nCan be regarded as by size is m
b* n
bThe biradical check matrix H
bZ expands according to spreading factor, wherein n=z * n
b, m=z * m
b, z is integer.During the biradical matrix-expand, the right cyclic shift matrices of element 1 usefulness z * z is replaced, and element 0 usefulness z * z zero battle array is replaced.H
M * nIn each circulating unit battle array can by its to the right the cyclic shift amount determine, can be incorporated into biradical check matrix information and circular shift information in the basic check matrix, be designated as H
BmH
BmAnd H
bDimension is identical, H
BmDirectly by H
bObtain: with H
bIn 0 change-1 into, be defined as z * z zero battle array, 1 element changes the cyclic shift amount into.By H
BmCan directly obtain H by the spreading factor expansion
M * nWhen constructing quasi-cyclic LDPC code, take basic check matrix as the basis, construct to optimize the ring distribution by the position of definite cyclic shift matrices and the size of cyclic shift amount.
In order to support HARQ (Hybrid Automatic Repeat request mixed automatic retransfer) scheme, employed quasi-cyclic LDPC code based on the cyclic shift matrices design is a kind of rate compatible codes, be that high code check quasi-cyclic LDPC code code word bits is included in the quasi-cyclic LDPC code code word bits of low code check, only need a generating apparatus and a decoder just can realize the coding﹠decoding of different code checks.
Utilize extended method structure code-rate-compatible quasi-cyclic LDPC code in the prior art, by increasing more check bit, by the low code check quasi-cyclic LDPC code of high code check quasi-cyclic LDPC code structure, adopt in the low code check quasi-cyclic LDPC code that extended method obtains corresponding to the number of degrees of the check-node of high code check quasi-cyclic LDPC code and can not adjust flexibly, the performance of quasi-cyclic LDPC code has to be optimized.Decomposition method is a kind ofly to be decomposed into the method that two low check-nodes of the number of degrees are constructed low code check quasi-cyclic LDPC code by the check-node that the number of degrees of high code check quasi-cyclic LDPC code are high, and generally can not increase becate, even also might reduce becate, improve the length of enclosing of low code check quasi-cyclic LDPC code.Adopt in the low code check quasi-cyclic LDPC code that said method obtains corresponding to the number of degrees of the variable node of high code check quasi-cyclic LDPC code and can not adjust flexibly, the performance of coding has to be optimized.
Summary of the invention
The embodiment of the invention provides a kind of generation method of code-rate-compatible quasi-cyclic low-density parity check code, guarantee when using the method to obtain in the low code check quasi-cyclic low-density parity check code, the number of degrees corresponding to the check-node of high code check quasi-cyclic low-density parity check code can reduce along with the reduction of code check by decomposition method, the number of degrees corresponding to the variable node of high code check quasi-cyclic low-density parity check code can increase along with the reduction of code check by extended method, said method comprising the steps of:
The low code check of acquisition system requires and the degree of high code check quasi-cyclic low-density parity check code distributes, and the degree of the low code check quasi-cyclic low-density parity check code of design distributes;
Distribute and the degree of high code check quasi-cyclic low-density parity check code distributes variable node that need in the high code check quasi-cyclic low-density parity check code in the basic check matrix process of the low code check quasi-cyclic low-density parity check code of structure to determine the basic check-node that decomposes and needs to expand according to the degree of described low code check quasi-cyclic low-density parity check code;
Based on the restriction to biradical check matrix check part structure of building method and low code check quasi-cyclic low-density parity check code, the check matrix of the low code check quasi-cyclic low-density parity check code of structure.
The embodiment of the invention also further provides a kind of method that generates code-rate-compatible quasi-cyclic low-density parity check code, and described method comprises:
The low code check of acquisition system requires and the degree of high code check quasi-cyclic low-density parity check code distributes, and the degree of the low code check quasi-cyclic low-density parity check code of design distributes;
Distribute and the degree of high code check quasi-cyclic low-density parity check code distributes variable node that need in the high code check quasi-cyclic low-density parity check code in the basic check matrix process of the low code check quasi-cyclic low-density parity check code of structure to determine the check-node that decomposes and needs to expand according to the degree of described low code check quasi-cyclic low-density parity check code;
Based on the restriction to biradical check matrix check part structure of building method and low code check quasi-cyclic low-density parity check code, the basic check matrix of the low code check quasi-cyclic low-density parity check code of structure;
Obtain low code check quasi-cyclic low-density parity check code and delete remaining operation, obtain the quasi-cyclic low-density parity check code of code-rate-compatible.
The embodiment of the invention also provides a kind of quasi-cyclic low-density parity check code coder simultaneously, and described encoder comprises:
The test matrix generation unit, for the check matrix of design quasi-cyclic low-density parity check code, wherein the check part structure of the biradical check matrix of low code check quasi-cyclic low-density parity check code is:
Wherein, the number of degrees that first check bit is corresponding are 4, h
b(0)=1, h
b(m
b'-1)=1, h
b(k)=1,0＜k＜(m
b'-1), m
b'＞m
b, m
bThe high code check quasi-cyclic low-density parity check code of ' expression is through corresponding check-node number after decomposing, number of degrees span corresponding to check bit that the check bit of remaining high code check quasi-cyclic low-density parity check code correspondence and decomposition method produce is 2≤i≤3, i represents number of degrees value corresponding to check bit, and the number of degrees corresponding to check bit that produce by extended method are 1.
The embodiment of the invention provides a kind of mixed automatic retransferring method based on code-rate-compatible quasi-cyclic low-density parity check code simultaneously, and described method is:
Determine check bit to be sent original position in the check bit of low code check quasi-cyclic low-density parity check code code word and the particular location of check bit in the check bit of low code check quasi-cyclic low-density parity check code code word to be sent, pass through formula
F
k＝(SPID
k*L
k)mod(ParityLen)
Determine check bit to be sent original position in the check bit of whole low code check quasi-cyclic low-density parity check code code word, wherein SPID
kExpression attached bag indicated value, L
kRepresent check bit number to be sent, ParityLen represents the total number of check bit in the low code check quasi-cyclic low-density parity check code code word, and k represents number of retransmissions, passes through formula
S
k，i＝(F
k+i)mod(ParityLen)，i＝0，1，L L
k-1
Determine check bit to be sent particular location in the check bit of low code check quasi-cyclic low-density parity check code code word;
Send the packet that the information bit connection forms with the check bit of determining according to above-mentioned formula.
Further, provide a kind of method of reseptance based on code-rate-compatible quasi-cyclic low-density parity check code mixed automatic retransfer, described method comprises:
Determine in the receive data bag data corresponding to check bit in the check bit of low code check quasi-cyclic low-density parity check code code word original position and corresponding to the particular location of data in the check bit of low code check quasi-cyclic low-density parity check code code word of check bit, pass through formula
F
k＝(SPID
k*L
k)mod(ParityLen)
Determine to receive in the packet original position of data in the check bit of low code check quasi-cyclic low-density parity check code code word corresponding to check bit, wherein SPID
kExpression attached bag indicated value, L
kThe check bit number that expression sends, ParityLen represent the total number of check bit in the low code check quasi-cyclic low-density parity check code code word, and k represents number of retransmissions, passes through formula
S
k，i＝(F
k+i)mod(ParityLen)，i＝0，1，L L
k-1
Determine in the receive data bag particular location of data in the check bit of low code check quasi-cyclic low-density parity check code code word corresponding to check bit;
The packet that receives is deciphered, if correct transmission of decoding confirmed feedback signal, if decipher incorrect then send signal unconfirmed.
Further, provide a kind of low-density parity check code generating apparatus, described generating apparatus comprises:
Degree distribution determining unit, degree distribution situation based on high code check quasi-cyclic low-density parity check code, the degree of the low code check quasi-cyclic low-density parity check code of design distributes, and the check part of the biradical check matrix of described high code check quasi-cyclic low-density parity check code has the biconjugate corner structure;
Computing unit, be used for that degree according to described low code check quasi-cyclic low-density parity check code distributes and the degree of high code check quasi-cyclic low-density parity check code distributes, variable node that need in the high code check quasi-cyclic low-density parity check code in the basic check matrix process of the low code check quasi-cyclic low-density parity check code of structure to determine the check-node that decomposes and needs to expand;
The check matrix generation unit, based on the restriction to biradical check matrix check part structure of building method and low code check quasi-cyclic low-density parity check code, the basic check matrix of the low code check quasi-cyclic low-density parity check code of structure.
Another kind of code-rate-compatible quasi-cyclic low-density parity check code generating apparatus, described generating apparatus comprises:
Degree distribution determining unit, degree distribution situation based on high code check quasi-cyclic low-density parity check code, the degree of the low code check quasi-cyclic low-density parity check code of design distributes, and the check part of the biradical check matrix of described high code check quasi-cyclic low-density parity check code has the biconjugate corner structure;
Computing unit, be used for that degree according to described low code check quasi-cyclic low-density parity check code distributes and the degree of high code check quasi-cyclic low-density parity check code distributes, variable node that need in the high code check quasi-cyclic low-density parity check code in the basic check matrix process of the low code check quasi-cyclic low-density parity check code of structure to determine the check-node that decomposes and needs to expand;
The check matrix generation unit, based on the restriction to biradical check matrix check part structure of building method and low code check quasi-cyclic low-density parity check code, the basic check matrix of the low code check quasi-cyclic low-density parity check code of structure;
Delete remaining operating unit, the different code check quasi-cyclic low-density parity check codes that the acquisition system needs for low code check quasi-cyclic low-density parity check code is deleted remaining operation, thereby the quasi-cyclic low-density parity check code of acquisition code-rate-compatible.
The embodiment of the invention also provides a kind of transmitting terminal device, and described transmitting terminal device comprises:
Position calculation unit, it is used for passing through formula
F
k＝(SPID
k*L
k)mod(ParityLen)
Determine check bit to be sent original position in the check bit of low code check quasi-cyclic low-density parity check code code word, wherein SPID
kExpression attached bag indicated value, L
kRepresent check bit number to be sent, ParityLen represents the total number of check bit in the low code check quasi-cyclic low-density parity check code code word, and k represents number of retransmissions, passes through formula
S
k，i＝(F
k+i)mod(ParityLen)，i＝0，1，L L
k-1
Determine check bit to be sent particular location in the check bit of low code check quasi-cyclic low-density parity check code code word;
Transmitting element is used for the packet that sends information bit and form according to the check bit that above-mentioned formula is determined.
A kind of receiving end device further is provided, and described device comprises:
Position calculation unit, it is used for passing through formula
F
k＝(SPID
k*L
k)mod(ParityLen)
Determine in the receive data bag original position of data in the check bit of low code check quasi-cyclic low-density parity check code code word corresponding to check bit, wherein SPID
kExpression attached bag indicated value, L
kThe check bit number that expression sends, ParityLen represent the total number of check bit in the quasi-cyclic low-density parity check code code word of low code check, and k represents number of retransmissions, passes through formula
S
k，i＝(F
k+i)mod(ParityLen)，i＝0，1，L L
k-1
Determine to receive in the packet particular location of data in the check bit of low code check quasi-cyclic low-density parity check code code word corresponding to check bit;
Decoding unit is used for the packet that receives is deciphered;
The feedback signal transmitting element be used for to send and to feed back signal to transmitting terminal, if correct transmission of decoding confirmed feedback signal, if decipher incorrect then send signal unconfirmed.
The method and apparatus that adopts the embodiment of the invention to provide, utilize associating decomposition method and extended method to construct the quasi-cyclic low-density parity check code of code-rate-compatible, when using the method to obtain in the low code check code, the number of degrees corresponding to the check-node of high code check quasi-cyclic low-density parity check code can reduce along with the reduction of code check by decomposition method, can increase along with the reduction of code check by extended method corresponding to the number of degrees of the variable node of high code check quasi-cyclic low-density parity check code; Simultaneously delete remaining mode based on the check bit deinterleaving method with optimization, then more than deleting, obtain the quasi-cyclic low-density parity check code of different code checks, and then generated the quasi-cyclic low-density parity check code of code-rate-compatible.Proposed corresponding support HARQ scheme on the quasi-cyclic low-density parity check code basis that designs based on above method, the transmitting-receiving two-end control overhead is less, and has improved the performance of whole system.
Description of drawings
Fig. 1 is the Tanner figure expression of LDPC code;
Fig. 2 is the check matrix structure chart of quasi-cyclic LDPC code;
Fig. 3 is that the embodiment of the invention generates LDPC code method flow chart;
Fig. 4 is the check part structure chart of the biradical check matrix of high code check quasi-cyclic LDPC code among the embodiment;
Fig. 5 is the check part structure chart of the biradical check matrix of the low code check quasi-cyclic LDPC code that constructs among the embodiment;
Fig. 6 is low code check quasi-cyclic LDPC code codeword structure among the embodiment;
The interweave low code check code codeword structure of rear acquisition of Fig. 7;
The HARQ flow chart that Fig. 8 designs for the embodiment of the invention;
Fig. 9 provides the LDPC code coder one embodiment block diagram for the embodiment of the invention;
Figure 10 also provides LDPC code generating apparatus another embodiment block diagram for the embodiment of the invention;
Figure 11 provides a kind of transmitting terminal device block diagram for the embodiment of the invention;
Figure 12 provides a kind of receiving end device block diagram for the embodiment of the invention.
Embodiment
The embodiment of the invention provides the method for a kind of generation quasi-cyclic low-density parity check (LDPC, low densityparity check) code.The method is by high code check quasi-cyclic low-density parity check LDPC code design code-rate-compatible quasi-cyclic LDPC code, at first by the basic check matrix of the high code check quasi-cyclic LDPC code basic check matrix according to the required low code check quasi-cyclic LDPC code of associating decomposition method and extended method design system, and expand to the check matrix of low code check quasi-cyclic LDPC code by spreading factor; Then, it is as follows that the check bit of designed low code check quasi-cyclic code is carried out interlace operation: designed low code check quasi-cyclic LDPC code is carried out piecemeal corresponding to the check bit that check bit and the decomposition method of high code check quasi-cyclic LDPC code produces take spreading factor as unit, then the check block that generates is interweaved, at last with information bit and the check bit that produces of the check block after interweaving and extended method be multiplexed into a low code check quasi-cyclic LDPC code code word; At last by the low code check quasi-cyclic LDPC code after multiplexing being deleted remaining operation, the different code check quasi-cyclic LDPC codes that the acquisition system needs, thereby the quasi-cyclic LDPC code of acquisition code-rate-compatible.
Consult Fig. 3, the embodiment of the invention generates code-rate-compatible quasi-cyclic LDPC code method flow diagram, and the method flow process is as follows:
S301 obtains the low code check requirement of system and the degree of high code check quasi-cyclic LDPC code and distributes, and the degree of the low code check quasi-cyclic LDPC code of design distributes.The check part of the biradical check matrix of the high code check quasi-cyclic LDPC code that adopts in the present embodiment has the biconjugate corner structure, and degree corresponding to first check bit is 3.Instantiation as shown in Figure 4, h wherein
b(0)=1, h
b(m
b-1)=1, h
b(k)=1,0＜k＜(m
b-1), m
bCheck-node number before expression is decomposed.
S302, distribute and the degree of high code check quasi-cyclic LDPC code distributes variable node that need in the high code check quasi-cyclic LDPC code in the basic check matrix process of the low code check quasi-cyclic LDPC code of structure to determine the check-node that decomposes and needs to expand according to the degree of described low code check quasi-cyclic LDPC code.
S303, based on the restriction to biradical check matrix check part structure of building method and low code check quasi-cyclic LDPC code, the basic check matrix of the low code check quasi-cyclic LDPC code of structure, and expand to the check matrix of low code check quasi-cyclic LDPC code by spreading factor.Building method described in the present embodiment adopts the method for progressive edge-growth.
In the process of the basic check matrix of constructing low code check quasi-cyclic LDPC code, consider that at first low code check quasi-cyclic LDPC code is to the restriction of the check part structure of biradical check matrix, then decompose with extended operation to construct the basic check matrix that hangs down the code check quasi-cyclic LDPC code based on the variable node of the check-node that needs in progressive edge-growth method and the described high code check quasi-cyclic LDPC code to decompose and the needs expansion basic check matrix to high code check quasi-cyclic LDPC code, in the operating process
Variable node corresponding to check bit for low code check quasi-cyclic LDPC code, according to the restriction of low code check quasi-cyclic LDPC code to biradical check matrix check part structure, adopt the position of progressive edge-growth method selection cyclic shift matrices and corresponding cyclic shift value to construct to optimize the ring distribution;
There are following four kinds of situations in variable node corresponding to each information bit for low code check quasi-cyclic LDPC code:
If variable node needing in the basic check matrix of high code check quasi-cyclic LDPC code only to have participated in the verification of the check-node that decomposes, then select preferably is olation to distribute to optimize ring with the progressive edge-growth method, and the check-node of the low code check quasi-cyclic LDPC code after guaranteeing as far as possible to decompose have the least possible different number of degrees;
If variable node only needs expansion, then select position and the corresponding cyclic shift value of the cyclic shift matrices of expansion to distribute to optimize ring based on the progressive edge-growth method, and guarantee that the check-node of the low code check quasi-cyclic LDPC code after the expansion has the least possible different number of degrees;
If variable node not only needs expansion, and needing in the basic check matrix of high code check quasi-cyclic LDPC code to have participated in the verification of the check-node that decomposes, the ring that then needs to adopt simultaneously top two kinds of methods to optimize under the different spreading factors distributes, and the check-node of the low code check quasi-cyclic LDPC code after guaranteeing as far as possible expansion and decomposing has the least possible different number of degrees;
If variable node neither needs expansion, needing in the basic check matrix of high code check quasi-cyclic LDPC code not participate in the verification of the check-node that decomposes yet, continue to judge other variable node;
Each variable node is all made above-mentioned judgement and corresponding operating, until judged the variable node that all information bits are corresponding.
In the present embodiment, the check part structure of the biradical check matrix of low code check quasi-cyclic LDPC code as shown in Figure 5.Wherein, the number of degrees that first check bit is corresponding are 4, h
b(0)=1, h
b(m
b'-1)=1, h
b(k)=1,0＜k＜(m
b'-1), m
b'＞m
b, m
bThe high code check quasi-cyclic LDPC code of ' expression is through corresponding check-node number after decomposing, number of degrees span corresponding to check bit that the check bit that remaining high code check quasi-cyclic LDPC code is corresponding and decomposition method produce is 2≤i≤3, i represents number of degrees value corresponding to check bit, and number of degrees value can be determined by Density evolution is theoretical; The number of degrees corresponding to check bit that produce by extended method are 1.
S304 carries out interlace operation for the check bit of the low code check quasi-cyclic LDPC code that obtains based on said method.
Check bit based on the low code check quasi-cyclic LDPC code of said method structure is comprised of three parts: i.e. check bit corresponding to high code check quasi-cyclic LDPC code, the check bit that the check bit that produces based on decomposition method and extension-based method produce.
Unite decompose and expansion after the low code check quasi-cyclic LDPC code codeword structure that obtains as shown in Figure 6, comprise the check bit that check bit that message part, high code check quasi-cyclic LDPC code are corresponding and decomposition method produce, the check bit that extended method produces.
At first check bit corresponding to high code check quasi-cyclic LDPC code and the check bit that produces based on decomposition method are carried out piecemeal take spreading factor as unit; Then the check block that generates is interweaved, the check block that guarantees simultaneously high code check quasi-cyclic LDPC code is positioned at before the check block of decomposition method generation, the principle that interweaves is based on deletes in the remaining equivalent basic check matrix that obtains later, and the number of check-node that guarantees to have different number of degrees values is the least possible; At last with information bit and the check bit that produces of the check block after interweaving and extended method be multiplexed into a low code check quasi-cyclic LDPC code code word.
Interweave rear acquisition low code check quasi-cyclic code codeword structure as shown in Figure 7, the check bit that produces comprising the check bit of message part, the rear acquisition that interweaves, extended method.
S305 deletes remaining operation to the low code check quasi-cyclic LDPC code of the rear acquisition that interweaves, the different code check quasi-cyclic LDPC codes that the acquisition system needs, the quasi-cyclic LDPC code of acquisition code-rate-compatible.
In concrete enforcement, can low code check quasi-cyclic code not carried out interlace operation, the quasi-cyclic LDPC code that obtains based on S301 to S303 step is deleted remaining operation and different code check quasi-cyclic LDPC codes that the acquisition system needs, thereby obtain the quasi-cyclic LDPC code of code-rate-compatible.
Owing to adopt different basic check matrixes under the different code lengths, can increase like this memory requirement of system, in order to reduce the memory space of system, the general employing of quasi-cyclic LDPC code represents corresponding to the basic check matrix under the maximum code length, then by spreading factor corresponding under the different code length cyclic shift amount is revised, obtain the basic check matrix of correction, then expand the quasi-cyclic LDPC code check matrix that obtains under the required code length by corresponding spreading factor.
In order to obtain the basic check matrix under the different code length, behind the basic check matrix of the low code check quasi-cyclic LDPC code of above-mentioned steps S303 acquisition, use spreading factor that the cyclic shift amount is revised, obtain the basic check matrix of correction, obtain again the check matrix of the low code check quasi-cyclic LDPC code under the required code length by corresponding spreading factor expansion.
Accordingly, be applied in the situation of different code length in consideration, variable node corresponding to check bit for low code check quasi-cyclic LDPC code, according to the restriction of low code check quasi-cyclic LDPC code to biradical check matrix check part structure, adopt the progressive edge-growth method to select the position of cyclic shift matrices and corresponding cyclic shift value to distribute to construct with the ring of optimizing under the different code length;
For being operating as of variable node corresponding to each information bit of low code check quasi-cyclic LDPC code:
If variable node needing in the basic check matrix of high code check quasi-cyclic LDPC code only to have participated in the verification of the check-node that decomposes, then select is olation preferably to distribute with the ring of optimizing under the different code length with the progressive edge-growth method, and the check-node of the low code check quasi-cyclic LDPC code after guaranteeing as far as possible to decompose have the least possible different number of degrees;
If variable node only needs expansion, then select position and the corresponding cyclic shift value of the cyclic shift matrices of expansion to distribute with the ring of optimizing under the different code length based on the progressive edge-growth method, and guarantee that the check-node of the low code check quasi-cyclic LDPC code after the expansion has the least possible different number of degrees;
If variable node not only needs expansion, and needing in the basic check matrix of high code check quasi-cyclic LDPC code to have participated in the verification of the check-node that decomposes, the ring that then needs to adopt simultaneously top two kinds of methods to optimize under the different code length distributes, and the check-node of the low code check quasi-cyclic LDPC code after guaranteeing as far as possible expansion and decomposing has the least possible different number of degrees;
If variable node neither needs expansion, needing in the basic check matrix of high code check quasi-cyclic LDPC code not participate in the verification of the check row that decomposes yet, continue to judge other variable node;
Each variable node is all made above-mentioned judgement and corresponding operating, until judged the variable node that all information bits are corresponding.
According to the code-rate-compatible quasi-cyclic LDPC code of the inventive method structure, the HARQ scheme based on above-mentioned code-rate-compatible quasi-cyclic LDPC code is proposed further on this basis.
The formula of the original position of the calculating that proposes in embodiment of the invention check bit to be sent in the check bit of low code check quasi-cyclic LDPC code code word is as follows,
F
k＝(SPID
k*L
k)mod(ParityLen) (1)
SPID wherein
kExpression attached bag indicated value (SPID
kValue be 0,1,2 or 3), L
kThe check bit number that expression sends, ParityLen represent the total number of check bit in the low code check quasi-cyclic LDPC code code word, and k represents number of retransmissions.
The formula that calculates each check bit to be sent particular location in the check bit in low code check quasi-cyclic LDPC code code word is as follows,
S
k，i＝(F
k+i)mod(ParityLen)，i＝0，1，L L
k-1 (2)
S wherein
K, iRepresent the particular location of each check bit to be sent in the check bit of low code check quasi-cyclic LDPC code code word.Equally, at receiving terminal, calculate the particular location of each received check bit in the check bit of low code check quasi-cyclic LDPC code code word with said method.
Can find out, can under the position prerequisite of disobeying the check bit that sends before relying, calculate the particular location of each check bit in the check bit of low code check quasi-cyclic LDPC code code word of current transmission according to above-mentioned formula receiving terminal.
Concrete design is consulted Fig. 8, the HARQ flow chart of embodiment of the invention design,
S801 determines check bit to be sent original position in the check bit of low code check quasi-cyclic LDPC code code word and the particular location of each check bit in the check bit of low code check quasi-cyclic LDPC code code word to be sent.
When sending first, SPID
K=0=0 (k=0 represents to send first), check bit number according to the need transmission, determine check bit to be sent original position in the check bit of low code check quasi-cyclic LDPC code code word by formula (1), then further determine the particular location of each check bit to be sent in the check bit of low code check quasi-cyclic LDPC code code word by formula (2).Information bit and the check bit of determining according to above-mentioned formula are formed packet, then send described packet, HARQ transmits beginning, records one time transmission times, and namely this sends k=1 behind the described packet.
S802, receiving terminal is deciphered, and judges whether decoding is correct, if the receiving terminal correct decoding, to transmitting terminal feeding back ACK (affirmation) signal, then transmitting terminal is carried out S803, receives described ack signal; Otherwise to transmitting terminal feedback NACK (unconfirmed) signal, then transmitting terminal is carried out S804, receives described NACK signal.
Transmitting terminal is carried out S806 after receiving ack signal, and transmitting terminal sends other new code word bits, this HARQ end of transmission; Carry out S605 after receiving the NACK signal, judge whether to reach maximum retransmission.
If reach maximum retransmission, then carry out the S806 transmitting terminal and send other new code word bits, this HARQ end of transmission.
If do not reach maximum retransmission, then carry out S607, according to SPID
kAnd L
kValue, determine that by formula (1) check bit to be sent is in the original position of low code check quasi-cyclic LDPC code code word, then further determine the particular location of each check bit to be sent in the check bit of low code check quasi-cyclic LDPC code code word by formula (2), send the packet that corresponding bit forms, retransmit, every re-transmission once adds 1 to the k value afterwards.
When the corresponding packet of transmission retransmits, three kinds of schemes are arranged.Scheme one is when retransmitting, and retransmission data packet may is identical with the content of the packet of transmission first, and wherein check bit to be sent can pass through formula (1) (SPID wherein
k=0, L
k=L
0) determine, send this packet, each re-transmission all send information bit with send first identical check bit.Scheme two when retransmitting according to SPID
kAnd L
kValue, calculate check bit to be sent at the original position of low code check quasi-cyclic LDPC code code word and the particular location of each check bit in the check bit of low code check quasi-cyclic LDPC code code word to be sent by formula (1) and formula (2), then form packet by check bit to be sent, send this packet, only send selected check bit at every turn when retransmitting.Scheme three when retransmitting according to SPID
kAnd L
kValue, calculate check bit to be sent at the original position of low code check quasi-cyclic LDPC code code word and the particular location of each check bit in the check bit of low code check quasi-cyclic LDPC code code word to be sent by formula (1) and formula (2), then information bit and check bit to be sent form packet, send this packet, not only send selected check bit during each the re-transmission, and send information bit.
At receiving terminal, the method for its reception is:
The packet that receiving end/sending end sends, described data comprise the information of information bit and check bit, verification bit number L in the described data that receive that provide according to system control information
kValue and SPID
kValue, calculate in the received packet corresponding to the particular location of each data in the check bit of whole low code check quasi-cyclic LDPC code code word of each check bit.When receiving first the current packet that receives is deciphered, non-ly the current packet that receives and the packet that receives are before merged when receiving first, be combined into a code word and decipher.Correctness according to decoding feeds back response message to transmitting terminal.If correct decoding is to transmitting terminal feeding back ACK signal; If do not have correct decoding then to transmitting terminal feedback NACK signal.
In order to implement top method, the embodiment of the invention also provides relevant apparatus in order to realize said method.
As shown in Figure 9, the embodiment of the invention provides a kind of LDPC code coder 900, and described encoder 900 comprises:
Test matrix generation unit 902, for the check matrix of design code-rate-compatible LDPC codes, the check part structure of the binary radix check matrix of accurate circulation low code rate LDPC code as shown in Figure 5.Wherein, the number of degrees that first check bit is corresponding are 4, h
b(0)=1, h
b(m
b'-1)=1, h
b(k)=1,0＜k＜(m
b'-1), m
b'＞m
b, m
bThe high code check quasi-cyclic LDPC code of ' expression is through corresponding check-node number after decomposing, number of degrees span corresponding to check bit that the check bit that remaining high code check quasi-cyclic LDPC code is corresponding and decomposition method produce is 2≤i≤3, i represents number of degrees value corresponding to check bit, and the number of degrees corresponding to check bit that produce by extended method are 1.
As shown in figure 10, the embodiment of the invention also provides a kind of generating apparatus 1000 of quasi-cyclic LDPC code, and described generating apparatus comprises:
Degree distribution determining unit 1002, degree distribution situation based on high code check quasi-cyclic LDPC code, the degree of the low code check quasi-cyclic LDPC code of design distributes, and the check part of the biradical check matrix of described high code check quasi-cyclic LDPC code has the biconjugate corner structure, and the degree of first check digit is 3; Instantiation as shown in Figure 4, h wherein
b(0)=1, h
b(m
b-1)=1, h
b(k)=1,0＜k＜(m
b-1), m
bCheck-node number before expression is decomposed.
Computing unit 1004, be used for that degree according to described low code check quasi-cyclic LDPC code distributes and the degree of high code check quasi-cyclic LDPC code distributes, variable node that need in the high code check quasi-cyclic LDPC code in the basic check matrix process of the low code check quasi-cyclic LDPC code of structure to determine the check-node that decomposes and needs to expand;
Check matrix generation unit 1006, based on the restriction to biradical check matrix check part structure of building method and low code check quasi-cyclic LDPC code, the basic check matrix of the low code check quasi-cyclic LDPC code of structure, the check part structure of the biradical check matrix of low code check quasi-cyclic LDPC code as shown in Figure 5, wherein, the number of degrees that first check bit is corresponding are 4, h
b(0)=1, h
b(m
b'-1)=1, h
b(k)=1,0＜k＜(m
b'-1), m
b'＞m
b, m
bThe high code check quasi-cyclic LDPC code of ' expression is through corresponding check-node number after decomposing, number of degrees span corresponding to check bit that the check bit that remaining high code check quasi-cyclic LDPC code is corresponding and decomposition method produce is 2≤i≤3, i represents number of degrees value corresponding to check bit, and the number of degrees corresponding to check bit that produce by extended method are 1;
This check matrix generation unit 1006 also comprises an expansion module, and it is used for the basic check matrix of described quasi-cyclic LDPC code is expanded to by spreading factor the check matrix of low code check quasi-cyclic LDPC code.
Delete remaining operating unit 1012, the different code check quasi-cyclic LDPC codes that the acquisition system needs for low code check quasi-cyclic LDPC code is deleted remaining operation, the quasi-cyclic LDPC code of acquisition code-rate-compatible.
In order to realize the support to many code lengths demand, this generating apparatus also comprises a code length amending unit 1014, this code length amending unit is used for using spreading factor corresponding under the different code length that the cyclic shift amount is revised to the basic check matrix of the described low code check quasi-cyclic LDPC code that constructs, and obtains the basic check matrix of revising.
As shown in figure 11, the embodiment of the invention also provides a kind of transmitting terminal device 1100.
This transmitting terminal device 1100 comprises:
F
k＝(SPID
k*L
k)mod(ParityLen)
Determine check bit to be sent original position in the check bit of low code check quasi-cyclic LDPC code code word, wherein SPID
kExpression attached bag indicated value (SPID
kValue be 0,1,2 or 3), L
kThe check bit number that expression sends, ParityLen represent the total number of check bit in the low code check quasi-cyclic LDPC code code word, and k represents number of retransmissions, passes through formula
S
k，i＝(F
k+i)mod(ParityLen)，i＝0，1，L L
k-1
Determine the particular location of each check bit to be sent in the check bit of low code check quasi-cyclic LDPC code code word;
Transmitting element 1104 is used for sending the packet that the information bit connection forms with the check bit of determining according to above-mentioned formula.
This device also comprises receiving element 1108, is used for receiving the feedback information that sends from receiving terminal; And
Judging unit 1106 is for the type of judging the feedback information that receiving element 1108 receives.
The embodiment of the invention also provides a kind of receiving end device 1200 as shown in figure 12, cooperates above-mentioned transmitting terminal device 1100 work.Described receiving end device comprises:
F
k＝(SPID
k*L
k)mod(ParityLen)
Determine the original position of check bit in the check bit of whole low code check quasi-cyclic LDPC code code word in the receive data bag, wherein SPID
kExpression attached bag indicated value (SPID
kValue be 0,1,2 or 3), L
kThe check bit number that expression sends, ParityLen represent the total number of check bit in the quasi-cyclic LDPC code code word of low code check, and k represents number of retransmissions, passes through formula
S
k，i＝(F
k+i)mod(ParityLen)，i＝0，1，L L
k-1
Determine in the receive data bag particular location of each data in the check bit of low code check quasi-cyclic LDPC code code word corresponding to check bit;
Feedback signal transmitting element 1210 be used for to send and to feed back signal to transmitting terminal, sends ack signal if decoding is correct, if decipher incorrect then send the NACK signal.
Utilize associating decomposition method and extended method to construct the code-rate-compatible quasi-cyclic LDPC code, when using the method to obtain low code check quasi-cyclic LDPC code, the number of degrees corresponding to the check-node of high code check quasi-cyclic LDPC code can reduce along with the reduction of code check by decomposition method, can increase along with the reduction of code check by extended method corresponding to the number of degrees of the variable node of high code check quasi-cyclic LDPC code; Simultaneously delete remaining mode based on the check bit deinterleaving method with optimization, then more than deleting, obtain the quasi-cyclic LDPC code of different code checks, and then generated the quasi-cyclic LDPC code of code-rate-compatible.Proposed corresponding support HARQ scheme on the code-rate-compatible quasi-cyclic LDPC code basis that designs based on above method, the transmitting-receiving two-end control overhead is less, has improved the performance of whole system.
Claims (14)
1. a method that generates quasi-cyclic low-density parity check code is characterized in that, described method comprises:
The low code check of acquisition system requires and the degree of high code check quasi-cyclic low-density parity check code distributes, and the degree of the low code check quasi-cyclic low-density parity check code of design distributes;
Distribute and the degree of high code check quasi-cyclic low-density parity check code distributes variable node that need in the high code check quasi-cyclic low-density parity check code in the process of the low code check quasi-cyclic low-density parity check code base check matrix of structure to determine the check-node that decomposes and needs to expand according to the degree of described low code check quasi-cyclic low-density parity check code;
Based on the restriction to biradical check matrix check part structure of building method and low code check quasi-cyclic low-density parity check code, the basic check matrix of the low code check quasi-cyclic low-density parity check code of structure;
Based on the restriction to biradical check matrix check part structure of building method and low code check quasi-cyclic low-density parity check code, the basic check matrix of the low code check quasi-cyclic low-density parity check code of structure is:
According to the restriction of low code check quasi-cyclic low-density parity check code to the check part structure of biradical check matrix, decompose and extended operation based on the variable node of the check-node that needs in building method and the high code check quasi-cyclic low-density parity check code to decompose and the needs expansion basic check matrix to high code check quasi-cyclic low-density parity check code, structure hangs down the basic check matrix of code check quasi-cyclic low-density parity check code;
The basic check matrix of described low code check quasi-cyclic low-density parity check code is expanded to the check matrix of low code check quasi-cyclic low-density parity check code by spreading factor; Perhaps, basic check matrix to described low code check quasi-cyclic low-density parity check code uses spreading factor that the cyclic shift amount is revised, obtain the basic check matrix of correction, obtain the check matrix of the low code check quasi-cyclic low-density parity check code under the required code length by the spreading factor expansion;
Check matrix based on described low code check quasi-cyclic low-density parity check code is encoded, and obtains low code check quasi-cyclic low-density parity check code.
2. the method for claim 1 is characterized in that, the check part structure of the biradical check matrix of the basic check matrix of described low code check quasi-cyclic low-density parity check code is:
Wherein, the number of degrees that first check bit is corresponding are 4, h
b(0)=1, h
b(m
b'-1)=1, h
b(k)=1,0＜k＜m
b'-1, m
b'＞m
b, m
bThe high code check quasi-cyclic low-density parity check code of ' expression is through corresponding check-node number after decomposing, m
bRepresent the check-node number before high code check quasi-cyclic low-density parity check code decomposes, number of degrees span corresponding to check bit that the check bit of remaining high code check quasi-cyclic low-density parity check code correspondence and decomposition method produce is 2≤i≤3, i represents number of degrees value corresponding to check bit, and the number of degrees corresponding to check bit that produce by extended method are 1.
3. the method for claim 1 is characterized in that, the check part of the biradical check matrix of described high code check quasi-cyclic low-density parity check code has the biconjugate corner structure, and degree corresponding to first check bit be 3, and structure is:
H wherein
b(0)=1, h
b(m
b-1)=1, h
b(k)=1,0＜k＜m
b-1, m
bRepresent the check-node number before high code check quasi-cyclic low-density parity check code decomposes.
4. method that generates code-rate-compatible quasi-cyclic low-density parity check code is characterized in that described method comprises:
The low code check of acquisition system requires and the degree of high code check quasi-cyclic low-density parity check code distributes, and the degree of the low code check quasi-cyclic low-density parity check code of design distributes;
Distribute and the degree of high code check quasi-cyclic low-density parity check code distributes variable node that need in the high code check quasi-cyclic low-density parity check code in the basic check matrix process of the low code check quasi-cyclic low-density parity check code of structure to determine the check-node that decomposes and needs to expand according to the degree of described low code check quasi-cyclic low-density parity check code;
Based on the restriction to biradical check matrix check part structure of building method and low code check quasi-cyclic low-density parity check code, the basic check matrix of the low code check quasi-cyclic low-density parity check code of structure;
Based on the restriction to biradical check matrix check part structure of building method and low code check quasi-cyclic low-density parity check code, the basic check matrix of the low code check quasi-cyclic low-density parity check code of structure is:
According to the restriction of low code check quasi-cyclic low-density parity check code to the check part structure of biradical check matrix, decompose and extended operation based on the variable node of the check-node that needs in building method and the high code check quasi-cyclic low-density parity check code to decompose and the needs expansion basic check matrix to high code check quasi-cyclic low-density parity check code, structure hangs down the basic check matrix of code check quasi-cyclic low-density parity check code;
The basic check matrix of described low code check quasi-cyclic low-density parity check code is expanded to the check matrix of low code check quasi-cyclic low-density parity check code by spreading factor; Perhaps, the basic check matrix use spreading factor of the described low code check quasi-cyclic low-density parity check code that constructs is revised the cyclic shift amount, obtained the basic check matrix of revising; Obtain the check matrix of the low code check quasi-cyclic low-density parity check code under the required code length by the spreading factor expansion;
Obtain low code check quasi-cyclic low-density parity check code and delete remaining operation, obtain the quasi-cyclic low-density parity check code of code-rate-compatible, described low code check quasi-cyclic low-density parity check code is to encode according to the check matrix of described low code check quasi-cyclic low-density parity check code to obtain.
5. method as claimed in claim 4 is characterized in that, the check part structure of the biradical check matrix of the basic check matrix of described low code check quasi-cyclic low-density parity check code is:
Wherein, the number of degrees that first check bit is corresponding are 4, h
b(0)=1, h
b(m
b'-1)=1, h
b(k)=1,0＜k＜m
b'-1, m
b'＞m
b, m
bThe high code check quasi-cyclic low-density parity check code of ' expression is through corresponding check-node number after decomposing, m
bRepresent the check-node number before high code check quasi-cyclic low-density parity check code decomposes, number of degrees span corresponding to check bit that the check bit of remaining high code check quasi-cyclic low-density parity check code correspondence and decomposition method produce is 2≤i≤3, i represents number of degrees value corresponding to check bit, and the number of degrees corresponding to check bit that produce by extended method are 1.
6. method as claimed in claim 4 is characterized in that, the check part of the biradical check matrix of described high code check quasi-cyclic low-density parity check code has the biconjugate corner structure, and degree corresponding to first check bit be 3, and structure is:
H wherein
b(0)=1, h
b(m
b-1)=1, h
b(k)=1,0＜k＜m
b-1, m
bRepresent the check-node number before high code check quasi-cyclic low-density parity check code decomposes.
7. method as claimed in claim 4 is characterized in that, delete remaining operation and also comprise before,
Check bit to low code check quasi-cyclic low-density parity check code carries out interlace operation.
8. method as claimed in claim 7 is characterized in that, to the check bit of low code check quasi-cyclic low-density parity check code interweave for:
The check bit of high code check quasi-cyclic low-density parity check code correspondence and the check bit that produces based on decomposition method are carried out piecemeal take spreading factor as unit;
The check block that generates is interweaved;
With information bit and the check bit that produces of the check block after interweaving and extended method be multiplexed into a low code check quasi-cyclic low-density parity check code code word.
9. method as claimed in claim 4, it is characterized in that, the check part of described low code check quasi-cyclic low-density parity check code is comprised of three parts: the check bit of high code check quasi-cyclic low-density parity check code correspondence, and based on the check bit of decomposition method generation and the check bit of extension-based method generation.
10. the generating apparatus of a quasi-cyclic low-density parity check code is characterized in that, described generating apparatus comprises:
Degree distribution determining unit, based on the low code check requirement of system and the degree distribution situation of high code check quasi-cyclic low-density parity check code, the degree of the low code check quasi-cyclic low-density parity check code of design distributes, and the check part of the biradical check matrix of described high code check quasi-cyclic low-density parity check code has the biconjugate corner structure;
Computing unit, be used for that degree according to described low code check quasi-cyclic low-density parity check code distributes and the degree of high code check quasi-cyclic low-density parity check code distributes, variable node that need in the high code check quasi-cyclic low-density parity check code in the basic check matrix process of the low code check quasi-cyclic low-density parity check code of structure to determine the check-node that decomposes and needs to expand;
The check matrix generation unit, based on the restriction to biradical check matrix check part structure of building method and low code check quasi-cyclic low-density parity check code, the basic check matrix of the low code check quasi-cyclic low-density parity check code of structure;
Described check matrix generation unit specifically is used for: according to the restriction of low code check quasi-cyclic low-density parity check code to the check part structure of biradical check matrix, decompose and extended operation based on the variable node of the check-node that needs in building method and the high code check quasi-cyclic low-density parity check code to decompose and the needs expansion basic check matrix to high code check quasi-cyclic low-density parity check code, structure hangs down the basic check matrix of code check quasi-cyclic low-density parity check code;
Described generating apparatus also comprises: coding unit, be used for encoding based on described low code check quasi-cyclic low-density parity check code check matrix, obtain low code check quasi-cyclic low-density parity check code, described low code check quasi-cyclic low-density parity check code check matrix is: the check matrix of the basic check matrix of described low code check quasi-cyclic low-density parity check code being expanded the low code check quasi-cyclic low-density parity check code that obtains by spreading factor; Perhaps, basic check matrix to described low code check quasi-cyclic low-density parity check code uses spreading factor that the cyclic shift amount is revised, obtain the basic check matrix of correction, expand the check matrix of the low code check quasi-cyclic low-density parity check code under the required code length that obtains by spreading factor.
11. generating apparatus as claimed in claim 10 is characterized in that, the check part structure of the biradical check matrix of the basic check matrix of the low code check quasi-cyclic low-density parity check code of described check matrix generation unit structure is:
Wherein, the number of degrees that first check bit is corresponding are 4, h
b(0)=1, h
b(m
b'-1)=1, h
b(k)=1,0＜k＜m
b'-1, m
b'＞m
b, m
bThe high code check quasi-cyclic low-density parity check code of ' expression is through corresponding check-node number after decomposing, m
bRepresent the check-node number before high code check quasi-cyclic low-density parity check code decomposes, number of degrees span corresponding to check bit that the check bit of remaining high code check quasi-cyclic low-density parity check code correspondence and decomposition method produce is 2≤i≤3, i represents number of degrees value corresponding to check bit, and the number of degrees corresponding to check bit that produce by extended method are 1.
12. the generating apparatus of a code-rate-compatible quasi-cyclic low-density parity check code is characterized in that described generating apparatus comprises:
Degree distribution determining unit, based on the low code check requirement of system and the degree distribution situation of high code check quasi-cyclic low-density parity check code, the degree of the low code check quasi-cyclic low-density parity check code of design distributes, and the check part of the biradical check matrix of described high code check quasi-cyclic low-density parity check code has the biconjugate corner structure;
Computing unit, be used for that degree according to described low code check quasi-cyclic low-density parity check code distributes and the degree of high code check quasi-cyclic low-density parity check code distributes, determine the low code check quasi-cyclic low-density parity check code of structure basic check matrix process in need in the high code check quasi-cyclic low-density parity check code check-node that decomposes and needs to expand variable node;
The check matrix generation unit, based on the restriction to biradical check matrix check part structure of building method and low code check quasi-cyclic low-density parity check code, the basic check matrix of the low code check quasi-cyclic low-density parity check code of structure;
Described check matrix generation unit specifically is used for: according to the restriction of low code check quasi-cyclic low-density parity check code to the check part structure of biradical check matrix, decompose and extended operation based on the variable node of the check-node that needs in building method and the high code check quasi-cyclic low-density parity check code to decompose and the needs expansion basic check matrix to high code check quasi-cyclic low-density parity check code, structure hangs down the basic check matrix of code check quasi-cyclic low-density parity check code;
Described check matrix generation unit also comprises, expansion module, and it is used for the basic check matrix of described low code check quasi-cyclic low-density parity check code is expanded to by spreading factor the check matrix of low code check quasi-cyclic low-density parity check code;
Coding unit is used for encoding based on described low code check quasi-cyclic low-density parity check code check matrix, obtains low code check quasi-cyclic low-density parity check code;
Delete remaining operating unit, the different code check quasi-cyclic low-density parity check codes that the acquisition system needs for low code check quasi-cyclic low-density parity check code is deleted remaining operation, thereby the quasi-cyclic low-density parity check code of acquisition code-rate-compatible.
13. generating apparatus as claimed in claim 12 is characterized in that, described generating apparatus also comprises:
Interleave unit is used for interweaving for the check bit of the low code check quasi-cyclic low-density parity check code that obtains based on said method.
14. generating apparatus as claimed in claim 12 is characterized in that, described generating apparatus also comprises:
Code length amending unit, this code length amending unit are used for using spreading factor that the cyclic shift amount is revised to the basic check matrix of the described low code check quasi-cyclic low-density parity check code that constructs.
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| CN102075196B (en) * | 2010-12-10 | 2014-02-19 | 清华大学 | Multi-code rate multi-code length QC-LDPC coding method and coding modulation system |
| CN105811996B (en) | 2014-12-30 | 2019-12-06 | 华为技术有限公司 | data processing method and system based on quasi-cyclic LDPC |
| US10784901B2 (en) * | 2015-11-12 | 2020-09-22 | Qualcomm Incorporated | Puncturing for structured low density parity check (LDPC) codes |
| US11043966B2 (en) | 2016-05-11 | 2021-06-22 | Qualcomm Incorporated | Methods and apparatus for efficiently generating multiple lifted low-density parity-check (LDPC) codes |
| US10454499B2 (en) | 2016-05-12 | 2019-10-22 | Qualcomm Incorporated | Enhanced puncturing and low-density parity-check (LDPC) code structure |
| US9917675B2 (en) | 2016-06-01 | 2018-03-13 | Qualcomm Incorporated | Enhanced polar code constructions by strategic placement of CRC bits |
| WO2017214851A1 (en) * | 2016-06-14 | 2017-12-21 | 华为技术有限公司 | Signal transfer method, transmitting terminal, and receiving terminal |
| US10291354B2 (en) | 2016-06-14 | 2019-05-14 | Qualcomm Incorporated | High performance, flexible, and compact low-density parity-check (LDPC) code |
| CN106506010B (en) * | 2016-10-17 | 2019-05-17 | 中国科学院国家空间科学中心 | A kind of LDPC encoder compatible based on DVB-S2 standard multi code Rate of Chinese character |
| CN118473421A (en) | 2017-05-05 | 2024-08-09 | 华为技术有限公司 | Information processing method and communication device |
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| CN108988869B (en) * | 2017-05-31 | 2021-07-30 | 大唐移动通信设备有限公司 | Method and device for determining check matrix and computer storage medium |
| US10312939B2 (en) | 2017-06-10 | 2019-06-04 | Qualcomm Incorporated | Communication techniques involving pairwise orthogonality of adjacent rows in LPDC code |
| CN109617554B (en) * | 2018-11-22 | 2023-02-03 | 周口师范学院 | Q-element quasi-cyclic LDPC code construction method based on arbitrary array |
| DE102019200256B4 (en) * | 2019-01-10 | 2020-07-30 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Nesters |
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