CN101567348A - Wafer structure with convex lumps and forming method thereof - Google Patents
Wafer structure with convex lumps and forming method thereof Download PDFInfo
- Publication number
- CN101567348A CN101567348A CN 200810093192 CN200810093192A CN101567348A CN 101567348 A CN101567348 A CN 101567348A CN 200810093192 CN200810093192 CN 200810093192 CN 200810093192 A CN200810093192 A CN 200810093192A CN 101567348 A CN101567348 A CN 101567348A
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- layer
- weld
- weld pad
- ubm layer
- ubm
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- 238000000034 method Methods 0.000 title claims description 12
- 239000013078 crystal Substances 0.000 claims abstract description 26
- 238000000059 patterning Methods 0.000 claims description 19
- 239000002861 polymer material Substances 0.000 claims description 19
- 238000007772 electroless plating Methods 0.000 claims description 8
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 8
- 239000010931 gold Substances 0.000 claims description 8
- 229910052737 gold Inorganic materials 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 8
- 230000015572 biosynthetic process Effects 0.000 claims description 6
- 239000004065 semiconductor Substances 0.000 claims description 5
- 230000000717 retained effect Effects 0.000 claims description 4
- 238000003466 welding Methods 0.000 claims 1
- 239000010410 layer Substances 0.000 description 62
- 238000005516 engineering process Methods 0.000 description 15
- 235000012431 wafers Nutrition 0.000 description 13
- 238000010586 diagram Methods 0.000 description 11
- 239000002131 composite material Substances 0.000 description 8
- 239000000758 substrate Substances 0.000 description 8
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 238000000206 photolithography Methods 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 239000002699 waste material Substances 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- 239000000084 colloidal system Substances 0.000 description 1
- 230000008602 contraction Effects 0.000 description 1
- 239000012792 core layer Substances 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention relates to a wafer structure with convex lumps, which comprises a wafer, a plurality of macromolecular convex lumps, a UBM layer and a conducting layer, wherein a plurality of crystal grains are arranged on the wafer, and a plurality of weld pads are arranged on each crystal grain; the macromolecular convex lump is arranged on the weld pad of each crystal grain and exposes part of the weld pad; the UBM layer is formed on each macromolecular convex lump and covered the weld pad which is partially exposed; and the conducting layer is coated on the surface of the UBM layer and electrically connected with the weld pads by the UBM layer.
Description
Technical field
The encapsulating structure of the relevant a kind of semiconductor subassembly of the present invention, more particularly relevant a kind of electroless plating of using forms gold in having encapsulating structure of macromolecular convex and forming method thereof.
Background technology
In the current chip encapsulation technology, with crystal grain mantle encapsulation (Chip on Film, COF) and crystal grain and glass substrate bond package (Chip on Glass, COG) be major technique, and the packaged type of COF utilizes anisotropic conductive (anisotropic conductive film, ACF) vertical conducting engages and utilizes non-conductive adhesive (Non-Conductive Paste, the contraction joint that produces after NCP/NCF) hot tooth solidifies etc.Often just be connected between chip and the substrate, yet, can obtain excellent electrical property and connect, and the contact stress that produced of the easier adaptation engaging process of soft characteristic of gold, make to engage quality and guaranteed because gold is difficult for oxidation with golden projection.
In order to form the projection technology that connects on the production cost that reduces golden projection and the simplifying integrated circuit, be that composite projection (compliant bump) structure of core layer is studied successively and delivers out in recent years with the macromolecular convex.Figure 1A is the schematic diagram that expression utilizes the encapsulating structure of composite projection joint chip on substrate.Shown in Figure 1A, have a macromolecular convex 104 in the composite projection 102, and in surface coverage one conductive metallic material 106 of macromolecular convex 104, it is in order to connect chip 110 on substrate 120.Wherein composite projection 102 can be by conducting particles 132 vertical conductings in the anisotropic conductive 130 in upper and lower contact 122,112, perhaps directly with non-conductive adhesive (expression in the drawings) produce shrink engage and conducting in upper and lower contact 122,112.
Please continue with reference to Figure 1B, be the chip 110 that is shown in Figure 1A when being heated with substrate 120, because of rise phenomenon and the inequality of being heated of colloid heat makes chip 110 or substrate 120 that the schematic diagram of buckling deformations take place.Clearly, when the deflection of entire chip packaging body 100 surpasses predetermined bond strength, to make the outside contact 124 of substrate 120 composite projection 102 on can't contact chip 110, and cause signal to open circuit or problem such as contact impedance increase, reduce the reliability that engages.
Summary of the invention
In view of above problem, main purpose of the present invention is to provide a kind of electroless plating gold as conductive junction point, so as to saving the technology cost.
Another object of the present invention, be by the UBM layer to electrically connect conductive layer and weld pad, make the reliability of encapsulating structure of wafer increase.
In view of the above, the present invention discloses a kind of encapsulating structure of semiconductor subassembly, comprises: a crystal grain, dispose a plurality of weld pads on it; A plurality of macromolecular convex are to be configured on the weld pad of each crystal grain and to expose weld pad partly; One UBM layer is formed on each macromolecular convex and covers this weld pad that exposes partly; And a conductive layer, be coated on the surface of UBM layer, and form electric connection by UBM layer and a plurality of weld pad.
The present invention also discloses a kind of formation method of chip architecture, comprise: a wafer is provided, have a upper surface and a back side, and dispose a plurality of crystal grain on the wafer, and in having a plurality of weld pads on each crystal grain and on each weld pad, having the weld pad screen of a patterning; Form a polymer material layer, on each crystal grain and a plurality of weld pad of covering wafer; Remove partly polymer material layer, being retained in the polymer material layer on a plurality of weld pads, and expose the part surface of a plurality of weld pads; Forming a UBM layer to cover on the wafer, is that the UBM layer is covered in a part surface that weld pad screen, a plurality of weld pad of patterning exposed to the open air and a surface of polymer material layer; Remove partly UBM layer, be retained on the polymer material layer part UBM layer and and be adjacent to part UBM layer on the weld pad screen of part patterning of a plurality of weld pads; And form a conductive layer on a surface of UBM layer, be that the mode with electroless plating forms conductive layer on the surface of UBM layer, and by UBM layer and the electric connection of a plurality of weld pad.
Description of drawings
For making purpose of the present invention, structure, feature and function thereof there are further understanding, below conjunction with figs. are elaborated to preferred embodiment of the present invention, wherein:
Figure 1A and Figure 1B are according to the composite projection structure of prior art and the schematic diagram that engages with substrate;
Fig. 2 is disclosed technology according to the present invention, represents to have on the wafer vertical view of a plurality of crystal grain;
Fig. 3 is disclosed technology according to the present invention, and the weld pad screen of expression patterning is formed on the crystal grain and exposes the partly schematic diagram of weld pad;
Fig. 4 and Fig. 5 are disclosed technology according to the present invention, are shown in the step schematic diagram that forms macromolecular convex on the weld pad of crystal grain;
Fig. 6 to Fig. 7 is disclosed technology according to the present invention, is illustrated in the step schematic diagram that forms a UBM layer on the surface of macromolecular convex; And
Fig. 8 is disclosed technology according to the present invention, forms the schematic diagram of conductive layer on the surface of UBM layer.
Embodiment
Fig. 2 to Fig. 8 is each steps flow chart schematic diagram of disclosed chip architecture and forming method thereof according to the present invention.As shown in Figure 2, be that expression provides a wafer 20, it has a upper surface and a back side, and disposes a plurality of crystal grain 210 on the wafer 20.Be noted that at this in the represented steps flow chart schematic diagram of Fig. 2 to Fig. 8 be with the explanation of any crystal grain on the wafer 20 as specific embodiment, for showing feature of the present invention, only illustrate simultaneously with a certain weld pad 212 on the crystal grain 210; Yet, be that entire wafer is encapsulated in the step of reality.
At first, please refer to Fig. 3, be that expression forms the weld pad screen (patterned pad mask layer) 214 of a patterning with semiconductor technology on wafer 20, this weld pad screen 214 cover crystal grain 210 and partly weld pad 212 all around and expose the central part of weld pad 212; And this weld pad screen 214 is a dielectric material.
Then, please refer to Fig. 4 to Fig. 8, is to be shown in the steps flow chart schematic diagram that forms composite projection on the weld pad of crystal grain.At first, as shown in Figure 4, be to form a polymer material layer 30, to cover weld pad screen 214 and each weld pad 212 of the patterning on the crystal grain 20, at this, the method that forms polymer material layer 30 can be coating (coating) or polymer material layer 30 injected the upper surface of wafers 20, utilize die device (expression in the drawings) with polymer material layer 30 planarizations again; Then after breaking away from die device, can obtain having weld pad 212 tops that the polymer material layer 30 of a uniform outer surface is formed on the weld pad screen 214 of patterning and exposes to the open air.
Then, with photolithography (photolithography) technology, formation one has photoresist (photoresist) layer (expression in the drawings) of patterning on polymer material layer 30; Then, use etch process (for example: wet etching) remove polymer material layer 30 partly; Then, after removing the photoresist layer of patterning, make a plurality of macromolecular convex 30 being formed on the centre of each weld pad 212, and each macromolecular convex 30 and the adjacent weld pad screen 214 part surface of separating and exposing each weld pad 212, as shown in Figure 5.At this, the material of macromolecular convex 30 can be polyimides (polyimide) or epoxy resin (epoxy) or elasticity macromolecular material.
Next please refer to Fig. 6 to Fig. 7, is that expression forms a UBM layer at the lip-deep step schematic diagram of macromolecular convex.As shown in Figure 6, the mode with sputter (sputtering) forms a UBM layer 40 on crystal grain 210 earlier, with weld pad 212 surface and each macromolecular convex 30 that cover weld pad screen 214, expose to the open air.Then, form the photoresist layer (not expression in the drawings) of a patterning on the UBM layer 40 on macromolecular convex 30 and the weld pad 212; Follow again, be etched with and remove the UBM layer 40 that is not covered by photoresist layer.At last, the photoresist layer that will be positioned at again on macromolecular convex 30 and the weld pad 212 removes, so that UBM layer 40 only covers on macromolecular convex 30, weld pad 212 and the part weld pad screen 214, as shown in Figure 7.UBM layer is in the present embodiment formed by the Ti/Ni material.
Then, please refer to Fig. 8, is that one deck conductive layer 50 is formed on the surface of UBM layer 40, and makes this conductive layer 50 to form electric connection by UBM layer 40 and weld pad 212.In inventive embodiment, conductive layer 50 is to use the mode of electroless plating (electroless plating) to form, and wherein conductive layer 50 employed materials are gold (gold), so 50 of conductive layers are formed on the surface of UBM layer 40.Be stressed that at this, the purpose of utilizing electroless plating to form conductive layer 50 is: conductive layer 50 only is formed on the surface of UBM layer 40, the part of other no UBM layer 40 can not form any conductive layer on chip architecture, thereby can significantly reduce the use cost of gold; This is compared to traditional semiconductor technology, after on the weld pad screen 214 of conductive layer 50 and patterning, being formed on UBM layer 40, also need to carry out again photolithography technology once, to remove the conductive layer 40 on the weld pad screen 214 of patterning, this makes the increase of technology cost also can waste the material of conductive layer and increase many unnecessary costs virtually.
Therefore, according to the above, in present embodiment, the composite projection that utilizes macromolecular convex 30, UBM layer 40 and conductive layer 50 to be constituted, the effect that can have excellent electrical property to connect equally.In addition, utilize the mode of electroless plating, can save the technology cost, avoid the waste of unnecessary material.
Though the present invention discloses as above with aforesaid preferred embodiment; yet it is not in order to limit the present invention; any person skilled in the art person; without departing from the spirit and scope of the present invention; when can making all changes that is equal to or replacement, therefore scope of patent protection of the present invention must be looked being as the criterion that the appended the application's claim scope of this specification defined.
Claims (10)
1. the encapsulating structure of a semiconductor subassembly comprises:
One crystal grain disposes a plurality of weld pads on it, and has the weld pad screen of a patterning on each this weld pad;
A plurality of macromolecular convex are configured on each this weld pad and expose the part surface of these weld pads;
One UBM layer is formed on each this macromolecular convex and covers the part surface of these weld pads that expose; And
One conductive layer is coated on this UBM layer.
2. one kind has the bump wafer structure, comprises:
One wafer disposes a plurality of crystal grain on it, and has a plurality of weld pads on each this crystal grain, and has the weld pad screen of a patterning on each this weld pad; And
A plurality of projections are formed on each this weld pad, and wherein each this projection comprises:
One macromolecular convex is formed on these weld pads and exposes the part surface of these weld pads;
One UBM layer is formed on partly on this patterning welding cover layer and coats this macromolecular convex and fill up the part surface that this weld pad exposes to the open air; And
One conductive layer covers this UBM layer.
3. chip architecture according to claim 2 is characterized in that these macromolecular convex are the elasticity macromolecular convex.
4. chip architecture according to claim 2, the material that it is characterized in that the UBM layer of these patternings is the Ti/Ni layer.
5. chip architecture according to claim 2 is characterized in that the material of these conductive layers is gold.
6. projection cube structure comprises:
One macromolecular convex;
One UBM layer is covered on this macromolecular convex; And
One conductive layer is coated on this UBM layer.
7. projection cube structure according to claim 6 is characterized in that this macromolecular convex is the elasticity macromolecular convex.
8. the formation method of a chip architecture comprises:
One wafer is provided, disposes a plurality of crystal grain on it, and on each this crystal grain, have a plurality of weld pads, and on each this weld pad, have the weld pad screen of a patterning;
Form a polymer material layer, on each this crystal grain and these weld pads of covering this wafer;
Remove partly this polymer material layer, being retained in this polymer material layer on these weld pads, and expose the part surface of these weld pads;
Forming a UBM layer to cover on this wafer, is that this UBM layer is covered a part surface that weld pad screen, these weld pads of this patterning exposed to the open air and a surface of this polymer material layer;
Remove partly this UBM layer, to be retained in this UBM layer of part on this polymer material layer and to be adjacent to this UBM layer of part on the weld pad screen of this patterning of part of these weld pads; And
Forming a conductive layer on a surface of this UBM layer, is that the mode with electroless plating forms this conductive layer on this surface of this UBM layer, and by this UBM layer and the electric connection of these weld pads.
9. formation method according to claim 8 is characterized in that this polymer material layer is an elasticity polymer material layer.
10. formation method according to claim 8 is characterized in that this UBM layer is the Ti/Ni layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200810093192 CN101567348A (en) | 2008-04-21 | 2008-04-21 | Wafer structure with convex lumps and forming method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200810093192 CN101567348A (en) | 2008-04-21 | 2008-04-21 | Wafer structure with convex lumps and forming method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101567348A true CN101567348A (en) | 2009-10-28 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200810093192 Pending CN101567348A (en) | 2008-04-21 | 2008-04-21 | Wafer structure with convex lumps and forming method thereof |
Country Status (1)
| Country | Link |
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| CN (1) | CN101567348A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102593068A (en) * | 2011-01-11 | 2012-07-18 | 颀邦科技股份有限公司 | Oblique-conic-shaped bump structure |
| CN102790016A (en) * | 2011-05-16 | 2012-11-21 | 颀邦科技股份有限公司 | Bump structure and producing process thereof |
| CN102790035A (en) * | 2011-05-17 | 2012-11-21 | 颀邦科技股份有限公司 | Bump structure and process |
| CN103383928A (en) * | 2012-05-03 | 2013-11-06 | 爱思开海力士有限公司 | Semiconductor chip and semiconductor package |
-
2008
- 2008-04-21 CN CN 200810093192 patent/CN101567348A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102593068A (en) * | 2011-01-11 | 2012-07-18 | 颀邦科技股份有限公司 | Oblique-conic-shaped bump structure |
| CN102593068B (en) * | 2011-01-11 | 2015-08-19 | 颀邦科技股份有限公司 | Oblique-conic-shaped bump structure |
| CN102790016A (en) * | 2011-05-16 | 2012-11-21 | 颀邦科技股份有限公司 | Bump structure and producing process thereof |
| CN102790016B (en) * | 2011-05-16 | 2014-10-15 | 颀邦科技股份有限公司 | Bump structure and producing process thereof |
| CN102790035A (en) * | 2011-05-17 | 2012-11-21 | 颀邦科技股份有限公司 | Bump structure and process |
| CN102790035B (en) * | 2011-05-17 | 2015-02-18 | 颀邦科技股份有限公司 | Bump structure and process |
| CN103383928A (en) * | 2012-05-03 | 2013-11-06 | 爱思开海力士有限公司 | Semiconductor chip and semiconductor package |
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Open date: 20091028 |