CN101436569A - Method of manufacturing thin film transistor array substrate and display device - Google Patents

Abstract

A method of manufacturing a thin film transistor array substrate according to the present invention includes: forming a pattern made of a first conductive film; stacking a gate insulating film, a semiconductor layer, and a resist in the stated order; forming a resist pattern having a step structure in a thickness direction; forming an exposed area of the first conductive film and a pattern of the semiconductor layer by using the resist pattern; forming a pattern made of a second conductive film in contact with the first conductive film in the exposed area of the first conductive film; and forming a pattern made of a third conductive film. The first conductive film forms a gate electrode, and the second conductive film forms each of a source electrode and a drain electrode. The third conductive film forms a pixel electrode, and the second conductive film is coated with an upper-layer film.

Description

Manufacturing method of thin film transistor array substrate and display device

technical field

0001

The present invention relates to a method for manufacturing a thin film transistor array substrate, and also relates to a display device equipped with a thin film transistor array substrate manufactured by the method for manufacturing a thin film transistor array substrate.

Background technique

0002

Thin film transistors (hereinafter also referred to as "TFT" (Thin Film Transistor)) are widely used as transistors for driving pixels in active matrix liquid crystal display devices (AMLCD: Active-Matrix Liquid-Crystal Display). Amorphous (amorphous) silicon (Si) films are also used as semiconductor films in TFTs. This is because they can be manufactured with a small number of steps and can easily increase the size of insulating substrates, so they are widely used because of their high productivity. use.

0003

At least five different etching processes are required in the manufacturing process of the TFT array substrate. In addition, in order to form the photoresist pattern (resistpattern) corresponding to each etching (etching) process, need 5 photoplate-making processes, in order to carry out these 5 photoplate-making processes, will use 5 photomasks (photomask) ( For example, Patent Document 1).

0004

In recent years, methods for further reducing the number of manufacturing steps to reduce manufacturing costs have been proposed (for example, Patent Documents 2 to 5). By adopting so-called multi-gradation exposure technology and liftoff method, etc., the number of manufacturing steps will be reduced. By adopting multi-gray exposure technology, film thickness differences can be intentionally formed on the photoresist layer. In order to form a difference in film thickness on the photoresist layer, it is necessary to form a half-tone area on the photomask, and to allow a smaller amount of light to pass through this area than the amount of light passing through the transparent substrate. A method using a graytone mask and a method using a half tone mask are known as methods for forming halftone regions. The so-called gray tone mask is a mask in which minute patterns that become unresolvable in the photolithographic process are arranged in slits or grids to control the amount of light transmitted through the parts. A halftone mask is a mask in which half-tone areas are formed with a semi-transparent film.

0005

Patent Document 2 discloses a method for manufacturing an inverse stacked liquid crystal display device with an electrostatic protection circuit portion using four mask technology, and Patent Document 3 discloses a method for manufacturing a lateral electric field driven liquid crystal display. In addition, Patent Document 4 discloses a method of manufacturing a liquid crystal display device including an inverted staggered TFT that uses both a lift-off method and a multi-tone exposure technique to reduce the manufacturing process.

Patent Document 1: Japanese Unexamined Patent Publication No. 11-64884

Patent Document 2: Figures 1 to 3 of JP-A-2002-26333, paragraph numbers 0037-0047

Patent Document 3: Figures 7 to 10 of JP-A-2004-318076, paragraph numbers 0022-0028

Patent Document 4: Figures 2 to 6 and Figure 11 of JP-A-2007-59926, paragraph numbers 0042-0060 and 0074-0079

Patent Document 5: JP-A-2003-172946

Contents of the invention

0006

The above-mentioned Patent Document 2 discloses a method in which a transparent conductive film (transparent electrode layer) is formed on the source/drain electrodes without an interlayer insulating film, and the source/drain electrodes are electrically connected to the gate electrodes through the transparent conductive film. structure. However, the volume resistivity of ITO, ITZO, or IZO, which is generally used as a transparent conductive film, is about double digits higher than that of metal materials generally used for gate electrodes and source/drain electrodes. Therefore, if the source/drain electrode and the gate electrode are electrically connected via a transparent conductive film, it is necessary to secure a sufficient contact area with the transparent conductive film in order to suppress an increase in resistance.

0007

The liquid crystal display device described in the above-mentioned Patent Document 3 has a structure that does not use a transparent conductive film such as ITO, and thus can achieve cost reduction. However, there is a problem that the metal of the terminal portion is easily corroded by the external atmosphere because the metal is exposed in the opening portion serving as the terminal portion for inputting an external signal or the like. In addition, in the above-mentioned Patent Document 3, since the contact hole is provided on the stacked film of the gate insulating film and the semiconductor layer, there is a possibility that a surface step may be formed on a part of the contact hole, and the conductive film disposed on the upper layer and inside the contact hole may The cover layer on the contact hole portion of the chip deteriorates, causing problems such as disconnection.

0008

The aforementioned Patent Document 4 discloses a structure in which a Cr conductive film constituting a gate electrode is electrically connected to a metal conductive film constituting a source/drain electrode via a transparent conductive film. Therefore, similarly to the above-mentioned Patent Document 2, in order to suppress an increase in resistance, it is necessary to secure a sufficient contact area with the transparent conductive film.

0009

Recently, demands for securing a display area and miniaturizing the entire display device are increasing. Therefore, a structure in which the frame area defined outside the display area is reduced is required. In addition, highly reliable display devices are required.

0010

The present invention is made in view of the above-mentioned background, and an object of the present invention is to provide a thin film transistor array substrate manufacturing method and a display device that can narrow the frame, have excellent reliability, and further reduce the cost.

0011

The manufacturing method of the thin film transistor array substrate of the present invention comprises: a step of forming a pattern composed of a first conductive film on the substrate; a step of sequentially stacking a gate insulating film, a semiconductor layer and a photoresist layer on the first conductive film; Disposing a photomask on the upper part of the above-mentioned photoresist layer, adopting a photolithography process to form a photoresist pattern with a step structure along the thickness direction; using the above-mentioned photoresist pattern to form the exposed area of the above-mentioned first conductive film and A step of patterning the semiconductor layer; a step of forming a pattern of a second conductive film in contact with the first conductive film in the exposed region of the first conductive film; film and the third conductive film constitute the process of each pattern.

Furthermore, the gate electrode of the thin film transistor is formed of the above-mentioned first conductive film, the source electrode and the drain electrode are formed of the above-mentioned second conductive film, and the pixel electrodes are formed of the above-mentioned third conductive film. In addition, the above-mentioned second conductive film is covered with an upper layer film.

0012

The present invention has the following excellent effects: it can provide a manufacturing method and a display device of a thin-film transistor array substrate that realize narrow borders, have excellent reliability, and can be further reduced in cost.

Description of drawings

0089

FIG. 1 is a partially enlarged schematic top view of a TFT array substrate in Embodiment 1. FIG.

FIG. 2 is a schematic circuit diagram of the vicinity of a pixel in Embodiment 1. FIG.

FIG. 3 is a cross-sectional view of a TFT of Example 1. FIG.

FIG. 4 is a top view of the vicinity of a wiring conversion portion in Embodiment 1. FIG.

FIG. 5 is a cross-sectional view of the vicinity of the wiring conversion portion of the first embodiment.

6( a ) to ( c ) are manufacturing process diagrams of the TFT array substrate of the first embodiment.

7( a ) to ( c ) are manufacturing process diagrams of the TFT array substrate of the first embodiment.

8( a ) to ( c ) are manufacturing process diagrams of the TFT array substrate of the first embodiment.

9( a ) to ( c ) are manufacturing process diagrams of the TFT array substrate of the second embodiment.

FIG. 10( a ) is a circuit diagram of a TFT formed on the driver circuit unit, and FIG. 10( b ) is a schematic top view of a TFT in the driver circuit unit of the third embodiment.

11( a ) is a schematic plan view of a liquid crystal display panel of Example 4, and FIG. 11( b ) is a cross-sectional view of a terminal portion.

FIG. 12 is a top view of the vicinity of the wiring conversion portion of the TFT array substrate of Comparative Example 1. FIG.

Fig. 13 is a cross-sectional view taken at XIII-XIII of Fig. 12 .

FIG. 14 is a partially enlarged top view of a drive circuit portion of a TFT array substrate of Comparative Example 2. FIG.

15 is a cross-sectional view of a terminal portion of a TFT array substrate of Comparative Example 3. FIG.

Explanation of reference signs

0090

1 insulating substrate

2 Gate insulating film

4 semiconductor layer

5 Interlayer insulating film

6 TFT

7 hold capacitor

10 The first conductive film

11 Gate Wiring

12 Gate terminal

13 Shared capacitor wiring

15 Common capacitance electrode layer

16 Gate electrode

20 Second conductive film

21 Source wiring

22 source terminal

23 Public Wiring

24 common terminal

25 source electrode

26 drain electrode

30 The third conductive film

31 pixel electrodes

33 connection layer

41 1st photoresist pattern

42 Second photoresist pattern

50 display area

51 border area

53 Wiring Conversion Department

54 TFT formation area

55 shading area

56 Translucent area

57 semi-transparent area

58 Gate wiring area

59 Source wiring area

60 Drive circuit configuration area

61 1st opening

62 2nd contact hole

71 External terminal area

80 TFT array substrate

81 LCD display panel

Detailed ways

0013

An embodiment employing the present invention will be described below. In addition, it goes without saying that as long as they conform to the gist of the present invention, other embodiments also belong to the category of the present invention. In addition, the dimensions and ratios of the components in the following drawings are for convenience of description and are not limiting.

0014

Example 1

The display device of the first embodiment is a display device including an active matrix TFT array substrate having a thin film transistor (TFT) having an inverse stacked MOS structure as a switching element. Here, a light-transmissive liquid crystal display device will be described as an example of a display device.

0015

FIG. 1 is a plan view of a TFT array substrate 80 of the first embodiment. As shown in FIG. 1 , the TFT array substrate 80 includes a gate wiring 11, a gate wiring side terminal 12, a common capacitor wiring 13, a source wiring 21, a source wiring side terminal 22, a common wiring 23, a common terminal 24, and a pixel electrode. 31 etc.

0016

The gate wiring 11 extends in the lateral direction in FIG. 1 , and a plurality of them are arranged side by side in the vertical direction. The source wiring 21 extends in the vertical direction in FIG. 1 , and a plurality of them are arranged side by side in the lateral direction, and intersect via the gate wiring 11 and a gate insulating layer (not shown). A plurality of gate wirings 11 and a plurality of source wirings 21 substantially vertically intersect to form a matrix, and pixel electrodes 31 are formed in regions surrounded by adjacent gate wirings 11 and source wirings 21 . This area functions as a pixel, and the area where a plurality of pixels are formed is the display area 50 . The area divided outside the display area 50 is a frame area 51 .

0017

A plurality of gate wiring side terminals 12 are arranged on the left side of the frame area 51 in the drawing, and each gate wiring 11 extends from the display area 50 to the terminal. Similarly, a plurality of source wiring-side terminals 22 are arranged on the upper side of the frame region 5 in the figure, and each source wiring 21 extends from the display region 50 to this terminal.

0018

The common capacitance wiring 13 for forming a capacitor is provided in parallel with the gate wiring 11 in each pixel, and is connected to the common wiring 23 in the frame region 51 . The common wiring 23 is formed at the end where the plurality of source wirings 21 are arranged, and is formed in parallel with the source wirings using a second conductive film which is the same layer as the source wirings 21 . In addition, the common wiring 23 extends to the common terminal 24 . The common terminal 24 is a terminal for externally supplying a common potential, and is arranged at one end of a plurality of source wiring side terminals 22 arranged in a row in the example of FIG. 1 .

0019

FIG. 2 shows a schematic circuit diagram of the adjacent area indicated at 52 in FIG. 1 . As shown in FIG. 2 , at least one TFT 6 for signal transmission is provided near the intersection of the gate wiring 11 and the source wiring 21 of each pixel. The gate electrode of the TFT 6 formed on the pixel is connected to the gate wiring 11, and the source electrode of the TFT 6 is connected to the source wiring 21.

0020

When a signal is supplied to the gate wiring 11 , the signal charge transferred from the source wiring 21 is written into the pixel, and the charge is stored in the storage capacitor 7 . At this time, the pixel electrode 31 applies a potential corresponding to the signal to be written to the liquid crystal to display a desired image. The pixel electrode 31 is used as an electrode for storing signal charges of each pixel, and the common capacitance line 13 is used as a counter electrode. The common capacitor wiring 13 is formed of the same layer (first conductive film) as the gate wiring 11, and is arranged to intersect the source wiring 21 via a gate insulating layer in order to connect to all the pixels.

0021

FIG. 3 shows a schematic cross-sectional view of the vicinity of TFT 6 in the first embodiment. TFT 6 is a reverse stack type, manufactured by channel etching (CE (channel etching). As shown in FIG. Layer 4a, second semiconductor layer 4b, source electrode 25, drain electrode 26, interlayer insulating film 5, pixel electrode 31, and the like.

0022

As the insulating substrate 1, a transparent substrate such as a glass substrate or a quartz substrate is used. The gate electrode 16 is formed on the insulating substrate 1, and the same layer as the gate wiring 11, the common capacitance wiring 13, the common capacitance electrode layer 15, etc., that is, the first conductive film is used. A gate insulating film 2 is formed thereon so as to cover the gate electrode 16 . The first semiconductor layer 4 a is formed on the gate insulating film 2 , and at least a part thereof is arranged to face the gate electrode 16 via the gate insulating film 2 .

0023

The second semiconductor layer 4b is formed on the upper layer of the first semiconductor layer 4a. The source electrode 25 and the drain electrode 26 are formed on the second semiconductor layer 4b. The region of the second semiconductor layer 4b on which the source electrode 25 is stacked becomes a source region, and the region of the second semiconductor layer 4b on which the drain electrode 26 is stacked becomes a drain region. The first semiconductor layer 4a is sandwiched by the first semiconductor layer 4a located under the source region and the drain region, and the region excluding the second semiconductor layer 4b is a channel region.

0024

The source electrode 25 and the drain electrode 26 are arranged to face at least a part of the gate electrode 16 with the gate insulating film 2 , the first semiconductor layer 4 a , and the second semiconductor layer 4 b interposed therebetween. That is, in order to operate as a TFT, the channel region is located on the gate electrode 16 and is in a state that is easily affected by an electric field when a voltage is applied to the gate electrode 16 .

0025

The interlayer insulating film 5 is formed to cover the channel region, the source electrode 25 and the drain electrode 26 (see FIG. 3 ). Then, the pixel electrode 31 is formed on the interlayer insulating film 5 . The pixel electrode 31 is electrically connected to the drain electrode 26 through a second contact hole 62 formed on the interlayer insulating film 5 .

0026

Next, a method of electrically connecting the common capacitance wiring 13 and the common wiring 23 will be described. As described above, the common capacitance wiring 13 for forming a capacitor is composed of the first conductive film 10 which is the same layer as the gate wiring 11, and the common wiring 23 is composed of the second conductive film which is the same layer as the source wiring 21. 20 poses. Furthermore, in the frame region 51 , the common capacitor wiring 13 is electrically connected to the common wiring 23 . As the "first conductive film", a material generally used to form a gate electrode of a thin film transistor is used, and as the "second conductive film", a material generally used to form a source/drain electrode of a thin film transistor is used. That is, a film composed of metal or a material mainly composed of metal, that is, a material having volume resistivity at the same level as metal is used.

0027

First, the method of electrically connecting the shared capacitance wiring and the common wiring in Comparative Example 1 will be described with reference to FIGS. 12 and 13 . 12 is a schematic top view of the vicinity of the wiring conversion portion between the common capacitor wiring and the common wiring in Comparative Example 1, and FIG. 13 is a cross-sectional view taken along line XIII-XIII of FIG. 12 . 12 omits the illustration of the interlayer insulating film 105 and the gate insulating film 102, and shows the positions where the first contact hole 161 and the second contact hole 162 are formed.

0028

As shown in FIG. 13 , the wiring conversion portion 153 on the TFT array substrate 200 includes an insulating substrate 101 , a common capacitor electrode layer 115 , a gate insulating film 102 , a common wiring 123 , an interlayer insulating film 105 , and a connection layer 133 .

0029

The common capacitor electrode layer 115 is formed on the insulating substrate 101, and is formed of the first conductive film 110 which is the same layer as the gate wiring 111, the common capacitor wiring 113, and the gate electrode (not shown). A gate insulating film 102 is formed thereon to cover the common capacitance electrode layer 115 . In addition, the common wiring 123 is formed on the gate insulating film 102 and is arranged to face the common capacitance electrode layer 115 with the gate insulating film 102 interposed therebetween. The common wiring 123 is formed of the second conductive film 120 which is the same layer as the source wiring, source/drain electrodes, and the like.

0030

In order to cover the common wiring 123 and the gate insulating film 102, an interlayer insulating film 105 is formed. Then, the connection layer 133 is formed on the interlayer insulating film 105 . The connection layer 133 is electrically connected to the common wiring 123 through the first contact hole 161 penetrating the interlayer insulating film 105 . Similarly, the common capacitor electrode layer 115 is electrically connected to the connection layer 133 through the second contact hole 162 penetrating the interlayer insulating film 105 and the gate insulating film 102 . Accordingly, the external potential supplied from the common terminal 124 is transmitted to the common capacitor electrode layer 115 via the common wiring 123 and the connection layer 133 , and supplied to the common capacitor wiring 113 . Furthermore, the connection layer 133 is made of the same conductive film as the layer constituting the pixel electrode.

0031

As shown in FIG. 13 , in order to transmit signals from the common wiring 123 to the common capacitor electrode layer 115 in the wiring conversion portion 153 of Comparative Example 1, a first contact hole 161 is formed on the common wiring 123 and a hole penetrating through the common wiring 123 is also formed. The second contact hole 162 .

0032

In the wiring conversion portion 153 of Comparative Example 1, the connection layer 133 used to connect the common wiring 123 and the common capacitor electrode layer 115 is usually made of a transparent conductive film material such as ITO for a fully transparent liquid crystal display device. As described above, the volume resistivity of ITO and the like is about 2 orders of magnitude higher than that of metals. Therefore, when using ITO or the like as the material of the connection layer 133 , it is necessary to have a large contact area.

0033

Furthermore, in Comparative Example 1 above, the first contact hole 161 and the second contact hole 162 for connecting the common wiring 123 to the common capacitor electrode layer 115 need to be formed after the interlayer insulating film 105 is formed and the pixel electrode 131 is formed. formed in the previous process.

0034

Next, the method of electrically connecting the common capacitor wiring and the common wiring in the first embodiment will be described with reference to FIGS. 4 and 5 . FIG. 4 is a schematic top view of the vicinity of the wiring conversion portion of the common capacitor wiring and the common wiring in the first embodiment, and FIG. 5 is a cross-sectional view taken along line V-V in FIG. 4 . In addition, for convenience of description, illustration of the interlayer insulating film 5 and the gate insulating film 2 is omitted in FIG. 4 , and the formation positions of the first openings 61 are shown by dotted lines.

0035

As shown in FIG. 5 , in the wiring conversion portion 53 on the TFT array substrate 80 , there are an insulating substrate 1 , a common capacitor electrode layer 15 , a gate insulating film 2 , a common wiring 23 , and an interlayer insulating film 5 . In addition, a first opening 61 for connecting the common capacitance electrode layer 15 to the common wiring 23 is formed on the gate insulating film 2 . In the example of FIG. 5 , it was described that the first opening 61 is formed in a slit shape, but the present invention is not limited thereto, and a plurality of contact holes in shapes such as squares and circles may be arranged.

0036

The common capacitor electrode layer 15 is formed on the insulating substrate 1, and is formed of the first conductive film 10 which is the same layer as the gate wiring 11, the common capacitor wiring 13, and the gate electrode (not shown). A gate insulating film 2 is formed thereon so as to cover the common capacitance electrode layer 1 . In addition, the common wiring 23 is formed on the gate insulating film 2 , and at least a part thereof is connected to the common capacitor electrode layer 15 through the first opening 61 of the gate insulating film 2 . The common wiring 23 is formed of the second conductive film 20 which is the same layer as the source wiring, source/drain electrodes, and the like.

0037

The interlayer insulating film 5 is formed to cover the common wiring 23 and the gate insulating film 2 . In the first embodiment, the common wiring 23 and the common capacitor electrode layer 15 are not made of a film corresponding to the connection layer 133 of the above-mentioned comparative example 1, but are electrically connected through the first opening 61 formed on the gate insulating film 2. . Accordingly, the external potential supplied from the common terminal 24 is transmitted to the common capacitance electrode layer 15 via the common wiring 23 and supplied to the common capacitance wiring 13 . In addition, in the following description, the region where the first conductive film 10 and the second conductive film 20 are directly connected is referred to as a "conductive film connection region". An upper layer film is formed on the upper layer of the second conductive film in the conductive film connection region.

0038

Recently, various display devices typified by liquid crystal display devices have been required to be further reduced in size and weight. Especially for small liquid crystal display panels with a diagonal size less than about 3 inches used in mobile phones, it is very necessary to reduce the area of the frame area in order to ensure a wide display area 50 .

0039

According to the TFT array substrate 80 of the first embodiment, the width of the wiring transition portion 53 can be narrowed. In the above-mentioned Comparative Example 1, the width of the wiring conversion portion 153 needs to be about 100 μm. On the other hand, the width of the wiring conversion portion 53 in the first embodiment can be set to about 10 μm, for example. According to the first embodiment, since the common capacitance electrode layer 15 is directly connected to the common wiring 23, the pattern of contact holes can be reduced compared to the case of using the connection layer 133 which is a conductive film constituting the pixel electrode. In addition, since the first conductive film and the second conductive film can be contacted and connected without intervening through ITO or the like having a high volume resistivity, the contact area can be reduced. In addition, since the structure is simpler than the case of connecting via the conductive film constituting the pixel electrode, the manufacturing yield can be improved. In addition, as described above, in the above-mentioned Patent Document 3, a contact hole is provided on the laminated film of the gate insulating film and the semiconductor layer, so there is a possibility that a surface step may occur in a part of the contact hole, and disconnection due to poor coverage may occur. question. On the other hand, according to the TFT array substrate 80 of the first embodiment, the first conductive film and the second conductive film are brought into contact through the opening formed in the gate insulating film, and the conductive film covered by the upper film on the second conductive film is In the film connection region, the second conductive film is directly laminated without forming a semiconductor layer directly on the gate insulating film. In other words, the contact hole is formed only on the gate insulating film. Therefore, it is possible to prevent surface steps from being generated in a part of the contact hole, and it is possible to effectively prevent problems such as disconnection due to poor coverage.

0040

Next, a method of manufacturing the TFT array substrate configured as described above will be described with reference to FIGS. 6 to 8 . In FIGS. 6 to 8 , the right side of the figure shows the TFT formation region 54 , and the left side of the figure shows the cross-sectional structure of the wiring transition portion 53 .

0041

First, the first conductive film 10 is formed on an insulating substrate 1 such as a glass substrate by a method such as vapor deposition. The first conductive film is, for example, Cr, Al, Mo, W, or an alloy mainly composed of these metals, or a laminated film of these metals. Then, through a photolithography process, an etching process, and a photoresist layer removal process, etc., the gate wiring 11, the common capacitance electrode layer 15, the gate electrode 16, etc. of a desired shape are formed.

0042

Next, after a cleaning process etc., various CVD methods such as plasma CVD (Chemical Vapor Deposition) are used to sequentially deposit the gate insulating film 2 on the gate electrode 16 and the like and the insulating substrate 1, and the first layer serving as the semiconductor layer. The semiconductor layer 4 a and the second semiconductor layer 4 b (see FIG. 6( a )). The gate insulating film 2 is made of SiNx, SiOy, or the like. The first semiconductor layer 4a is a so-called true semiconductor that is a pure semiconductor that does not contain conductive impurities. As the first semiconductor layer 4a, a-Si (amorphous silicon) or the like is used. As the second semiconductor layer 4b, an n-type semiconductor is used, that is, a-Si is slightly doped with (doping) P (phosphorus ( phosphorus)) and other n ⁺ a-Si (n ⁺ amorphous silicon) films, etc.

0043

The first semiconductor layer 4a and the second semiconductor layer 4b are preferably formed in the same chamber. By forming the first semiconductor layer 4a and the second semiconductor layer 4b in the same chamber, the electrical connection resistance between the two types of silicon (silicon) layers can be reduced. Of course, the gate insulating film 2 may also be formed in the same chamber. Hereinafter, when it is not necessary to distinguish between the first semiconductor layer 4 a and the second semiconductor layer 4 b, both are collectively referred to as the semiconductor layer 4 .

0044

Next, a photosensitive resin, that is, photoresist, is coated on the semiconductor layer 4 by a spin coat method. Then, the coated photoresist layer is exposed using a photomask (not shown). As shown in FIG. 6( b ), as a photomask, a light-shielding area 55 , a light-transmitting area 56 , and a half-tone exposure area 57 whose light transmittance is lower than that of the light-transmitting area 56 are arranged in a desired pattern and used. Then, a series of photoplate-making processes such as exposure and development are carried out. Specifically, the part where the first opening 61 is formed on the common electrode layer 15 is the light-transmitting region 56, the part where the semiconductor layer 4 remains as an island is the light-shielding region 55, and the region where the semiconductor layer 4 is removed is the halftone exposure region. 57.

0045

Thereby, the photoresist layer in the exposed part is removed, and the 1st photoresist pattern 41 shown in FIG.6(b) is obtained. That is, by removing the photoresist layer in the light-transmitting region 56, the semiconductor layer 4 is exposed on the surface. In the unexposed portion, that is, the light-shielding region 55, the photoresist layer is not removed, and a photoresist pattern with a predetermined film thickness is formed. In the half-exposed portion, that is, the half-tone translucent region 15 , the photoresist layer is removed to the extent that the surface of the semiconductor layer 4 is not exposed, and a pattern having a film thickness thinner than the predetermined film thickness of the light-shielding region 55 is formed. In other words, the first photoresist pattern 41 can have a pattern having two step structures along the film thickness direction through the unexposed portion and the half-exposed portion.

0046

Next, etching treatment is performed. Thereby, the exposed semiconductor layer 4 and the gate insulating film 2 located therebelow are removed, and the first opening 61 is formed in the gate wiring 12 (see FIG. 6( c )). Then, the thin film portion of the first photoresist pattern 41 is removed, followed by ashing treatment to expose the semiconductor layer 4 located therebelow (see FIG. 7( a )). Well-known devices such as RIE-DE device and UV asher (UV Asher) can be used for the ashing treatment. After the ashing process, the thicker region of the light-shielding region 55 is also thinned by ashing, but remains as a photoresist pattern.

0047

By ashing the first resist pattern 41, the second resist pattern 42 shown in FIG. 7(a) is obtained. The second photoresist pattern 42 is formed of a pattern corresponding to a region where the semiconductor layer 4 is to be an island.

0048

The exposed semiconductor layer 4 is removed by etching using the second photoresist pattern 42 as a mask (see FIG. 7( b )). In this way, the semiconductor layer 4 where the TFT is formed becomes an isolated island, and a desired pattern is formed. In addition, the common capacitive electrode layer 15 is exposed in the first opening 61, but Al, Cr, Mo, W, and alloy metals mainly composed of these metals are generally used on the common capacitive electrode layer 15, so it can sufficiently The selectivity for etching of the semiconductor layer 4 is ensured. Next, the exposed semiconductor layer 4 is removed by etching, and then the second photoresist pattern 42 is removed.

0049

Then, a second conductive film 20 is formed by sputtering or the like so as to cover the common capacitance electrode layer 15, the gate insulating film 2, and the semiconductor layer 4 (see FIG. 7(c)). Next, a third photoresist pattern 43 is formed by a photolithography process (see FIG. 8( a )). Then, etching is performed using the third photoresist pattern 43 as a mask to obtain the source electrode 25, the drain electrode 26, the source wiring 21, the common wiring 23, and the like in desired shapes. Then, a part of the semiconductor layer 4 at the back channel portion of the TFT 6 is etched. At this time, by cutting off the second semiconductor layer 4b on the side of the source electrode 25 and the side of the drain electrode 26, a TFT serving as a switching element is formed (see FIG. 8(b)).

0050

Then, interlayer insulating film 5 is formed by various CVD methods such as plasma CVD to cover gate insulating film 2, channel region, source electrode 25, drain electrode 26, common wiring 23, etc. (see FIG. 8(c)). As the interlayer insulating film 5, _SiNx , _SiOy, etc., or their mixtures and laminates can be used. When the TFT 6 is mounted on a liquid crystal display device, the second photoresist pattern 4 is removed, and then the second contact hole 62 is formed on the interlayer insulating film 5, and then the transparent conductive film 30 as the pixel electrode 31 is formed, The pixel electrode 31 is electrically connected to the drain electrode 26 through processes such as photolithography, etching, and removal of the photoresist layer. Through this series of steps, the wiring conversion portion 53 shown in FIG. 5 and the TFT 6 shown in FIG. 3 are formed on the substrate.

0051

In addition, the second conductive film 20 is covered with an upper layer film so as not to form an exposed region. As the upper layer film, a protective film such as an interlayer insulating film and a passivation film can be used. As the material of the upper layer film, an inorganic film such as a silicon nitride film or a silicon oxide film, or an organic insulating film may be used. In addition, these laminated films may also be used. In addition, in areas where conductivity is required on exposed surfaces such as terminal portions, transparent conductive films such as ITO, ITZO, and IZO can be appropriately used according to this specification.

0052

In addition, as a method of carrying out the above-mentioned halftone exposure, a so-called "half-tone mask" technique can be used, that is, a pattern is formed with a material having a certain light transmittance on a mask used for photolithography. In addition, a pattern mask of a geometric pattern such as a mesh or a checker and an L/S (line (line)/space ( space)) and other pattern masks. As described above, in the first embodiment, the exposed region of the first conductive film 10 can be formed, and the semiconductor layer 4 can be formed as an island, and a photoresist pattern having a stepped structure can be formed using a well-known photomask.

0053

The TFT array substrate, color filter substrate, backlight, liquid crystal, and the like manufactured as described above are mounted on a liquid crystal display device through a known manufacturing process.

0054

In Comparative Example 1 above, the first conductive film and the second conductive film were surrounded by insulating films in an independent state before the connection layer was formed using a transparent conductive film such as ITO. Therefore, when the glass substrate is charged during the process, there is a possibility of discharge between layers and between wirings on the same layer, and there is a risk that the display device as a product will become a defective product. According to the first embodiment, the connecting portion between the first conductive film 10 and the second conductive film 20 is formed at an early stage in the manufacturing process of the TFT array substrate. As a result, even when there is abnormal static electricity, since there is a connected area, a passage for abnormal static electricity to escape can be formed, and defective products can be effectively prevented.

0055

According to the first embodiment, the common capacitance electrode layer 15 made of the first conductive film 10 is electrically connected to the common wiring 23 made of the second conductive film 20 in the wiring conversion portion 53, so the common wiring 23 can be shortened. the wiring width. In addition, instead of using materials with high volume resistivity such as ITO, metal materials are used to connect each other, so that the contact area can be reduced. The result: the ability to make the bezels narrower.

0056

Also, according to the first embodiment, the second conductive film is not exposed by covering with the upper layer film (the interlayer insulating film in the first embodiment), so there is no fear of the second conductive film being corroded. As a result, a highly reliable TFT array substrate can be provided. There is no need to add a mask for forming an opening in the gate insulating film 2, and it is not necessary to add a photolithography process for connecting the first conductive film 10 and the second conductive film 20. That is to say, the above-mentioned effect can be obtained by using a process with a small number of photolithography. Therefore, cost reduction can be achieved.

0057

Furthermore, since the first conductive film 10 and the second conductive film 20 are in contact, the structure can be simplified compared to the case where the first conductive film and the second conductive film are connected via the connection layer 133 as in Comparative Example 1 above. In addition, since the first conductive film 10 and the second conductive film 20 are directly connected in the conductive film connection region, there is no coverage defect of the connection layer 133 as in Comparative Example 1 above. Therefore, entry of moisture or the like due to poor coverage can be prevented, and a highly reliable display device can be provided.

0058

Example 2

Next, an example of a method of manufacturing a TFT array substrate different from that of the first embodiment will be described. In addition, in the following description, the same components as those of the above-mentioned embodiment are given the same symbols, and the description thereof will be appropriately omitted.

0059

The manufacturing method of the TFT array substrate of the present embodiment 2 is the same as the manufacturing method of the above-mentioned embodiment 1 except for the following differences. The difference is: in the above-mentioned embodiment 1, the first photoresist pattern 41 is used as a mask, and the semiconductor layer 4 and the gate insulating film 2 are removed by etching; while in the second embodiment, the first photoresist pattern 41 is used As a mask, only the semiconductor layer 4 is first etched. In addition, after the second photoresist pattern 42 is formed, the exposed gate insulating film 2 is etched using the exposed semiconductor layer 4 as a mask, and then the exposed semiconductor layer 4 is etched.

0060

9( a ) to ( c ) are cross-sectional views for explaining the manufacturing process of the TFT array substrate of the second embodiment. Using the same method as in Embodiment 1 above, a gate electrode 16, a gate wiring 11, a gate insulating film 2, a semiconductor layer 4, and a first photoresist pattern 41 are formed on an insulating substrate 1 (see FIG. 6(b)). . Then, the semiconductor layer 4 is removed by etching using the first photoresist pattern 41 as a mask (see FIG. 9( a )).

0061

Then, the thin film portion of the first photoresist pattern 41 is removed, and an ashing process is performed to expose the semiconductor layer 4 located therebelow. By ashing the first photoresist pattern 41, the second photoresist pattern 42 shown in FIG. 9(b) is obtained. The second photoresist pattern 42 is formed of a pattern corresponding to a region to be an island in the semiconductor layer 4 .

0062

Next, the exposed gate insulating film 2 is removed by etching using the exposed semiconductor layer 4 as a mask (see FIG. 9( c )). Then, the exposed semiconductor layer 4 is removed by etching using the second photoresist pattern 42 as a mask. In this way, the semiconductor layer 4 where the TFT is formed becomes an isolated island, and a desired pattern is formed. After the exposed semiconductor layer 4 is removed by etching, the second photoresist pattern 42 is removed. Then, the wiring transition portion 53 shown in FIG. 5 and the TFT 6 shown in FIG. 3 are formed by the same method as in the first embodiment described above.

0063

According to the manufacturing method of the TFT array substrate of the second embodiment, it is possible to effectively prevent the gate electrode from being destroyed due to abnormal discharge. The reason is as follows: if the semiconductor layer 4 and the gate insulating film 2 are etched using the first photoresist pattern 41 as a mask to form the structure shown in FIG. The conductive material is the structure of the first conductive film 10 . In this case, if the state of the plasma is unstable during dry etching, abnormal discharge may occur depending on the situation, and the first conductive film 10 (common capacitor electrode layer 15 ) will be completely destroyed.

0064

According to the manufacturing method of the TFT array substrate of the second embodiment, most of the surface of the semiconductor layer 4 is exposed when the gate insulating film 2 is etched. Therefore, even when a part of the first conductive film 10 (common capacitance electrode layer 15) is exposed, the partial area of conductivity does not change rapidly, so that the gate electrode can be prevented from being destroyed by abnormal discharge.

0065

Example 3

Next, an example of forming a conductive film connection region in which the first conductive film 10 and the second conductive film 20 are in contact and connected in the drive circuit portion of the TFT array substrate will be described. The basic structure of the TFT array substrate of the third embodiment is the same as that of the first embodiment above.

0066

As described above, by connecting a liquid crystal driving semiconductor chip (chip) (hereinafter referred to as "IC" (Integrated Circuit)) equipped with a gate driver circuit and a source driver circuit (hereinafter referred to as "driver circuit") and a TFT array substrate, The terminal part is directly connected or connected via a flexible printed circuit board (hereinafter referred to as "FPC (Flexible Printed Circuit)"), etc., and a desired image is displayed. However, the IC needs to be prepared separately, so its cost is actually reflected in the manufacturing cost. Therefore, by forming circuits on the TFT array substrate while forming the TFTs of the pixels, ICs used can be reduced, and circuits with new functions can be formed, thereby increasing the added value of the display device. In the third embodiment, an example in which the present invention is applied when such a driving circuit is formed in the frame region 51 (see FIG. 1) of the TFT array substrate will be described.

0067

If a value-added circuit is mounted in addition to the minimum required functions as a display device, a connection portion 8 is provided between the source/drain electrodes and the gate electrode of TFT 6a as shown in FIG. Various logic circuits can be configured by combining the circuits provided with the connection portion 8 .

0068

FIG. 14 shows a schematic top view of the vicinity of the TFT 106a in the drive circuit of Comparative Example 2. 14 omits the illustration of the gate insulating film and the interlayer insulating film, and the conductive film constituting the connection layer is shown by thick solid lines. In addition, the positions where the contact holes are formed are shown by thick solid lines.

0069

As shown in FIG. 14, in the TFT 106a of the drive circuit of Comparative Example 2, the gate electrode 116 composed of the first conductive film 110, the source electrode 125 and the drain electrode 126 composed of the second conductive film 120 pass through the semiconductor layer 104 and the gate. Insulating films (not shown) are arranged facing each other. Furthermore, an interlayer insulating film (not shown) is formed on the source electrode 125 and the drain electrode 126, and the connection layer 133a made of the third conductive film 130 is disposed thereon. The connection layer 133a is electrically connected to the drain electrode 126 through a first contact hole 161a penetrating through an interlayer insulating film (not shown). Similarly, the connection layer 133a is electrically connected to the gate electrode 125 through the second contact hole 162a penetrating through the interlayer insulating film (not shown) and the gate insulating film (not shown). Thus, the gate electrode 125 is electrically connected to the source/drain electrodes.

0070

In the drive circuit section of Comparative Example 2, in order to electrically connect the gate electrode to the source/drain electrodes, as shown in FIG. 162a. In addition, as in Comparative Example 1, in a fully transparent liquid crystal display device, a transparent conductive film material such as ITO is generally used as the connection layer 133 a. As mentioned above, the volume resistivity of ITO etc. is 2 places higher than metal. Therefore, when using ITO or the like as the material of the connection layer 133a, it is necessary to take a large contact area.

0071

On the other hand, as shown in FIG. 10(b), in the third embodiment, the drain electrode 26a is in contact with the gate electrode 16a to form a connection between metals. Therefore, compared with the case where ITO and metal are connected, it is possible to Reduce the contact area of the connection part. Therefore, required connection can be performed in a small area, and the frame can be narrowed.

0072

In addition, in the drive circuit, in order to reduce the delay of the drive signal as much as possible, it is desirable that the wiring resistance and the contact resistance be small. According to the third embodiment, the layer of the first conductive film made of metal with high conductivity is in contact with the layer of the second conductive film not through ITO having high resistance, so that a high-performance drive circuit can be provided.

0073

In addition, according to the manufacturing method of the third embodiment, without increasing the number of photolithography steps, it is possible to form a driving circuit having a contact portion between metal wirings (first conductive film and second conductive film) at a desired position. . In addition, since the source electrode 25a and the drain electrode 26a made of the second conductive film 20 are not exposed by covering with the interlayer insulating film 5, there is no possibility of corroding the wiring. As a result, it is possible to provide a display device with reduced cost and high reliability.

0074

Example 4

An example in which a conductive film connection region for directly connecting the first conductive film 10 and the second conductive film 20 is formed on the terminal of the TFT array substrate will be described. The basic structure of the TFT array substrate of the fourth embodiment is the same as that of the first embodiment above.

0075

Fig. 11(a) shows a schematic top view of a liquid crystal display panel (panel) of the fourth embodiment. Here, as in the third embodiment described above, a case where a driving circuit and the like are packaged using COG (Chip on Glass) technology will be described. As described above, the liquid crystal display panel 81 includes the display area 50 and the frame area 51 (see FIG. 1 ) defined outside the display area 50 . In addition, as shown in FIG. 11( a ), the frame area 51 has a gate wiring area (area) 58 , a source wiring area 59 , a driver circuit mounting area 60 , an external terminal area 71 , and the like.

0076

The gate wiring 11 extends from the display area 50 to the driver circuit mounting area 60 via the gate wiring area 58 of the frame area 51 . Similarly, the source wiring 21 is also extended from the display area 50 to the driver circuit mounting area 60 via the source wiring area 59 of the frame area 51 .

0077

The external terminal area 71 and the drive circuit mounting area 60 are connected via wiring (not shown). External signals are transmitted from FPC (Flexible Printed Circuit) or the like to terminals (not shown) formed on the external terminal area 71 . Then, various signals from the outside are transmitted from the external terminal area 71 to a driving circuit (not shown) located in the driving circuit mounting area 60 . A gate terminal of the gate wiring 11 and a source terminal of the source wiring 21 are arranged in the driver circuit mounting region 6a. Then, the drive circuit supplies a gate signal to the gate wiring and a display signal to the source wiring in accordance with an external control signal. Thus, a display voltage corresponding to display data is transmitted to each pixel electrode.

0078

FIG. 15 is a schematic cross-sectional view of the gate terminal 112 and the source terminal 122 in the drive circuit mounting region of Comparative Example 3. As shown in FIG. In FIG. 15 , the left side of the figure shows the vicinity of the gate terminal 112 , and the right side of the figure shows the vicinity of the source terminal 122 .

0079

In Comparative Example 3, the pattern of the first conductive film 110, which is the same layer as the gate electrode 116, is formed on the gate terminal 112, and the third conductive film 130 is connected through the third contact hole 163 formed on the gate insulating film 102. Layer 133 is connected to first conductive film 110 . Similarly, the pattern of the second conductive film 120, which is the same layer as the source electrode 126, is formed on the source terminal 122, and the connection layer 133, which is the third conductive film 130, is connected through the fourth contact hole 164 formed on the interlayer insulating film 105. connect. That is, the layers of the first conductive film 110 and the third conductive film 130 are used for the gate terminal 112 , and the layers of the second conductive film 120 and the third conductive film 130 are used for the source terminal 122 . Therefore, for the gate terminal 112 and the source terminal 122 , as shown in FIG. 15 , the height H11 of the gate terminal 112 is different from the height H12 of the source terminal 122 .

0080

If the heights of the gate terminal 112 and the source terminal 122 are different, when using a drive circuit in which the gate drive circuit and the source drive circuit are mounted on the same chip, the one with the lower terminal height may have poor connection. Especially in the case of a small panel or the like, a single IC including two circuits, a gate driver circuit and a source driver circuit, may be used, and thus poor connections are likely to occur.

0081

FIG. 11( b ) shows a schematic cross-sectional view of the gate terminal 12 and the source terminal 22 in the driving circuit mounting region of the fourth embodiment. In FIG. 11( b ), the left side of the figure shows the vicinity of the gate terminal 12 , and the right side of the figure shows the vicinity of the source terminal 22 .

0082

In Embodiment 4, the pattern of the first conductive film 10, which is the same layer as the gate electrode 16, is formed on the gate terminal 12, and the pattern of the second conductive film 20 is formed through the contact hole formed on the gate insulating film 2. The third conductive film 30 in the upper layer is connected to the second conductive film 20 . Similarly, the pattern of the first conductive film 10, which is the same layer as the gate electrode 16, is also formed on the source terminal 22, and the pattern of the second conductive film 20 is formed through the contact hole formed on the gate insulating film 2. The third conductive film 30 is connected to the second conductive film 20 . Therefore, with regard to the gate terminal 12 and the source terminal 22 , as shown in FIG. 11( b ), the height H1 of the gate terminal 12 is the same as the height H2 of the source terminal 22 .

0083

According to the fourth embodiment, the gate terminal 12 and the source terminal 22 are configured with the same structure, so the problem of the above-mentioned comparative example 3 can be solved. That is, according to Embodiment 4, since the terminal heights of the gate terminal 12 and the source terminal 22 are the same, poor connection in the terminal portion can be prevented.

0084

In addition, it is conceivable to adopt the system of the above-mentioned comparative example 1, and make the structures of the gate terminal and the source terminal the same. For example, in this method, either one of the gate wiring and the source wiring is provided with a conversion part in the middle of the wiring, and both the gate terminal and the source terminal are provided in the same manner as shown in FIG. 15 . The structure of either the gate terminal 112 or the source terminal 122 is uniform, and the height thereof is uniform. However, if the same structure as Comparative Example 1 is selected, that is, the structure in which the first conductive film and the second conductive film are connected via the third conductive film, the area of the frame region increases with the formation area of the contact hole or the like. In addition, the resistance of the total wiring rises as the wiring transitions, which is not conducive to improvement of display characteristics.

0085

Example 5

In Embodiment 5, an example in which the present invention is applied to a protection circuit of a TFT array substrate will be described. The basic structure of the TFT array substrate of the fifth embodiment is the same as that of the first embodiment above.

0086

In the protection circuit, as in the drive circuit described in Embodiment 3, by providing a connection portion 8 between the source/drain electrodes and the gate electrodes of the TFT in the protection circuit (see FIG. 10(a)), each kind of logic circuit. As shown in FIG. 10(b), by providing a region where the first conductive film 10 and the second conductive film 20 are in contact, the same effect as that of the drive circuit of the above-mentioned embodiment 3 can be obtained in the protection circuit of the fifth embodiment. .

0087

According to the fifth embodiment, it is possible to obtain effects such as preventing the metal wiring in the conductive film connection region (first conductive film 10 and second conductive film 20 ) from being corroded, reducing contact resistance, and reducing the area of the frame region 51 .

0088

In addition, the present invention is not limited to the application examples described in Embodiments 1 to 5 above. For example, it can also be used for inspection circuits, etc. In other words, the present invention can be applied to all positions where the first conductive film and the second conductive film need to be connected. In addition, in the above-mentioned Embodiments 1 to 5, examples in which a TFT array substrate is mounted on a liquid crystal display device have been described, but the present invention is not limited thereto, and can be applied to all display devices such as EL display devices.

Claims (11)

1. A method for manufacturing a thin film transistor array substrate, characterized in that, The method includes the following steps: forming a pattern composed of a first conductive film on a substrate; sequentially stacking a gate insulating film, a semiconductor layer and a photoresist layer on the first conductive film; A photomask is arranged on the upper part of the photoresist layer, and a photoresist pattern with a stepped structure along the thickness direction is formed by a photolithography process; using the photoresist pattern to form the exposed region of the first conductive film and the pattern of the semiconductor layer; forming a pattern consisting of a second conductive film in contact with the first conductive film in the exposed area of the first conductive film; and Forming each pattern composed of an interlayer insulating film and a third conductive film on the upper layer of the second conductive film, The first conductive film and the second conductive film have a conductive film connection region, and the conductive film connection region includes a region where they directly contact through an opening formed in the gate insulating film, and includes an upper layer film covering the The region of the second conductive film, A gate electrode of a thin film transistor is formed using the first conductive film, a source electrode and a drain electrode of the thin film transistor are formed using the second conductive film, and a pixel electrode is formed using the third conductive film. 2. The method for manufacturing a thin film transistor array substrate as claimed in claim 1, wherein: In the step of forming the exposed region of the first conductive film and the pattern of the semiconductor layer: using the photoresist pattern as a mask to etch the semiconductor layer and the gate insulating film to obtain an exposed region of the first conductive film, forming a second photoresist pattern, leaving a portion with a large film thickness of the photoresist pattern as a pattern, The semiconductor layer is etched using the second photoresist pattern as a mask to obtain a pattern of the semiconductor layer. 3. The method for manufacturing a thin film transistor array substrate as claimed in claim 1, wherein: In the step of forming the exposed region of the first conductive film and the pattern of the semiconductor layer: etching the semiconductor layer using the photoresist pattern as a mask, Forming the 2nd photoresist pattern, making the part with thicker film in the photoresist pattern remain as pattern, Next, using the semiconductor layer exposed through the second photoresist pattern as a mask to etch the gate insulating film to obtain an exposed region of the first conductive film, The semiconductor layer is etched using the second photoresist pattern as a mask to obtain a pattern of the semiconductor layer. 4. The method for manufacturing a thin film transistor array substrate as claimed in claim 1, wherein: The second conductive film in the conductive film connection region is formed in the opening formed in the gate insulating film and directly above the gate insulating film. 5. The method for manufacturing a thin film transistor array substrate as claimed in claim 1, wherein: The third conductive film is a transparent conductive film. 6. The manufacturing method of the thin film transistor array substrate as claimed in claim 1, characterized in that: The conductive film connection region is formed in a connection region between the wiring made of the first conductive film and the wiring made of the second conductive film. 7. The method for manufacturing a thin film transistor array substrate as claimed in claim 1, wherein: The conductive film connection area is formed on the driving circuit. 8. The method for manufacturing a thin film transistor array substrate as claimed in claim 1, wherein: The conductive film connection area is formed on the terminal. 9. The method for manufacturing a thin film transistor array substrate as claimed in claim 1, wherein: The conductive film connection area is formed on the protection circuit. 10. The method for manufacturing a thin film transistor array substrate as claimed in claim 1, wherein: The upper film is a protective film or the third conductive film. 11. A display device equipped with a thin film transistor array substrate manufactured by the method for manufacturing a thin film transistor array substrate according to any one of claims 1 to 10.

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