CN101409504A - Improved electric charge pump circuit - Google Patents
Improved electric charge pump circuit Download PDFInfo
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- CN101409504A CN101409504A CNA2007101809653A CN200710180965A CN101409504A CN 101409504 A CN101409504 A CN 101409504A CN A2007101809653 A CNA2007101809653 A CN A2007101809653A CN 200710180965 A CN200710180965 A CN 200710180965A CN 101409504 A CN101409504 A CN 101409504A
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- nmos pass
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- charge pump
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Abstract
The invention provides an improved charge pump circuit, comprising: from top to bottom, a second PMOS transistor, a first PMSO transistor, a first NMOS transistor and a second NMOS transistor which are sequentially connected between a power and a grounding reference point; wherein, the connection end of the first PMSO transistor and the first NMOS transistor is an output end; the first PMOS transistor is controlled by a first fixed bias voltage; the second PMOS tube is controlled by a first periodic pulse signal; the first fixed bias voltage and the first periodic pulse signal form a charging section so as to charge a first low-pass filter circuit; the first NMOS transistor is controlled by a second fixed bias voltage; the second NMOS transistor is controlled by a second periodic pulse signal; the second fixed bias voltage and the second periodic pulse signal form a discharging section so as to provide a low-pass filter circuit discharging path; the improved charge pump circuit also comprises a quick level lowering circuit and a quick level raising circuit.
Description
Technical field
The invention relates to a kind of electric charge pump circuit, be meant a kind of electric charge pump circuit that is applied in the phase-locked loop especially.
Background technology
Charge pump is a kind of size of adjustable output voltage, so that it provides the circuit of an output greater than the purpose of input voltage.Therefore, often by extensively in order to the voltage of the various patterns of flash memories to be provided.Although, to boost and also can use the DC-DC transducer to substitute, cost is that the shared area of cost and printed circuit board (PCB) all can be than charge pump height.
Another purposes of electric charge pump circuit (charge pump circuit) is to be used for the phase-locked loop, as shown in Figure 1a, comprises a reference signal generator 1 output one reference voltage Vref to phase frequency comparator 3.One frequency of oscillation divider 6 then is that (signal of frequency of oscillation/N) compares with Vref to phase frequency comparator 3 again, and both phase differences (phasedifference) that export to of controlling electric charge pump circuit 10 in view of the above are 0 in output one.Electric charge pump circuit 10 by a low pass filter 5 with supply voltage-controlled oscillator 4 one voltages exporting a frequency of oscillation, this frequency of oscillation is the frequency divider of feed-in simultaneously 6 and form feedback also.
Fig. 1 b is the circuit of a typical charge pump itself.Electric charge pump circuit 10 is between power vd D and ground, from top to bottom repeatedly meets the 2nd PMOS transistor P2, a PMOS transistor P1, the first nmos pass transistor N1 and the second nmos pass transistor N2.The link of the drain electrode of the one PMOS transistor P1 and the drain electrode of the first nmos pass transistor N1 is drawn an output node OUT.The signal of output node OUT is fed into a low pass filter 5, for example the low pass filter formed of a resistance R and capacitor C.Wherein, a PMOS transistor P1 is controlled by the first bias voltage signal vb1; The first nmos pass transistor N1 is controlled by the second bias voltage signal vb2.
Vb1 provides a fixed-bias transistor circuit that is enough to open a PMOS transistor P1, as long as pulse wave signal UPB when the state of 0 (low state), just can output current to low pass filter 5, again to load, for example similarly is voltage-controlled oscillator.
Relatively, vb2 provides another to be enough to open the fixed-bias transistor circuit of the first nmos pass transistor N1, as long as pulse wave signal DN when the state of 1 (high state), just can extremely be held by the first nmos pass transistor N1, the second nmos pass transistor N2 from OUT end inflow current by low pass filter 5.
The problem of existing charge group pump circuit 10 is the moments that when UPB switches to 1 by 0, and a PMOS transistor P1 can't very fast closing.As shown in Figure 4, the source voltage V of a PMOS transistor P1
SCan slowly discharge and close again.
Similarly, switch to 0 o'clock moment at DN by 1, the first nmos pass transistor N1 can't very fast closing.Because the source voltage V of the first nmos pass transistor N1
SBe very low, it can just not raise at the transient voltage of turning off the second nmos pass transistor N2.
In view of this, a purpose of the present invention is to solve the transient state problem that above-mentioned pulse wave signal switches moment.
Summary of the invention
The invention provides a kind of improved electric charge pump circuit, at least comprise: an electric charge pump circuit, from top to bottom comprise one the 2nd PMOS transistor, the one PMOS transistor, first nmos pass transistor and second nmos pass transistor repeatedly connect in regular turn, wherein, the link of described first nmos pass transistor of a described PMOS transistor AND gate is an output, and a described PMOS transistor is controlled with first fixed-bias transistor circuit, described the 2nd PMOS transistor is by periodically first pulse wave signal control, both form the charging section, so that a low-pass filter circuit is charged, described first nmos pass transistor is controlled with second fixed-bias transistor circuit, and both form the discharge section so that a low-pass filter circuit discharge path to be provided to described second nmos pass transistor by periodicity second pulse wave signal; And per stage of electric charge pump circuit charge or discharge when switching transition effect eliminate circuit, described transition effect is eliminated circuit and is comprised by one and drag down potential circuit fast and draw high wherein one or the two common composition of the group that potential circuit forms fast, the described potential circuit that drags down fast has the 3rd PMOS transistor that a grid is connected with drain electrode, one first current source is connected between transistorized grid of described the 3rd PMOS and the ground end, the transistorized grid of described the 3rd PMOS is connected to the first node of the described PMOS transistor connection of described the 2nd PMOS transistor AND gate of described electric charge pump circuit by one first gate PMOS transistor, when per stage of described electric charge pump circuit is charged switching, the voltage of described first node is dragged down, the described potential circuit of drawing high fast, has the 3rd nmos pass transistor that a grid is connected with drain electrode, one second current source is connected between the drain electrode and power end of described the 3rd nmos pass transistor, the grid of described the 3rd nmos pass transistor is connected to first nmos pass transistor of described electric charge pump circuit and the Section Point that second nmos pass transistor connects by one first gate nmos pass transistor, when per stage of described electric charge pump circuit is discharged switching, the voltage of described Section Point is drawn high.
The invention provides a kind of improved electric charge pump circuit, at least comprise: an electric charge pump circuit, from top to bottom comprise one the 2nd PMOS transistor, the one PMOS transistor, first nmos pass transistor and second nmos pass transistor repeatedly connect in regular turn, wherein, the link of described first nmos pass transistor of a described PMOS transistor AND gate is an output, and a described PMOS transistor is controlled with first fixed-bias transistor circuit, described the 2nd PMOS transistor is by periodically first pulse wave signal control, both form the charging section, so that a low-pass filter circuit is charged, described first nmos pass transistor is controlled with second fixed-bias transistor circuit, and both form the discharge section so that a low-pass filter circuit discharge path to be provided to described second nmos pass transistor by periodicity second pulse wave signal; One drags down potential circuit fast has the first node that is connected to the charging section of described electric charge pump circuit with described electric charge pump circuit equal number and the transistor that repeatedly connects order by one first gate transistor, described first node is the transistorized link of the described PMOS of described the 2nd PMOS transistor AND gate, when per stage of described electric charge pump circuit, charging was switched, the voltage of described first node is dragged down; Reach one and draw high potential circuit fast, has the Section Point that is connected to the discharge section of described electric charge pump circuit with described electric charge pump circuit equal number and the transistor that repeatedly connects order by one second gate transistor, described Section Point is the link of described second nmos pass transistor and described first nmos pass transistor, when per stage of described electric charge pump circuit is discharged switching, the voltage of described Section Point is drawn high.
Transient state time when switching when the present invention has reduced conventional charge group interim charging the in Pu.Transient state time also significantly reduces when switching when equally, the charge pump stage is discharged.Owing to when switching during the charging of charge pump stage, be to take over to the potential circuit that drags down fast of the similar environment of charge pump by another, the transistor P1 of fixing unlatching is closed, can reach balance very soon again.Equally, when switching during owing to the interim discharge of charge pump, be to take over to the potential circuit of drawing high fast of the similar environment of charge pump by another, close fixing the transistor N1 that opens, can reach balance very soon again.
Description of drawings
Fig. 1 a is the circuit box schematic diagram of a typical phase-locked loop.
Fig. 1 b is an existing charge group Pu schematic diagram.
Fig. 2 is a charge pump schematic diagram of the present invention.
Fig. 3 a is for having charge pump now when conjugation rising pulse wave signal switches, the transition effect of PMOS transistor source-grid voltage Vgs.
Fig. 3 B for charge pump of the present invention when conjugation rising pulse wave signal switches, the transition effect of a PMOS source transistor electrode current.
Fig. 4 is the charge pump schematic diagram according to first embodiment of the invention.
Drawing reference numeral
1 reference signal generator, 6 frequency dividers
3 phase frequency comparator, 10 electric charge pump circuits
4 voltage-controlled oscillators 20 drag down potential circuit fast
5 low pass filters 30 are drawn high potential circuit fast
35 first current sources, 36 second current sources
Embodiment
The invention provides a kind of transient state reaction time can significantly reduce charging control signal and discharge control signal and switch the time, and then reduce the aliasing noise (glitchnoise) that the electric current because of charge pump does not match and produced.
According to one embodiment of the invention, improvement electric charge pump circuit 10 of the present invention please refer to circuit diagram shown in Figure 2, comprises: an electric charge pump circuit 10, drags down potential circuit 20 fast, draws high potential circuit 30, gate transistor P3 (the 3rd PMOS transistor) and N3 (the 3rd nmos pass transistor) fast.The first node M1 of electric charge pump circuit 10 is connected to by one the 3rd PMOS transistor P3 and drags down potential circuit 20 fast.The 3rd PMOS transistor P3 is by rising pulse wave signal UP control (to be conjugation anti-phase with signal UPB).And the Section Point M2 of electric charge pump circuit 10 is connected to by the conjugated signal DNB of decline pulse wave signal DN control (it is anti-phase that two signals are conjugation) by one the 3rd nmos pass transistor N3 and drags down potential circuit 30 fast.The 3rd nmos pass transistor N3 is controlled by decline pulse wave signal DNB.
Electric charge pump circuit 10 is between power vd D and ground, from top to bottom repeatedly meets the 2nd PMOS transistor P2, a PMOS transistor P1, the first nmos pass transistor N1 and the second nmos pass transistor N2.The link of the drain electrode of the one PMOS transistor P1 and the drain electrode of the first nmos pass transistor N1 is drawn an output node OUT.The signal of output node OUT is fed into a low pass filter 5.In addition, a PMOS transistor P1 is controlled by the first bias voltage signal vb1; The first nmos pass transistor N1 is controlled by the second bias voltage signal vb2.
According to one embodiment of the invention, the first bias voltage signal vb1 and the second bias voltage signal vb2 are constant values.And the control signal of the 2nd PMOS transistor P2 is one-period property pulse wave UPB (UP is anti-phase with the rising pulse wave signal).The second nmos pass transistor N2 is controlled by the pulse wave signal DN that periodically descends.Basically, when UP=1 (when being high potential) opened the 2nd PMOS transistor P2, decline pulse wave signal DN one fixed on electronegative potential to close the second nmos pass transistor N2.But UP=1 and DN=0 may not be synchronous.Therefore, electric current I 1 will flow into low pass filter 5 to carry out the stage charging by output OUT by the 2nd PMOS transistor P2, a PMOS transistor P1.
When DN=1 (when being high potential) opened the second nmos pass transistor P1, rising pulse wave signal UP one fixed on electronegative potential 0 (UPB=1) to close the 2nd PMOS transistor P2.Therefore, electric current I 2 will be carried out the stage discharge by low pass filter 5, output OUT, the first nmos pass transistor N1, second this paths of nmos pass transistor N2.
Compare with conventional charge group Pu (please refer to Fig. 1 a, Fig. 1 b), the potential circuit 20 that drags down fast of the present invention is to become at 0 o'clock by 1, the residual voltage V of node M 1 in order to solve rising pulse wave signal UP
M1The PMOS transistor P1 that can not very fast making wins closes.If when not dragging down potential circuit 20 fast, will be shown in Fig. 3 a, V
GS, P1The voltage of (tradition) is the discharge of walking unhurriedly.Electric current I when dragging down potential circuit 20 has fast been arranged,
P1(the present invention) will reach the purpose of repid discharge by dragging down potential circuit 20 fast, shown in Fig. 3 b.
For this reason, drag down potential circuit 20 fast and be designed to number of transistors and the framework suitable with electric charge pump circuit 10.Still please refer to Fig. 2, drag down fast potential circuit 20 power vd D and ground between, from top to bottom comprise the 5th PMOS transistor P5, the 4th PMOS transistor P4, the 4th nmos pass transistor N4, the 5th nmos pass transistor N5 and repeatedly connect.When UP=0, dragging down potential circuit 20 fast is not have any effect, because of being isolated by the 3rd PMOS transistor P3.In case UP changeed 0 o'clock by 1, dragging down potential circuit 20 fast will very fast catcher.Promptly as shown in Figure 2, the node M 3 that promptly drags down potential circuit 20 is fast made with electric current and is helped the identical environment of Pu node M 1.Promptly the control signal of the 4th nmos pass transistor N4 and the first nmos pass transistor N1 is identical all is vb2.The 5th nmos pass transistor N5 keeps the opening of awaiting orders at any time.Promptly the control signal of the 5th nmos pass transistor N5 is supply voltage VDD.The 5th PMOS transistor P5 keeps the opening of awaiting orders, i.e. control signal ground connection at any time.In addition, the drain and gate of the 4th PMOS transistor P4 links together, and is unimpeded so that drag down current potential 20 these circuit fast, so that V
M1Voltage can be very fast pass through the 4th PMOS transistor P4, discharge with quick closedown the one PMOS transistor P1 through the 4th nmos pass transistor N4, the 5th nmos pass transistor N5 ground connection.
On the other hand, for solving the transition effect (being that DN=1 becomes 0) in the electric charge pump circuit 10 interim discharge processes, compare with conventional charge group Pu (please refer to Fig. 1 a, Fig. 1 b), the potential circuit 30 of drawing high fast of the present invention is to become at 0 o'clock by 1, the residual voltage V of node M 2 in order to solve decline pulse wave signal DN
M2The problem that the nmos pass transistor N1 that can not very fast making wins closes.That is, drawing high potential circuit 30 fast is with V
M2Very fast the drawing high of current potential.
For this reason, draw high potential circuit 30 fast and also be designed to number of transistors and the framework suitable with electric charge pump circuit 10.Still please refer to Fig. 2, draw high potential circuit 30 fast, from top to bottom comprise the 7th PMOS transistor P7, the 6th PMOS transistor P6, the 6th nmos pass transistor N6, the 7th nmos pass transistor N7 and repeatedly connect between power vd D and ground.When DN=0, drawing high potential circuit 30 fast is not have any effect, because of being isolated by the 3rd nmos pass transistor N3.In case DN changeed 0 o'clock by 1, drawing high potential circuit 30 fast will very fast catcher.Promptly as shown in Figure 2, promptly draw high the manufactured environment identical of the node M 4 of potential circuit 30 fast with electric current group Pu node M 2.Promptly the control signal of the 6th PMOS transistor N6 and a PMOS transistor P1 is identical all is vb1.The 7th PMOS transistor P7 keeps the opening of awaiting orders at any time.Promptly the control signal of the 7th PMOS transistor P7 is a ground connection.The 7th nmos pass transistor N7 keeps the opening of awaiting orders at any time, and promptly control signal meets source VDD.In addition, the drain and gate of the 6th nmos pass transistor N6 links together, and is unimpeded so that draw high current potential 30 these circuit fast, so that V
M2Voltage can be very fast pass through the 7th PMOS transistor P7, through the 6th PMOS transistor P6, the 5th nmos pass transistor N5, the 3rd nmos pass transistor N3 and the current potential V of node M 2
M2Draw high, to reach the purpose of the quick closedown first nmos pass transistor N1.
The foregoing description, the 5th PMOS transistor P5, the 4th nmos pass transistor N4 and the 5th nmos pass transistor N5 that drag down fast in the potential circuit 20 as the circuit that Fig. 2 described open, therefore, it just is equivalent to a current source.The composition of this current source 35 can be done suitable variation, as long as the summation that the effect that produces is equivalent to a PMOS transistor P1, the first nmos pass transistor N1 and the second nmos pass transistor N2 three when being unlocked.
Similarly, the 6th PMOS transistor P6, the 7th PMOS transistor P7 and the 7th nmos pass transistor N7 that draw high fast in the potential circuit 30 open in the state of idle (standby), and therefore, it also is equivalent to a current source 36.The composition of this current source 36 can be done suitable variation, as long as the summation that the effect that produces is equivalent to a PMOS transistor P1, the 2nd PMOS transistor P2 and first nmos pass transistor when being unlocked.
According to above-mentioned idea, we can be varied to the circuit diagram of Fig. 2 as Fig. 4.
Therefore, the present invention has following advantage:
1. transient state time when switching when the present invention has reduced conventional charge group interim charging the in Pu.Transient state time also significantly reduces when switching when equally, the charge pump stage is discharged.
2. when switching during owing to the interim charging of charge pump, be to take over to the potential circuit that drags down fast of the similar environment of charge pump, close, can reach balance very soon again fixing the transistor P1 that opens by another.
3. equally, when switching during owing to the interim discharge of charge pump, be to take over to the potential circuit of drawing high fast of the similar environment of charge pump by another, close fixing the transistor N1 that opens, can reach balance very soon again.
Though the present invention illustrates as above with preferred embodiments, so it is not in order to limit the present invention's spirit and invention entity.Therefore, the modification of being done in not breaking away from spirit of the present invention and scope all should be included in the claim scope.
Claims (8)
1. improved electric charge pump circuit comprises at least:
One electric charge pump circuit, from top to bottom comprise one the 2nd PMOS transistor, the one PMOS transistor, first nmos pass transistor and second nmos pass transistor repeatedly connect in regular turn, wherein, the link of described first nmos pass transistor of a described PMOS transistor AND gate is an output, and a described PMOS transistor is controlled with first fixed-bias transistor circuit, described the 2nd PMOS transistor is by periodically first pulse wave signal control, both form the charging section, so that a low-pass filter circuit is charged, described first nmos pass transistor is controlled with second fixed-bias transistor circuit, and both form the discharge section so that a low-pass filter circuit discharge path to be provided to described second nmos pass transistor by periodicity second pulse wave signal; And
Transition effect was eliminated circuit when the charge or discharge of per stage of one electric charge pump circuit were switched, described transition effect is eliminated circuit and is comprised by one and drag down potential circuit fast and draw high wherein one or the two common composition of the group that potential circuit forms fast, the described potential circuit that drags down fast has the 3rd PMOS transistor that a grid is connected with drain electrode, one first current source is connected between transistorized grid of described the 3rd PMOS and the ground end, the transistorized grid of described the 3rd PMOS is connected to the first node of the described PMOS transistor connection of described the 2nd PMOS transistor AND gate of described electric charge pump circuit by one first gate PMOS transistor, when per stage of described electric charge pump circuit is charged switching, the voltage of described first node is dragged down, the described potential circuit of drawing high fast, has the 3rd nmos pass transistor that a grid is connected with drain electrode, one second current source is connected between the drain electrode and power end of described the 3rd nmos pass transistor, the grid of described the 3rd nmos pass transistor is connected to first nmos pass transistor of described electric charge pump circuit and the Section Point that second nmos pass transistor connects by one first gate nmos pass transistor, when per stage of described electric charge pump circuit is discharged switching, the voltage of described Section Point is drawn high.
2. improved electric charge pump circuit as claimed in claim 1, the first wherein above-mentioned current source are equivalent to the summation that a described PMOS transistor, described first nmos pass transistor and the described second nmos pass transistor three are unlocked.
3. improved electric charge pump circuit as claimed in claim 1, the second wherein above-mentioned current source are equivalent to the summation that described the 2nd PMOS transistor, a described PMOS transistor and the described first nmos pass transistor three are unlocked.
4. improved electric charge pump circuit comprises at least:
One electric charge pump circuit, from top to bottom comprise one the 2nd PMOS transistor, the one PMOS transistor, first nmos pass transistor and second nmos pass transistor repeatedly connect in regular turn, wherein, the link of described first nmos pass transistor of a described PMOS transistor AND gate is an output, and a described PMOS transistor is controlled with first fixed-bias transistor circuit, described the 2nd PMOS transistor is by periodically first pulse wave signal control, both form the charging section, so that a low-pass filter circuit is charged, described first nmos pass transistor is controlled with second fixed-bias transistor circuit, and both form the discharge section so that a low-pass filter circuit discharge path to be provided to described second nmos pass transistor by periodicity second pulse wave signal;
One drags down potential circuit fast has the first node that is connected to the charging section of described electric charge pump circuit with described electric charge pump circuit equal number and the transistor that repeatedly connects order by one first gate transistor, described first node is the transistorized link of the described PMOS of described the 2nd PMOS transistor AND gate, when per stage of described electric charge pump circuit, charging was switched, the voltage of described first node is dragged down; And
One draws high potential circuit fast, has the Section Point that is connected to the discharge section of described electric charge pump circuit with described electric charge pump circuit equal number and the transistor that repeatedly connects order by one second gate transistor, described Section Point is the link of described second nmos pass transistor and described first nmos pass transistor, when per stage of described electric charge pump circuit is discharged switching, the voltage of described Section Point is drawn high.
5. improved electric charge pump circuit as claimed in claim 4, wherein above-mentioned drag down fast potential circuit comprise the 5th PMOS transistor, the 4th PMOS transistor, the 4th nmos pass transistor, and the 5th nmos pass transistor repeatedly connect, described the 4th nmos pass transistor has and the identical control signal of described first nmos pass transistor, opens and the 5th PMOS transistor AND gate the 5th nmos pass transistor is permanent.
6. improved electric charge pump circuit as claimed in claim 4, wherein above-mentioned the 4th PMOS transistor drain that drags down potential circuit fast links to each other with grid, when per stage, charging was switched, the voltage of described first node can be equivalent to described the 4th PMOS transistor drain voltage.
7. improved electric charge pump circuit as claimed in claim 4, wherein above-mentioned draw high fast potential circuit comprise the 7th PMOS transistor, the 6th PMOS transistor, the 6th nmos pass transistor, and the 7th nmos pass transistor repeatedly connect, described the 6th PMOS transistor has and the identical control signal of a described PMOS transistor, opens and the 7th PMOS transistor AND gate the 7th nmos pass transistor is permanent.
8. improved electric charge pump circuit as claimed in claim 4, wherein above-mentioned drain electrode of drawing high the 6th nmos pass transistor of potential circuit fast links to each other with grid, when per stage, discharge was switched, the voltage of described Section Point can be equivalent to the source voltage of described the 6th nmos pass transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2007101809653A CN101409504A (en) | 2007-10-10 | 2007-10-10 | Improved electric charge pump circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2007101809653A CN101409504A (en) | 2007-10-10 | 2007-10-10 | Improved electric charge pump circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101409504A true CN101409504A (en) | 2009-04-15 |
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ID=40572347
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2007101809653A Pending CN101409504A (en) | 2007-10-10 | 2007-10-10 | Improved electric charge pump circuit |
Country Status (1)
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| CN (1) | CN101409504A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106708149A (en) * | 2015-11-18 | 2017-05-24 | 扬智科技股份有限公司 | Buffer circuit and voltage generator using same |
| CN112187040A (en) * | 2019-07-05 | 2021-01-05 | 台达电子国际（新加坡）私人有限公司 | Charging type charge pump with wide output voltage range |
-
2007
- 2007-10-10 CN CNA2007101809653A patent/CN101409504A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106708149A (en) * | 2015-11-18 | 2017-05-24 | 扬智科技股份有限公司 | Buffer circuit and voltage generator using same |
| CN112187040A (en) * | 2019-07-05 | 2021-01-05 | 台达电子国际（新加坡）私人有限公司 | Charging type charge pump with wide output voltage range |
| CN112187040B (en) * | 2019-07-05 | 2023-12-26 | 台达电子国际（新加坡）私人有限公司 | Charge pump with wide output voltage range |
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Open date: 20090415 |