CN101399226B - Method for forming a pattern of a semiconductor device - Google Patents
Method for forming a pattern of a semiconductor device Download PDFInfo
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- CN101399226B CN101399226B CN2008101354934A CN200810135493A CN101399226B CN 101399226 B CN101399226 B CN 101399226B CN 2008101354934 A CN2008101354934 A CN 2008101354934A CN 200810135493 A CN200810135493 A CN 200810135493A CN 101399226 B CN101399226 B CN 101399226B
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- 238000000034 method Methods 0.000 title claims abstract description 48
- 239000004065 semiconductor Substances 0.000 title claims abstract description 46
- 125000006850 spacer group Chemical group 0.000 claims abstract description 36
- 230000002093 peripheral effect Effects 0.000 claims abstract description 31
- 238000000059 patterning Methods 0.000 claims abstract description 13
- 238000005530 etching Methods 0.000 claims description 37
- 239000000758 substrate Substances 0.000 claims description 21
- 230000004888 barrier function Effects 0.000 claims description 16
- 239000012528 membrane Substances 0.000 claims description 8
- 229920002120 photoresistant polymer Polymers 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 description 10
- 230000003667 anti-reflective effect Effects 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 230000002950 deficient Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000005039 memory span Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
- H01L2223/5446—Located in scribe lines
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Photosensitive Polymer And Photoresist Processing (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Abstract
In a method for forming a fine pattern of a semiconductor device, forming a spacer for double patterning of a cell region is performed separate from forming a mask pattern that defines a dummy pattern for a pad of a peripheral circuit region.
Description
Technical field
The present invention relates to form the method for the fine pattern of semiconductor device, more particularly, relate to and prevent from first and second mask process of double exposure operation, to produce the method for defective with the resolution limit that overcomes exposer.
Background technology
Along with semiconductor device diminishes and integrated level uprises, chip area increases along with the increase of memory span proportionally, and still, the area that forms the unit area of pattern of semiconductor device reduces.Owing to need more pattern to guarantee that memory has required capacity in the limited unit area, therefore reduce the critical dimension (CD) of pattern thus make pattern become meticulousr.
Usually use photo-mask process to obtain to have the pattern of less CD.Photo-mask process comprises: apply photoresist on substrate; By using wavelength photoresist to be exposed as the exposed mask that the light source utilization of 365nm, 248nm, 193nm and 153nm has fine pattern; And carry out developing procedure to form the photoresistance pattern that limits fine pattern.
In photo-mask process, shown in equation R=k1 * λ/NA, resolution (R) is decided by the wavelength (λ) and the numerical aperture (NA) of light source.In this equation, k1 is the operation constant with physics limit, thereby can not reduce the value of k1 by conventional method.For the exposer that uses the short wavelength, need a kind ofly the novel photoresist of high response be arranged, thereby be difficult to form the fine pattern of CD less than this short wavelength to the short wavelength.
Therefore, developed a kind of double patterning technology (double patterningtechnology), this double patterning technology uses exposer to make pattern overlapping to obtain fine pattern.
The double patterning operation is included in and forms the first hard mask on the semiconductor substrate.The CD that the first hard mask limits is 3 times of CD of fine pattern.On the first hard mask, form the second hard mask, the second hard mask and the first hard mask are alternately arranged, thereby obtain fine pattern by the first hard mask and the second hard mask.Yet the operation allowance of accurately the arrange first hard mask and the second hard mask reduces, thereby causes the allowance of double patterning operation to reduce.
In order to prevent that allowance from reducing, form the sacrificial oxidation article pattern, and on the sidewall of oxide pattern, form sept, thus can be with sept as the hard mask that limits fine pattern.Though the method for using sept to form fine pattern can increase the operation allowance that forms fine pattern, dummy pattern (dummy pattern) thus also diminish and make dummy pattern produce defective.
As mentioned above, in the conventional method of the fine pattern that forms semiconductor device, because the resolution limit of exposer is difficult to form the fine pattern with little CD.In overcoming the double patterning operation of this limit, form at the mask of carrying out twice that pattern may misalignment in the operation.Though develop the method for using sept to form fine pattern, form in the operation at the hard mask of the sept that forms fine pattern and also define dummy pattern.Therefore, the yield of dummy pattern variation and semiconductor device and reliability reduce.
Summary of the invention
Various embodiment of the present invention relates to the method for using sept to form the fine pattern of semiconductor device.In described method, form the sept that limits fine pattern discretely with the step that forms the mask pattern that limits dummy pattern.The method that described use sept formation limits the hard mask pattern of fine pattern has improved the yield and the reliability of semiconductor device.
According to one embodiment of present invention, a kind of method that forms the fine pattern of semiconductor device comprises: at semiconductor substrate upper limit order unit zone and peripheral circuit region; On described semiconductor substrate, form basic unit; In the basic unit of described unit area, form sacrificial pattern; On the sidewall of described sacrificial pattern, form sept; Remove described sacrificial pattern to form spacer patterns; In the basic unit of described peripheral circuit region, form the mask pattern that limits the peripheral circuit pattern; And use described spacer patterns and photoresistance pattern to the basic unit's patterning in described unit area and the described peripheral circuit region, to obtain unit pattern and peripheral circuit pattern.
Described method also is included in when forming described spacer patterns to go up in scribe lanes (scribelane) and forms alignment keys or cover the key case of marking on a map.
Described mask pattern is defined as embossment or engraving type with dummy pattern.
A kind of method that forms the fine pattern of semiconductor device comprises: form first hard mask layer on semiconductor substrate; On described first hard mask layer, form the etching barrier film; On described etching barrier film, form expendable film; On described expendable film, form second hard mask layer; To described second hard mask layer patternization forming second hard mask pattern, thereby limit fine pattern by spacer regions; Use the described expendable film of the described second hard mask pattern etching to form sacrificial pattern; Remove described second hard mask pattern on the sidewall of described sacrificial pattern, to form sept; Remove described sacrificial pattern to form spacer patterns; Form the photoresistance pattern that limits dummy pattern, described dummy pattern is used for forming connection pad in the exterior lateral area of described spacer patterns; Use described spacer patterns and described photoresistance pattern as described etching barrier film of mask etching and described first hard mask layer; And remove described spacer patterns, described photoresistance pattern and described etching barrier film, to form first hard mask pattern that limits described fine pattern.
Description of drawings
Fig. 1 a to Fig. 1 g is the schematic diagram that illustrates according to the method for the fine pattern of the formation semiconductor device of the embodiment of the invention.
Fig. 2 is the cutaway view that is used to form the operation of alignment keys in the method that is illustrated in according to the formation fine pattern of the embodiment of the invention.
Fig. 3 a and Fig. 3 b are the cutaway views that is used to form the operation of dummy pattern in the method that is illustrated in according to the fine pattern of the formation semiconductor device of the embodiment of the invention.
Fig. 4 a and Fig. 4 b are the cutaway views that is used to form the operation of dummy pattern in the method that is illustrated in according to the fine pattern of the formation semiconductor device of the embodiment of the invention.
Embodiment
Below, the operation that forms flash grid (flash gate) and form dummy pattern in the unit area of semiconductor device in outer peripheral areas is described with reference to Fig. 1 a to 1g.Then, in the outer peripheral areas of semiconductor device, form alignment keys or cover the operation that key is marked (overlay vernier is called " alignment keys " below) with reference to Fig. 2 explanation.And explanation forms alignment keys in the outer peripheral areas of semiconductor device with reference to Fig. 3 a to Fig. 4 b.
Fig. 1 a to Fig. 1 g is the schematic diagram that illustrates according to the method for the fine pattern of the formation semiconductor device of the embodiment of the invention.Fig. 1 a (i) illustrates plane graph to Fig. 1 g (i), and the cutaway view of the line A-A ' intercepting of Fig. 1 a in (ii) (ii) illustrating along Fig. 1 a (i) to Fig. 1 g (i) to Fig. 1 g.
With reference to Fig. 1 a, on semiconductor substrate 100, form first hard mask layer 120.Can between first hard mask layer 120 and semiconductor substrate 100, be provided with such as basic unit's (not shown) such as gate material layers.
On first hard mask layer 120, form etching barrier film 130, on etching barrier film 130, form expendable film 140.On expendable film 140, form second hard mask layer 150.On second hard mask layer 150, form anti-reflective film 160.On anti-reflective film 160, form the first photoresistance pattern 170 that is defined as flash grid (fine pattern) type.The first photoresistance pattern 170 has the line style pattern to form.
Shown in Fig. 1 a (i), the end bent of the first photoresistance pattern 170 becomes " L " shape so that prevent to have the first photoresistance pattern, 170 avalanches of line style pattern.
With reference to Fig. 1 b, use the first photoresistance pattern 170 as the mask etching anti-reflective film 160 and second hard mask layer 150, to form the second hard mask pattern (not shown) that limits line/distance.After removing the first photoresistance pattern 170, use second hard mask pattern as mask etching expendable film 140, to form the sacrificial pattern 145 that limits the flash grid.
When form the etching selectivity layer of spacer material (not shown) different with the etching selectivity of sacrificial pattern 145 on semiconductor substrate 100 after, execution is eat-back operation and is formed first sept 180 with the side-walls in sacrificial pattern 145.The critical dimension of first sept 180 (CD) is the CD of the fine pattern (flash grid) that forms in subsequent handling.
With reference to Fig. 1 c, remove sacrificial pattern 145 by Wet-type etching operation or dry-etching operation.With reference to Fig. 1 d, form the second photoresistance pattern 190, this second photoresistance pattern 190 makes the two ends of the line style pattern that formed by first sept 180 on semiconductor substrate 100 expose.
With reference to Fig. 1 e, remove sept 180 from two ends that the second photoresistance pattern 190 exposes cutting apart first spacer patterns, thereby obtain to limit second spacer patterns 185 of flash grid.Then, remove the second photoresistance pattern 190.
With reference to Fig. 1 f, on the etching barrier film 130 that comprises second spacer patterns 185, form the 3rd photoresistance pattern 200 that limits connection pad (pad).With reference to Fig. 1 f (i), the 3rd photoresistance pattern 200 that limits connection pad is set in the peripheral circuit region of semiconductor substrate 100.Can also on " L " of second spacer patterns 185 shape curved edge part, be provided with and support pattern 185a.
Shown in Fig. 1 f, the pattern that the flash grid in the unit area is limited forms by spacer patterns chemical industry preface.The 3rd photoresistance pattern 200 that the dummy pattern of the connection pad that is used for peripheral circuit region is limited is to form by the single patterning operation of not using sept.Therefore, when using sept to be formed for the dummy pattern of the connection pad in the peripheral circuit region, can prevent dummy pattern because its thickness that approaches avalanche takes place or peels off.
Shown in Fig. 1 g, use second spacer patterns 185 and the 3rd photoresistance pattern 200 as the mask etching etching barrier film 130 and first hard mask layer 120, to form first hard mask pattern 125, the second hard mask pattern 125a and the 3rd hard mask pattern 125b.Specifically, form first hard mask pattern 125 that the flash grid as fine pattern is limited, the second hard mask pattern 125a that the support pattern that is used to prevent avalanche is limited and the 3rd hard mask pattern 125b that limits dummy pattern.The aforementioned mask pattern can comprise organic membrane, inoranic membrane and comprise organic membrane and the deposited picture of inoranic membrane.
Remove second spacer patterns 185 and the 3rd photoresistance pattern 200, and use first hard mask pattern 125, the second hard mask pattern 125a and the 3rd hard mask pattern 125b as mask etching semiconductor substrate 100, to form flash grid (not shown), to support pattern (not shown) and dummy pattern (not shown).
As mentioned above, adopt method of patterning to form flash grid and dummy pattern according to formation semiconductor device of the present invention.Hereinafter, be described in the operation that forms alignment keys in the outer peripheral areas with reference to Fig. 2.
Fig. 2 is the cutaway view that is used to form the operation of alignment keys in the method that is illustrated in according to the formation fine pattern of the embodiment of the invention.Specifically, Fig. 2 illustrates when forming first mask pattern that limits fine pattern on the semiconductor substrate at Fig. 2, is formed for forming in peripheral circuit region first mask pattern 175 of alignment keys.
The spacer patterns 175a (referring to Fig. 3 a and Fig. 3 b) that forms by the side-walls at first mask pattern 175 limits alignment keys.Because the size and the distribution of alignment keys pattern are relatively large, so alignment keys is subjected to the influence of CMP or etching work procedure less relatively.Therefore, can be pre-formed alignment keys 175 from the beginning and limit the first photoresistance pattern 170 in as shown in Figure 1 the unit area.Then, can adopt the operation of method execution graph 1b to Fig. 1 g of the fine pattern of above-mentioned formation unit area.
Fig. 3 a to Fig. 4 b is illustrated in the cutaway view that forms the operation of dummy pattern and alignment keys in the peripheral circuit region.Fig. 3 a to Fig. 4 b is corresponding to the operation that forms " pattern (Fig. 1 e) that is used for the flash grid of unit area " and " dummy pattern (Fig. 1 f) that is used for the connection pad of outer peripheral areas ".
Fig. 3 a and Fig. 3 b are the cutaway views that illustrates according to the dummy pattern of first embodiment of the invention.Fig. 3 a illustrates following operation: promptly, after the operation of execution graph 1a to Fig. 1 e in the unit area, form the dummy pattern 200a that the connection pad in the peripheral circuit region is limited.
With reference to Fig. 3 a, in peripheral circuit region, comprise forming the photoresistance pattern 200a that the dummy pattern that is used for connection pad is limited on the etching barrier film 330 of alignment keys pattern 175a.
With reference to Fig. 3 b, use alignment keys pattern 175a and photoresistance pattern 200a as the mask etching etching barrier film 330 and first hard mask layer 320, to form the first hard mask pattern (not shown).Then, use first hard mask pattern, to form dummy pattern 315 and alignment keys 325 as mask etching semiconductor substrate 300.
Fig. 4 a and Fig. 4 b are the cutaway views that illustrates according to the dummy pattern of second embodiment of the invention.Identical with Fig. 3 a, Fig. 4 a illustrates following operation: promptly, after the operation of execution graph 1a to Fig. 1 e in the unit area, form the dummy pattern 200b that the connection pad in the peripheral circuit region is limited.
With reference to Fig. 4 a, in peripheral circuit region, comprise forming the photoresistance pattern 200b that the dummy pattern 415 that is used for connection pad is limited on the etching barrier film 430 of alignment keys pattern 175a.
With reference to Fig. 4 b, similar to the operation shown in Fig. 3 b, use alignment keys pattern 175a and photoresistance pattern 200b as the mask etching etching barrier film 430 and first hard mask layer 420, to form the first hard mask pattern (not shown).Then, use the first hard mask pattern (not shown), to form dummy pattern 415 and alignment keys 425 as mask etching semiconductor substrate 400.
In the embodiment shown in Fig. 3 a, Fig. 3 b and Fig. 4 a, Fig. 4 b, though it is identical with 425 operation to be used to form alignment keys 325, the photoresistance pattern 200a and the 200b that are used to form dummy pattern 315 and 415 are mutually symmetrical.Use positive resist and negative resist to adopt identical graticule to form photoresistance pattern 200a and 200b.
As mentioned above, in method, carry out being formed for the step of sept of double patterning and the step that forms the mask pattern that the dummy pattern to the connection pad that is used for peripheral circuit region limits are carried out in the unit area respectively according to the fine pattern of the formation semiconductor device of the embodiment of the invention.When the dummy pattern that is used for the connection pad of peripheral circuit region when employing forms sept in the unit area, thereby the dummy pattern variation may not normally form the hard mask pattern that limits dummy pattern.Therefore, this method can increase the operation yield and the reliability of semiconductor device.
The above embodiment of the present invention is exemplary and not restrictive.The various modes that substitute and be equal to all are feasible.The present invention is not restricted to the type of deposition as herein described, etching, polishing and patterning step.The present invention also is not restricted to the semiconductor device of any particular type.For example, the present invention can be used for dynamic random access memory (DRAM) device or nonvolatile semiconductor memory member.Other that content of the present invention is done increases, deletes or revises in the scope that falls into appended claims.
The application requires the priority of korean patent application No.10-2007-0098451 that submitted on September 28th, 2007 and the korean patent application No.10-2008-0060486 that submitted on June 25th, 2008, and the full content of above-mentioned korean patent application is incorporated this paper by reference into.
Claims (17)
1. method that forms the fine pattern of semiconductor device, described method comprises:
Limit the unit area and the peripheral circuit region of semiconductor substrate;
On described semiconductor substrate, form basic unit;
In the basic unit of described unit area, form sacrificial pattern;
On the sidewall of described sacrificial pattern, form sept as follows:
Acquisition comprises the spacer patterns of two adjacent line style spacer patterns connected to one another;
Form the second photoresistance pattern, the described second photoresistance pattern makes the two ends of the line style pattern that formed by described sept on described semiconductor substrate expose; And
Use sept that the described second photoresistance pattern exposes as mask etching to cut apart the spacer patterns of connection;
Remove described sacrificial pattern to form spacer patterns;
In the basic unit of described peripheral circuit region, form the mask pattern that limits the peripheral circuit pattern; And
Use described spacer patterns and photoresistance pattern to the basic unit's patterning in described unit area and the described peripheral circuit region, to obtain unit pattern and peripheral circuit pattern.
2. method according to claim 1 also comprises:
When forming described spacer patterns, on scribe lanes, form alignment keys or cover the key case of marking on a map.
3. method according to claim 1, wherein,
Photoresistance pattern in the described peripheral circuit region is to use positive resist to form.
4. method according to claim 1, wherein,
Photoresistance pattern in the described peripheral circuit region is to use negative resist to form.
5. method according to claim 1, wherein,
At least one end of described sacrificial pattern is crooked at a predetermined angle.
6. method according to claim 1, wherein,
Described mask pattern comprises organic membrane, inoranic membrane and the deposited picture that comprises described organic membrane and described inoranic membrane.
7. method according to claim 1, wherein,
The step that forms described sept comprises:
On described semiconductor substrate, form layer of spacer material; And
Operation is eat-back in execution.
8. method according to claim 1, wherein,
The step that removes described sacrificial pattern is carried out by the Wet-type etching operation.
9. method according to claim 1 also comprises,
In described basic unit, form hard mask layer.
10. method that forms the fine pattern of semiconductor device, described method comprises:
On semiconductor substrate, form first hard mask layer;
On described first hard mask layer, form the etching barrier film;
On described etching barrier film, form expendable film;
On described expendable film, form second hard mask layer;
To described second hard mask layer patternization forming second hard mask pattern, thereby limit fine pattern by spacer regions;
Use the described expendable film of the described second hard mask pattern etching to form sacrificial pattern;
Remove described second hard mask pattern on the sidewall of described sacrificial pattern, to form sept;
Remove described sacrificial pattern to form spacer patterns;
Form the photoresistance pattern that limits dummy pattern, described dummy pattern is used for forming connection pad in the exterior lateral area of described spacer patterns;
Use described spacer patterns and described photoresistance pattern as described etching barrier film of mask etching and described first hard mask layer; And
Remove described spacer patterns, described photoresistance pattern and described etching barrier film, to form first hard mask pattern that limits described fine pattern.
11. method according to claim 10, wherein,
At least one end of described second hard mask pattern is crooked at a predetermined angle.
12. method according to claim 10, wherein,
The step that forms described sept comprises:
On described semiconductor substrate, form layer of spacer material; And
Operation is eat-back in execution.
13. method according to claim 10, wherein,
The step that removes described sacrificial pattern is carried out by the Wet-type etching operation.
14. method according to claim 10, wherein,
The step that forms described spacer patterns comprises:
Acquisition comprises the spacer patterns of two adjacent line style spacer patterns connected to one another;
Form the second photoresistance pattern, the described second photoresistance pattern makes the two ends of the line style pattern that formed by described sept on described semiconductor substrate expose; And
Use sept that the described second photoresistance pattern exposes as mask etching to cut apart the spacer patterns of connection.
15. method according to claim 10 also comprises:
When forming described spacer patterns, on scribe lanes, form alignment keys or cover the key case of marking on a map.
16. method according to claim 10, wherein,
Photoresistance pattern in the described peripheral circuit region is to use positive resist to form.
17. method according to claim 10, wherein,
Photoresistance pattern in the described peripheral circuit region is to use negative resist to form.
Applications Claiming Priority (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020070098451 | 2007-09-28 | ||
| KR10-2007-0098451 | 2007-09-28 | ||
| KR20070098451 | 2007-09-28 | ||
| KR1020080060486A KR101061316B1 (en) | 2007-09-28 | 2008-06-25 | Method of forming fine pattern of semiconductor device |
| KR1020080060486 | 2008-06-25 | ||
| KR10-2008-0060486 | 2008-06-25 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101399226A CN101399226A (en) | 2009-04-01 |
| CN101399226B true CN101399226B (en) | 2010-10-06 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2008101354934A Active CN101399226B (en) | 2007-09-28 | 2008-08-07 | Method for forming a pattern of a semiconductor device |
Country Status (2)
| Country | Link |
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| KR (1) | KR101061316B1 (en) |
| CN (1) | CN101399226B (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101105431B1 (en) | 2010-03-29 | 2012-01-17 | 주식회사 하이닉스반도체 | Method for fabricating fine pattern |
| KR101159954B1 (en) * | 2010-04-15 | 2012-06-25 | 에스케이하이닉스 주식회사 | Method for forming semiconductor device |
| US8895453B2 (en) * | 2013-04-12 | 2014-11-25 | Infineon Technologies Ag | Semiconductor device with an insulation layer having a varying thickness |
| CN104124149B (en) * | 2013-04-28 | 2016-10-05 | 中芯国际集成电路制造(上海)有限公司 | The forming method of semiconductor device |
| KR102552943B1 (en) * | 2016-08-08 | 2023-07-06 | 삼성전자주식회사 | Fabricating method of semiconductor device |
| CN113764260A (en) * | 2020-06-01 | 2021-12-07 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7151040B2 (en) * | 2004-08-31 | 2006-12-19 | Micron Technology, Inc. | Methods for increasing photo alignment margins |
| US7253118B2 (en) * | 2005-03-15 | 2007-08-07 | Micron Technology, Inc. | Pitch reduced patterns relative to photolithography features |
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2008
- 2008-06-25 KR KR1020080060486A patent/KR101061316B1/en active IP Right Grant
- 2008-08-07 CN CN2008101354934A patent/CN101399226B/en active Active
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| Publication number | Publication date |
|---|---|
| CN101399226A (en) | 2009-04-01 |
| KR101061316B1 (en) | 2011-08-31 |
| KR20090032940A (en) | 2009-04-01 |
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