CN101385214A - Method and apparatus for protecting a gate oxide using source/bulk pumping - Google Patents

Abstract

A method and apparatus for providing ESD event protection for a circuit using a source or bulk pump to increase the bulk and/or source potential level during an ESD event. The apparatus comprises a protection circuit that, in response to an ESD event, limits the voltage formed between two terminals of a transistor by adjusting a potential level on the second terminal.

Description

The method and the device of use source/body pump grill-protected oxide

The cross reference of related application

The application requires the benefit of priority of U.S. Provisional Patent Application sequence number of submitting on March 23rd, 2,004 60/555,566 and the sequence number of submitting on September 17th, 2,004 60/610,905, quotes both as a reference at this.

Technical field

Relate generally to of the present invention provides the circuit of electrostatic discharge (ESD) protection, relates more particularly to the method and the device of use source/body pump grill-protected oxide.

Background technology

The protection to ultra-thin gate oxide at ESD stress is the key factor that obtains enough high level ESD hardness in the advanced CMOS technology.When the voltage on being applied to gate oxide becomes too high, gate oxide will suffer catastrophic damage, and promptly it will puncture.Typically, SiO ₂Under the electric field strength of 6～9MV/cm (DC), puncture.In the ESD stress path, pulse duration is the magnitude of 100ns typically, crosses over the remarkable higher voltage of oxide before allowing to be damaged, and the maximum field that just causes puncturing may be about 20MV/cm.Conventional esd protection circuit for example ESD strangulation is worked finely when the protective standard circuit.

When gate oxide approximately is 5nm or when thinner, esd event causes the quantum mechanics tunneling effect, and electronics will flow through oxide and form tunnelling current.This tunnelling current causes undue power dissipation.It is overheated that gate oxide suffers very fast, and irreversibly damage.Can be damaged in the gate oxide zone below: directly following between any of source or drain region between gate electrode and the substrate (body) and/or at grid.In typical two trap CMOS technology (wherein the P trap is with substrate isolation), grid-oxide body takes place comparing with grid-source/drain breakdown under the significantly higher voltage.For example, find that ultra-thin gate oxide has grid-source puncture voltage BVox (G-S) of about 5V.On the other hand, for identity unit, grid-bulk breakdown voltage BVox (G-B) for example occurs on the more high voltage greater than 10V.Therefore, in order to protect ultra-thin gate oxide, the designer mainly concentrates on and limits more crucial grid-source ESD voltage.

Fig. 1 describes to have the curve 100 of example of its instantaneous breakdown characteristic of transistor that thickness is the gate oxide of 2.2nm.To described in the curve 102 that adds gate source voltage, begin excessive tunnelling current as gate current, and be damaged at about 7V at about 6V.Superincumbent is the curve 104 of the I-V characteristic of prior art esd protection strangulation (for example GGNMOS), so-called to form " ESD design window ".The I-V characteristic of esd protection device (curve 104) with the comparative descriptions of the breakdown characteristics (curve 102) of ultra-thin gate oxide cross over strangulation voltage surpass the tunnelling voltage and the puncture voltage of oxide fast.Therefore, the ability of protection device (being strangulation ESD voltage transient) is very limited.Therefore, conventional esd protection device uses together in protection device with the ultra-thin gate oxide device and is not subjected to the grid loss of esd event to have effective effect aspect bad.

Downsizing technology impels oxide thickness to reduce step by step, yet because of some physical restriction to the convergent-divergent protective circuit, the I-V characteristic of strangulation device is not with identical paces reduction.Because oxide thickness continues to reduce also to make puncture voltage to be reduced to more and more lower value, the esd protection device can not be protected oxide effectively by strangulation voltage.As describing among Fig. 1, to handle among the electric current I max at the maximum ESD stress that reduces and (follow the physical constraints of the strangulation of determining by its second breakdown triggering electric current I t2 to form contrast), it is obvious that ineffectivity becomes.Therefore, it is limited using the value of conventional esd protection device together with the ultra-thin gate oxide device.

Therefore, the method and apparatus that ultra-thin gate oxide is not damaged during esd event that needs protection in this area.

Summary of the invention

The present invention is by limiting the method and apparatus of grid-source and/or grid-bulk voltage in response to any of esd event pumping body and/or source.Device comprises in response to esd event and is limited in the protective circuit of the voltage that forms between transistorized two ends by regulating potential level on second end.In one embodiment of the present invention, the signal of telecommunication that is produced by esd event is coupled to the impedance circuit that is connecting transistorized source and/or body from the grid end that experiences incident.Cross over the voltage rising source of impedance circuit generation and/or the potential level of body, thus grid-source and/or grid-bulk voltage that restriction is produced by esd event.

Description of drawings

But so can obtain the mode of the above-mentioned feature of detail knowledge the present invention, the more specifically description of the present invention that summarizes above with reference to some embodiment that illustrates in the accompanying drawings.But, should notice that accompanying drawing only illustrates typical embodiments of the present invention, therefore should not think and limit its scope, because the present invention allows other same effectively embodiments.

The figure of the I-V characteristic curve of the more conventional ESD clamped circuit of Fig. 1 description and the I-V characteristic of ultrathin oxide grid;

Fig. 2 describes the simplified block diagram according to first embodiment of esd protection circuit of the present invention;

Fig. 3 describes the simplified block diagram according to second embodiment of esd protection circuit of the present invention;

First detailed maps of implementing of first embodiment of Fig. 4 depiction 2;

Second detailed maps of implementing of first embodiment of Fig. 5 depiction 2;

First detailed maps of implementing of second embodiment of Fig. 6 depiction 3;

Second detailed maps of implementing of second embodiment of Fig. 7 depiction 3;

Fig. 8 describes the block diagram of the 3rd embodiment of the present invention;

First schematic diagram of implementing of the 3rd embodiment of Fig. 9 depiction 8;

Second schematic diagram of implementing of the 3rd embodiment of Figure 10 depiction 8;

Figure 11 describes the diagrammatic sketch of ESD window expansion provided by the invention;

Figure 12 describes to use the TLP analysis result of the circuit of 10 Ω source resistors;

Figure 13 describes to use the TLP analysis result of the circuit of 25 Ω source resistors;

Figure 14 describes to use the another embodiment of the present invention of complex source impedance; And

Figure 15 is depicted in the another embodiment of the present invention of using isolation resistor in the input path.

Embodiment

Replace focusing on separately the optimization of effective ESD strangulation (quick, low resistance) with restriction grid voltages at nodes, the present invention utilizes new notion: by being increased in adventurous transistorized source electromotive force during the ESD stress condition, reduce to cross over the ESD voltage of adventurous grid-source oxide.Should be noted that same mechanism can be applied to wherein form transistorized semiconductor material body, as long as transistorized body is (NMOS: the isolation P trap in the triple-well technology, PMOS: isolate the N trap) that isolates.The result of rising source or bulk potential can tolerate higher instantaneous gate bias before reaching the oxide breakdown boundary.This provenance biasing technique is expanded the ESD design window effectively and is relaxed the esd protection challenge of ultra-thin gate oxide.

Fig. 2 describes the block diagram according to first embodiment of the circuit 200 of execution of the present invention source pumping.Comprise transistor 202 and 204 at esd event protected circuit 201, for example conventional input signal phase inverter.These transistors can be the transistors of NMOS or PMOS type.Certainly, can follow other circuit arrangement, device or independent transistor to use the present invention together.

Between IN end and Vss, form the first conventional ESD clamped circuit 206 (being also referred to as elementary protective circuit here), and between IN end and Vdd, form the second conventional ESD clamped circuit 208.For example, sort circuit comprises the common transfer United States Patent (USP) 6,768,616 and 6,791 that is incorporated herein by reference, those described in 122.Each transistor 202 and 204 comprises grid 212/210, source 216/214, and leak 220/218.Vdd is coupled to the source 214 of transistor 202 by first source impedance circuit 222.Transistor 202 connects together and is connected to IN end 230 (for example, the pads of integrated circuit) with 204 grid 210/212.Leak 218/220 OUTPUT that also connects together and form circuit 200 and hold 232.The source 216 of transistor 204 is coupled to Vss by second source impedance circuit 224.。Active source pump (ASP) 226 is coupled to source 214 from the grid 210 of transistor 204, and active source pump (ASP) 228 is coupled to source 216 from the grid 212 of transistor 202 similarly.

Fig. 3 describes to form the block diagram of the circuit 300 of second embodiment of the present invention, wherein provides source pumping voltage by each of elementary protective circuit 302 and 304.In other words, the source pump 226 and 228 of Fig. 2 is embedded in ESD clamped circuit 302 and 304.

In any embodiment, during the ESD stress events, by (typically＜100mA) pumping is to inside sources node 214/216, and source impedance circuit 222/224 provides the voltage drop of rising source electromotive force with ESD electric current in a small amount.ESD electric current in a small amount is directed flowing through source impedance Z _s222/224, this causes source bias voltage Vs again.In other words, the total ESD voltage that takes place between pad and ground is divided into two part: V _ESD=V _ASP+ V _SAs a result, reaching the low ESD voltage limit V of direct leap gate oxide (GOX) _Max(approaching instantaneous oxide breakdown) can tolerate higher total instantaneous voltage V before _ESD=V _Max'.In other words, as illustrated visually among Figure 11, expanded effective ESD design window.

During normal running, ASP 226/228 does not activate, and makes Vs～0V, and (almost) the whole voltage drop of crossing over ASP 226/228 is in acceptable low-leakage current.In order to prevent the adverse effect of source impedance when the normal running, design has minimum source impedance that may impedance and is good.But this has a balance with ESD, and the latter benefits from big resistance value.

Source impedance circuit 222/224 can comprise resistance, electric capacity, at least one of inductance or their combination.In a kind of enforcement of the present invention, source impedance 222/224 is Ohmic resistance Rs (being true impedance).The enforcement of describing about Figure 14 comprises complex impedance below.In order to use source resistor bias source during esd event, source resistor R s 223 and 225 need form real passive resistance device element (for example silicide stops source knot diffusion, separates and spread or the polymer resistive device) or active element (for example be in low resistive state during the normal running and be in the series connection MOS transistor of high resistant during esd event) in the paraphase MOS transistor.This transistor for example can provide in the cloudy input stage (for example LVDS) altogether at common grid, and perhaps transistor can be incorporated in the circuit of esd protection purpose, as long as transistorized interpolation does not influence the normal running of circuit 201.

The maximum of the source series resistance 223/225 in the NMOS/PMOS phase inverter 201 can allow resistance R s to depend on concrete IC application and normal running standard.During normal running, source resistor 223/225 is reduced to V with effective grid-source biasing _GS ^Eff=Vin-Rs * I _DSThereby reduce the input stage performance.For example, in the wide NMOS input circuit of the typical case 10 μ m of the MOS performance with about 0.5mA/um, the source resistance of Rs=25 Ω will cause Rs * I _Ds～25 Ω * 5mA=125mV subtracts bias effect, thus cause effective grid-source biasing to reduce be V _GS ^Eff=Vin-125mV.Therefore, the typical low input of Vin＜1.5V during input is used for ultra-thin gate oxide, the interpolation of source resistor 223/225 means that about 10% gate bias reduces.Relevant decreased performance can for example compensate with the transistor width that increases a little.

In this first embodiment of the present invention, can use source " resistor " element, follow two different notions and implement " source pump ".First notion is used and is arranged to elementary protective circuit 206/208 (the instantaneous ESD voltage between strangulation IN and the Vss) dedicated source pump 226/228 in parallel.In this was implemented, pump was triggered to current conduction mode (for worst condition stress) under enough low ESD voltage, thereby owing to crossed over the voltage drop of Rs, rising source electromotive force (Fig. 2).Alternatively, elementary protection strangulation 302/304 can be used to obtain very soon the signal of telecommunication (Fig. 3) that triggered by esd event, with drive source resistor 223/225 and set up the source pump efficiency should.Two kinds of technology all follow NMOS and PMOS transistor circuit to work together.Should be noted that and to distinguish different critical stress situations for different pins that they are expressed as respectively usually for the positive ESD of the IN vs.VSS of NMOS with for the positive ESD of the VDD vs.IN of PMOS.The design of source pump need guarantee for these stress events activation of source bias scheme.

An advantage of the dedicated pump technology of Fig. 2 is, can be independent of the protection strangulation, activates the pump mechanism of the ESD design window of ultra-thin gate oxide.This immediately effect can clear up the triggering problem of the slow response time that relates to the strangulation process in the protection device 206/208 effectively, this problem often causes jeopardizing the instantaneous voltage overshoot of ultra-thin gate oxide.

Fig. 4 describes the schematic diagram of first circuit of implementing 400 of the first embodiment of the invention of pie graph 2.Circuit 400 comprises dedicated source pump circuit 226/228.A kind of enforcement of this dedicated source pump circuit 226/228 is with passive source resistor 223/225 diode in series chain 402/404.For example utilizing, other pump configuration of PMOS detector also is possible.

The number of required series diode 402/404 leaks definite by the operate as normal standard such as the input signal amplitude of oscillation of circuit 400 with input in the pump circuit 226/228.If for example the corresponding Vin=1V of the maximum input voltage of normal work period needs three diodes to leak with enough restriction operate as normal so, allow the voltage drop of each diode 0.33V.As rule of thumb, the maximum of each diode can allow voltage drop approximately to be defined as 0.4 volt.This value causes a maximum number n=Vin/0.4V diode.

Under the ESD stress condition, diode chain provides sufficiently high electric current, up to about Ip～100mA, falls to produce the fundamental voltage of crossing over the source resistor R s223/225 with about 10～50Ohm resistance value.For the ultra-thin gate oxide of the instantaneous grid-source oxide breakdown with about BVox (GS)～5V, the ESD design window increases about Ip * Rs～1 to 5V (up to 100%).Must set up diode width like this, make that diode can be with enough electric current injections source, so that pumping effect to be provided, the ESD voltage drop of diode chain pump is crossed in restriction simultaneously.This voltage drop directly is exposed to sensitive grid-source oxide, therefore must can not surpass instantaneous oxide breakdown value.Should be noted that diode can design quite for a short time and have suitably low series resistance owing to obtain the required relatively little pump electric current of source pumping effect on width.

Second schematic diagram of implementing of the first embodiment of the invention of Fig. 5 depiction 2.Particularly, Fig. 5 describes the common grid NMOS part 500 of negative electricity road design altogether, and it comprises the following nmos pass transistor 502 as source impedance 224 of cooperating with diode chain pump 504.The wherein adventurous gate oxide of the combination increase of pump 504 and transistor 502 is exposed to the source electromotive force of the last nmos pass transistor 204 of input pad 230.This grid altogether the moon altogether are configured in existence in the multiple input pad (for example LVDS), perhaps can be incorporated in the circuit of esd protection purpose, as long as the operate as normal that extra circuit does not hinder circuit 201.

In the above in any of the embodiment of Tao Luning in the situation of Zs=Rs, ASP conducting resistance R _ASPBe used as voltage divider with source resistor R s.This causes the analytic representation of the ESD design margin Vmax ' that increases

Vmax’＝(1+Rs/R _ASP)·Vmax

Suppose to have Rs=R _ASPASP design, can obtain 100% of ESD design window so increases, just Vmax '=2Vmax.

Figure 12 and 13 is depicted in transmission line pulse (TLP) analysis result (for the positive pulse polarity of IN vs.GND) of Fig. 4 circuit structure that comprises source resistor R s=10 Ω (Figure 12) and Rs=25 Ω (Figure 13) in conventional P trap/isolation P trap (DNW).Obviously, for the voltage that is lower than about 3V, there is not the electric current of significant quantity can flow through with Rs diode in series chain.Under higher ESD voltage, diode begins conducting, causes the pumping of source/drain node, thereby causes the V that reduces _GS/ V _GDUnder the electric current that promotes, linear I-V curve form bends to I-V and roll-offs, and this is the feature of polymer resistive device under high current condition.In the situation (Figure 12) of Rs=10 Ω, the ESD design margin upper limit can be increased to about Vmax '=6V, shows as constant leakage current progress lost efficacy up to the polymer resistive device that, and the polymer resistive device lost efficacy to show as to leak down to fall fast with voltage to be increased.Initial leakage current increase before polymer lost efficacy shows that gate oxide damages at first.These results are corresponding at least 50% the increase of the most critical original ESD design margin Vmax=4V (approaching oxide breakdown).To (TR=10ns) and TLP rise time (TR=200ps) confirmatory measurement result at a slow speed fast, therefore guarantee that ASP reacts enough soon for very fast ESD transition such as CDM respectively.Vmax '=8V when Figure 13 discloses for Rs=25 Ω, this is equivalent to 100% of critical ESD design margin Vmax increases.Except conventional P trap NMOS, also studied the structural change that comprises the isolation P trap that connects Rs.Can obtain identical ESD design increases.Should be noted that in two kinds of situations discussing in the above,, consider the very conservative safety margin definition of the Vmax ' that extracts about classes of failures.

Fig. 6 describes first schematic diagram of implementing of the second embodiment of the invention of Fig. 3.In this embodiment, elementary protection device 304 is coupled between input pad 230 and the Vss (for example ground connection), and provides the pump electric current for source resistor 225.In enforcement shown in Figure 6, protective circuit is the diode triggered SCR (DTSCR) that comprises diac 602 and SCR 604.SCR 604 comprises pair of transistor 606 and 608 and the resistor 610 arranged in a usual manner, with the gate voltage strangulation to the level below the puncture voltage of gate oxide.This DTSCR is disclosed in the common transfer United States Patent (USP) 6,768,616 of issue on July 27th, 2004.In case DTSCR 304 is lockable in esd event, the inner electromotive force that produces in the P of SCR 604 trap and N trap.Element (being connected to the diode trigger chain of G2N trap) for G2 triggers can tap into this electromotive force by using scr gate G1.When this electromotive force is applied to the inside sources 214 of adventurous nmos pass transistor 204, obtain significantly reducing of effective grid/source electromotive force.

Second schematic diagram of implementing of the second embodiment of the invention of Fig. 7 depiction 3.In this embodiment, trigger DTSCR 604 by the diode chain 702 that is coupled input pad 230 by G1.In this case, pump signal in source is from " isolation " N trap (being SCRG2).During esd event, half that the electromotive force that produces in the N trap approximately falls corresponding to the total voltage of crossing over SCR.When this voltage is applied to the inside sources 214 of adventurous nmos pass transistor 204, obtain significantly reducing of effective grid/source electromotive force.

Other source pump configurations also are possible.For example, with the source resistor cooperation in the ESD circuit pathways, be elementary protection with nmos type ESD circuit application.This source resistor of NMOS protection provides voltage drop during esd event (Rs * Iesd), this can be applied on the inside sources 214 of MOS input stage, thereby reduces effective gate source voltage.

Fig. 8 describes the block diagram of the 3rd embodiment of the present invention.The universal of this embodiment is to set up the electromotive force increase at inside sources node place owing to flow through the tunnelling current of grid-source oxide during ESD, and does not use any external pump electric current.But the prerequisite of function design is the ESD value (Rs～k Ω) that subject string connection 806/808 can switch to high ohm from low ohm relatively normal operating conditions (Rs～10 Ω).Suitable R s element 806/808 and control circuit 802/804 are necessary.Control circuit 802/804 is surveyed esd event and is forwarded active Rs device 806/808 to high resistance ESD pattern, thereby increases internal source voltage and allow higher ESD gate voltage Vg.

First of third embodiment of the invention shown in Fig. 9 depiction 8 is implemented.The PMOS transistor 902 of normally is with nmos input transistor 204 series connection.The control circuit 802 that comprises series diode chain 904 and resistor 906 is as the esd event detector.Control circuit 802 is coupled between input pad 230 and the Vss.Junction point between diode chain 904 and the resistor 906 is coupled to the grid of transistor 902, makes during the ESD stress condition control circuit 802 de excitations PMOS transistor 902 of living.Internal source bias (corresponding to the increase of ESD design window) is followed PMOS transistor gate voltage: Vs～Vg basically ⁺Vth (PMOS).But because normal work period is crossed over the transistorized Vth voltage drop of PMOS, this technology is only applicable to specific analog circuit.

Second of the third embodiment of the invention of circuit 1000 presentation graphs 8 of Figure 10 is implemented.Circuit 1000 utilizes NMOS serial transistor 1002 (providing usually) to replace PMOS transistor 902.This circuit 1000 does not show this shortcoming, therefore generally is suitable for.In normal working conditions, diode string 904 non-conducting electric currents.Therefore, the grid of transistor 1004 are low, and not conducting of transistor.Resistor 1006 is with V _DDBe coupled transistor 1004.Because transistor 1004 not conductings, the grid of transistor 1002 are high, and this makes transistor 1002 be in low ohm state, just by low-ohmic path source 214 is coupled Vss.

In case esd event takes place, the voltage at input node 230 places will impel the 904 beginning conductings of diode string, thereby impel current flows through resistor 906.Cross over the voltage of resistor 906 and move the grid of transistor 1004 to high state, this activating transistor 1004.When transistor 1004 conductings, it moves the grid of transistor 1002 to low state.Transistor 1002 switches to high ohmic state, the electromotive force on this rising source 214.

In the situation of isolating P trap technology (triple-well or the silicon-on-insulator (SOI) that for example have dark N trap), above-mentioned constructed can being used for that provides arrived high potential with the body pumping during ESD stress.Therefore, effectively grid-bulk breakdown voltage can follow grid-source puncture voltage to increase simultaneously.If trend BVox (GB) is not followed in the oxide breakdown behavior〉during BVox (GS), this advantageous particularly.In order to carry out the body pumping, impedance circuit is coupled between transistorized body and the ground, and pump circuit is coupled between pad and the impedance.By being diverted in the impedance, setting up the electromotive force of crossing over impedance, thereby reduce the grid-bulk voltage that when not using the body impedance circuit, produces by esd event owing to the signal of telecommunication from pad of esd event.Impedance circuit can be the combination of one or more resistors, capacitor or inductor.Can use the body pump, and not have the source pump; But in combination, use them at last.

In any of previous embodiments, source impedance circuit 222/224 can be a complex impedance.Figure 14 describes to have the block diagram with the circuit 1400 of the source capacitor Cs1402 of source resistor R s223 parallel connection.The purpose of capacitor Cs is that the RF noise that resistor is introduced naturally is diverted in the ground.This noise source can increase the noise figure of circuit, and reduces the performance that low noise RF uses (for example LNA).

For typical ESD frequency in manikin (HBM) and quick Charged Device Model (CDM) the stress situation,, thereby cause impedance 1/ (ω for Cs=2.5pF _ESDCs) example calculation:

HBM (duration T～100ns): Zs～8k Ω

CDM (duration T～1ns): Zs～80 Ω

Even during quick CDM stress frequency, shunt capacitor keeps sufficiently high impedance, make and to gather by assurance function ASP voltage.

Use the another embodiment of complex impedance Zs can utilize inductor, it exists in the RF circuit of monolithic coupling purpose sometimes.

The another embodiment of the present invention that is described as the circuit 1500 among Figure 15 is followed the ASP circuit engineering of Fig. 2 the pi type strangulation notion combination of using the isolation resistor 1502 between pad 230 (elementary protective circuit 206/208) and secondary protection device (ASP 226/228).Here, the ASP technology is also as secondary clamp.The extra voltage general who has surrendered who crosses over Riso 1502 further relaxes the ESD design window.

Though the aforementioned embodiment of the present invention that relate to are to make other and Geng Duo embodiment of the present invention, and do not deviate from its base region, and its scope are determined by following claim.

Claims (26)

1. One kind be used to protect have at least the first end, the transistorized Electrostatic Discharge protective circuit of second end and the 3rd end, comprising:

   Protective circuit is coupled to second end from first end, by the potential level of regulating second end in response to the esd event that takes place on first end, limits the voltage between first end and second end.
2. 2. according to the esd protection circuit of claim 1, wherein protective circuit comprises:

   Pump circuit;

   Impedance circuit is coupled to first electromotive force from second end, and wherein in response to the esd event that takes place on first end, described pump circuit is applied to the signal of telecommunication on the impedance circuit.
3. 3. according to the esd protection circuit of claim 1, also comprise:

   Be coupled to the elementary protective circuit of first electromotive force from transistorized first end.
4. 4. according to the esd protection circuit of claim 2, wherein impedance circuit comprise resistance, electric capacity and inductance one of at least.
5. 5. according to the esd protection circuit of claim 2, wherein impedance circuit comprises one of at least parallel resistor device with capacitor and inductor.
6. 6. according to the esd protection circuit of claim 2, wherein impedance circuit comprises at least one active device.
7. 7. according to the esd protection circuit of claim 2, wherein pump circuit comprises a plurality of series diodes.
8. 8. according to the esd protection circuit of claim 2, wherein pump circuit is diode triggered SCR.
9. 9. according to the esd protection circuit of claim 2, wherein impedance circuit comprises the variable impedance element with controllable impedance value.
10. 10. according to the esd protection circuit of claim 2, also comprise the isolation resistor that is coupled between input and transistorized first end.
11. 11. according to the esd protection circuit of claim 1, wherein first end is a grid, second end is a source electrode, and the 3rd end is drain electrode.
12. 12. according to the esd protection circuit of claim 1, wherein second end is transistorized body.
13. 13. one kind be used to protect comprise have first end at least, the first transistor of second end and the 3rd end and the Electrostatic Discharge protective circuit of transistor circuit that has the transistor seconds of first end, second end and the 3rd end at least; wherein the 3rd end of the first transistor is coupled to the 3rd end of transistor seconds; and first end of the first transistor is coupled to first end of transistor seconds, comprising:

    First protective circuit, be coupled to second end of the first transistor from first end of the first transistor, by the potential level of regulating second end of the first transistor in response to the esd event that on first end of the first transistor, takes place, first end of restriction the first transistor and the voltage between second end; And

    Second protective circuit; be coupled to second end of transistor seconds from first end of transistor seconds; by the potential level of regulating second end of transistor seconds in response to the esd event that on first end of transistor seconds, takes place, first end of restriction transistor seconds and the voltage between second end.
14. 14. according to the ESD circuit of claim 13, wherein first and second transistors be NMOS or PMOS one of at least.
15. 15. according to the esd protection circuit of claim 13, wherein first protective circuit comprises:

    First pump circuit;

    First impedance circuit is coupled to first electromotive force from second end of the first transistor, and wherein in response to esd event, described first pump circuit is applied to first impedance circuit with the signal of telecommunication;

    Wherein second protective circuit comprises:

    Second pump circuit; And

    Second impedance circuit is coupled to second electromotive force from second end of transistor seconds, and wherein in response to esd event, described second pump circuit is applied to second impedance circuit with the signal of telecommunication.
16. 16. the esd protection circuit according to claim 13 also comprises:

    The first elementary protective circuit is coupled to first electromotive force from first end of the first transistor; And

    The second elementary protective circuit is coupled to second electromotive force from first end of transistor seconds.
17. 17. according to the esd protection circuit of claim 15, wherein first and second impedance circuits each comprise resistance, electric capacity and inductance one of at least.
18. 18. according to the esd protection circuit of claim 15, wherein first and second impedance circuits each comprise one of at least parallel resistor device with capacitor and inductor.
19. 19. according to the esd protection circuit of claim 15, wherein first and second impedance circuits comprises one of at least active device.
20. 20. according to the esd protection circuit of claim 15, wherein first and second pump circuits each comprise a plurality of diode in series.
21. 21. according to the esd protection circuit of claim 15, wherein first and second pump circuits comprise diode triggered SCR.
22. 22. according to the esd protection circuit of claim 15, wherein first and second impedance circuits each comprise variable impedance element with controllable impedance value.
23. 23., also comprise the isolation resistor that is coupled between the input and first and second transistorized first ends according to the esd protection circuit of claim 15.
24. 24. according to the esd protection circuit of claim 13, wherein both first ends of first and second transistors are grids, first and second transistors both second end be source electrode, and both the 3rd ends of first and second transistors be the drain electrode.
25. 25. the method at the esd event protective circuit comprises:

    Activate pump in response to the esd event that on transistorized first end, takes place;

    The signal of telecommunication of self-pumping is applied in the impedance in the future, to increase the potential level on transistorized second end.
26. 26. according to the method for claim 25, wherein first end is transistorized grid, and second end be transistorized source electrode or body one of at least.

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