CN101361109A

CN101361109A - Display device, active matrix substrate, liquid crystald display device and television receiver

Info

Publication number: CN101361109A
Application number: CNA200680051399XA
Authority: CN
Inventors: 内田岁久; 津幡俊英
Original assignee: Sharp Corp
Current assignee: Sharp Corp
Priority date: 2006-02-06
Filing date: 2006-11-30
Publication date: 2009-02-04

Abstract

In a display device, pixels are arranged in matrix, and a first luminance area (high luminance area (47a)) and a second luminance area (low luminance area (47b)) which surrounds the first luminance area and has a luminance lower than that of the first luminance area can be formed in each pixel. The display device which can clearly display an image having a high spatial frequency and an active matrix substrate to be used for the display device are provided.

Description

Display device, active matrix substrate, liquid crystal display device, and television receiver

Technical Field

The present invention relates to a display device such as a liquid crystal display device and an active matrix substrate used for the display device.

Background

Fig. 36 shows a structure of an active matrix substrate used in a conventional liquid crystal display device. As shown in fig. 36, the active matrix substrate 700 includes: a plurality of scanning signal lines 716 and a plurality of data signal lines 715 arranged to intersect each other, TFTs 712(Thin Film transistors) formed near the intersections of the signal lines 715 and 716, and pixel electrodes 717. The scanning signal line 716 also serves as a gate electrode of the TFT712, a source 719 of the TFT712 is connected to the data signal line 715, and a drain 708 of the TFT712 is connected to the pixel electrode 717 via a drain lead electrode 707. A hole is provided in the insulating film disposed between the drain extraction electrode 707 and the pixel electrode 717, thereby forming a contact hole 710 connecting the drain extraction electrode 707 and the pixel electrode 717. The pixel electrode 717 is a transparent electrode such as ITO, and transmits light (light from a backlight) incident from below the active matrix substrate.

In the active matrix substrate 700, when a scanning signal (gate-on voltage) is transmitted to the scanning signal line 716, the TFT712 is turned on (the source electrode 719 and the drain electrode 708 are in an on state), and a data signal (signal voltage) transmitted to the data signal line 715 in this state is written into the pixel electrode 717 through the source electrode 719, the drain electrode 708, and the drain lead electrode 707. The storage capacitor (Cs) line 718 has a function of preventing spontaneous discharge of the liquid crystal layer during the period when the TFT712 is off.

In the active matrix substrate 700, the entire pixel electrode 717 in each pixel is equipotential. That is, when the active matrix substrate 700 is used in a liquid crystal display device, each portion of one pixel is displayed with substantially uniform luminance.

Patent document 1 discloses a configuration in which each pixel is divided into two sub-pixels, one of the sub-pixels is a high-luminance clear display pixel and the other is a low-luminance dark display pixel, in order to suppress the dependency of the γ characteristic on the viewing angle.

Patent document 1: japanese patent application laid-open No. 2004-62146, published as: 2/26/2004.

Patent document 2: japanese patent application laid-open No. 2004-78157, published as: 3/11/2004.

Disclosure of Invention

However, when the luminance in each pixel is uniformly displayed, a problem occurs in that a video having a high spatial frequency is blurred as shown in fig. 21 (b). Further, even if the structure disclosed in patent document 1 is configured to make the luminances of the sub-pixels arranged above and below different from each other, it is not possible to sufficiently improve the display blur of a video image having a high spatial frequency.

The present invention has been made in view of the above problems, and an object thereof is to provide a display device capable of clearly displaying an image having a high spatial frequency, and an active matrix substrate used for the display device.

The display device of the present invention is characterized by having a plurality of pixels; in each pixel, a 1 st luminance region (high luminance region) and a 2 nd luminance region (low luminance region) can be formed, the 2 nd luminance region surrounding the 1 st luminance region and having a luminance lower than that of the 1 st luminance region. That is, in each pixel of the display device, a 1 st luminance region and a 2 nd luminance region surrounding the 1 st luminance region are provided, and luminance of the 1 st luminance region higher than the surrounding thereof and luminance of the 2 nd luminance region lower than the 1 st luminance region can be controlled.

For example, as long as the display device of the simultaneous additive color mixing method of 3 primary colors (R, G, B), 1 pixel may be provided for each of the 3 primary colors. In this case, 3 pixels corresponding to 3 primary colors may be arranged in a stripe shape, a mosaic shape, or a triangular shape.

As described above, since the high-luminance region and the low-luminance region surrounding the high-luminance region are formed in each pixel of the display device, the entire or most of the total luminance of the entire pixels is provided by the high-luminance region (light emission is concentrated in the center of the pixel), and halftone display can be performed. This improves the transmission characteristics in a high spatial frequency region, and clearly displays a video having a high spatial frequency.

The present display device may be configured such that each pixel includes a 1 st switching element and a 2 nd switching element, a 1 st sub-pixel electrode connected to the 1 st switching element, and a 2 nd sub-pixel electrode connected to the 2 nd switching element and surrounding the 1 st sub-pixel electrode.

In the display device, it is preferable that the 1 st luminance region and the 2 nd luminance region are both in a shape having the same point as the center of gravity. According to the above configuration, it is possible to accurately reproduce the position information corresponding to the video signal and obtain a natural video display without a jaggy feeling.

In the present display device, it is preferable that a lowest luminance region is formed between the 1 st luminance region and the 2 nd luminance region. By forming the lowest luminance region (for example, by blocking the outer edge of the high luminance region), it is possible to prevent a decrease in contrast caused by light leakage. Alternatively, the 1 st luminance region (high luminance region) and the 2 nd luminance region (low luminance region) may be adjacent to each other without providing the lowest luminance region.

In the display device including the color filter substrate and the active matrix substrate, the minimum luminance region may be formed using at least one of a black matrix provided on the color filter substrate and a light-shielding body provided on the active matrix substrate. This eliminates the need for a separate member for preventing light leakage (from the vicinity of the outer edge of the high-luminance region), and thus simplifies the manufacturing process and reduces the cost.

In the present display device, the 1 st switching element and the 2 nd switching element may be connected to the same data signal line. In addition, the 1 st switching element and the 2 nd switching element may be connected to the same scanning signal line. In the above case, for example, a 1 st storage capacitor line forming a capacitance with the 1 st sub-pixel electrode and a 2 nd storage capacitor line forming a capacitance with the 2 nd sub-pixel electrode are provided, and the potential of the 1 st storage capacitor line and the potential of the 2 nd storage capacitor line can be controlled separately. Specifically, signal voltages having opposite phases are applied to the storage capacitor lines. This makes it possible to easily control the effective voltages of the 1 st sub-pixel electrode and the 2 nd sub-pixel electrode, and to easily form a high-luminance region and a low-luminance region. In the above configuration, the potential may be controlled so that a phase difference between a potential waveform of the 1 st storage capacitor line and a potential waveform of the 2 nd storage capacitor line is 180 degrees. Further, the 1 st storage capacitor line and the 2 nd storage capacitor line may be potential-controlled so that the potential rises or falls after the 1 st switching element and the 2 nd switching element are turned off, and the state may be maintained until the switching elements are turned off in the next frame.

That is, the potential control is performed so that the potential of the 1 st storage capacitor line is increased after the respective switching elements are turned off and maintained in the state until the respective switching elements are turned off in the next frame, and the potential control is performed so that the potential of the 2 nd storage capacitor line is decreased after the respective switching elements are turned off and maintained in the state until the respective switching elements are turned off in the next frame; alternatively, the 1 st storage capacitor line is potential-controlled so that the potential of the 1 st storage capacitor line decreases after the respective switching elements are turned off and remains in that state until the respective switching elements are turned off in the next frame, and the 2 nd storage capacitor line is potential-controlled so that the potential of the 2 nd storage capacitor line increases after the respective switching elements are turned off and remains in that state until the respective switching elements are turned off in the next frame. In this case, the potential of the 1 st storage capacitor line may rise in synchronization with the potential of the 2 nd storage capacitor line, or the potential of the 1 st storage capacitor line may fall in synchronization with the potential of the 2 nd storage capacitor line. Further, it is also possible to have a configuration in which the rise in potential of the 1 st storage capacitor line and the fall in potential of the 2 nd storage capacitor line are shifted by one horizontal period, or the fall in potential of the 1 st storage capacitor line and the rise in potential of the 2 nd storage capacitor line are shifted by one horizontal period.

In the present display device, the 1 st switching element and the 2 nd switching element may be connected to the 1 st scanning signal line and the 2 nd scanning signal line, respectively. In this case, the on pulse supplied to the 1 st scanning signal line and the on pulse supplied to the 2 nd scanning signal line can be made not to coincide in time. Further, the on pulse supplied to the 1 st scanning signal line and the on pulse supplied to the 2 nd scanning signal line may be partially overlapped in time, and the end timings of the two on pulses may be different from each other.

For example, the start timing of the on pulse supplied to the 1 st scanning signal line and the start timing of the on pulse supplied to the 2 nd scanning signal line are synchronized, and the end timing of the on pulse supplied to the 1 st scanning signal line is earlier. Further, the potential supplied to the data signal line changes in synchronization with or after the end of the preceding end of the previously ended on pulse. In this way, the potential to be written is input again in a state where a certain potential is supplied to the 2 nd sub-pixel electrode, and therefore, the 2 nd sub-pixel electrode can be charged well. Wherein the 2 nd sub-pixel electrode is connected to a 2 nd switching element controlled by a 2 nd scanning signal line. In particular, it is particularly effective in the case where the polarity of the signal potential supplied to the data signal line is inverted every horizontal period (waveform distortion of the signal potential is large) as in the dot inversion driving or the H-line inversion driving, and in the case where the area of the 2 nd sub-pixel electrode is large (charging time is long). Further, since the period of the on pulse is long, the drive frequency of the scanning signal can be suppressed.

In the above configuration, the polarity of the potential supplied to the same data signal line may be inverted every horizontal period.

In the present display device, the 1 st switching element and the 2 nd switching element may be connected to the 1 st data signal line and the 2 nd data signal line, which are independent of each other. In this case, the 1 st luminance region and the 2 nd luminance region described above are formed by supplying different signal potentials to the 1 st data signal line and the 2 nd data signal line.

The active matrix substrate is characterized by comprising a plurality of pixel regions; in each pixel region, a 1 st switching element, a 2 nd switching element, a 1 st sub-pixel electrode connected to the 1 st switching element, and a 2 nd sub-pixel electrode connected to the 2 nd switching element and surrounding the 1 st sub-pixel electrode are provided. That is, the entire or most of the total luminance of the entire pixel is provided by the high luminance region (light emission is concentrated in the center of the pixel), and halftone display is possible. Thus, the display device having the active matrix substrate can significantly improve the transmission characteristics in the high spatial frequency region, and clearly display a video image with a high spatial frequency.

The present active matrix substrate may be configured such that the 1 st switching element and the 2 nd switching element are connected to the same scanning signal line. Alternatively, the 1 st switching element and the 2 nd switching element may be connected to the 1 st scanning signal line and the 2 nd scanning signal line, respectively, which are independent of each other.

In the active matrix substrate, one data signal line may be disposed in each pixel region, the data signal line may be connected to the 1 st switching element and the 2 nd switching element, and a 1 st storage capacitor line and a 2 nd storage capacitor line may be provided, the 1 st storage capacitor line and the 1 st sub-pixel electrode forming a capacitor, and the 2 nd storage capacitor line and the 2 nd sub-pixel electrode forming a capacitor.

The active matrix substrate may be configured such that a 1 st data signal line and a 2 nd data signal line, which are independent of each other, are disposed in each pixel region, the 1 st data signal line being connected to the 1 st switching element, and the 2 nd data signal line being connected to the 2 nd switching element.

The present active matrix substrate may be configured such that a light-shielding body is formed so as to overlap with a boundary portion between the 1 st sub-pixel electrode and the 2 nd sub-pixel electrode. This makes it possible to shield the boundary between the 1 st sub-pixel electrode and the 2 nd sub-pixel electrode from light, and therefore, in the display device having the active substrate of the present invention, it is possible to avoid a problem of a decrease in contrast caused by light leakage from the vicinity of the boundary between the 1 st sub-pixel electrode and the 2 nd sub-pixel electrode (gap region). Further, since the light-shielding body is provided on the active matrix substrate itself, there is no problem that the light-shielding effect is lowered due to misalignment when the substrates are bonded, as in the case where the light-shielding body is provided on the color filter substrate. In addition, a part of the wiring drawn from the 1 st sub-pixel electrode or the 2 nd sub-pixel electrode may overlap a boundary portion between the 1 st sub-pixel electrode and the 2 nd sub-pixel electrode. A part of the scanning signal line may overlap a boundary portion between the 1 st sub-pixel electrode and the 2 nd sub-pixel electrode. In this case, the scanning signal line may be surrounded in a frame shape at an intermediate portion of the pixel and may overlap the boundary portion. In addition, a structure may be adopted in which a part of the 1 st storage capacitor line overlaps a boundary portion between the 1 st sub-pixel electrode and the 2 nd sub-pixel electrode. In this case, the 1 st storage capacitor line may be surrounded in a frame shape in the middle portion of the pixel and may overlap the boundary portion.

In addition, the display device of the present invention is characterized by having the active matrix substrate.

The liquid crystal display device of the present invention includes the active matrix substrate and a backlight that emits light of a plurality of colors in a time-division manner, and performs field sequential display. In the above configuration, for example, 3 colors of 3 primary colors (R, G, B) are continuously displayed in 1 pixel (originally, only 1 color is displayed at a certain time). According to the above configuration, positional displacement of color information can be eliminated, and therefore display quality can be improved. In addition, since no color filter is required, the cost can be reduced.

A television receiver according to the present invention includes the display device and a tuner unit for receiving television broadcasts.

As described above, according to the display device, a video having a high spatial frequency can be clearly displayed. When the active matrix substrate is used in a display device, a high-luminance region and a low-luminance region surrounding the high-luminance region can be formed in each pixel corresponding to each pixel region, and a video having a high spatial frequency can be clearly displayed.

Drawings

Fig. 1 is a perspective plan view showing the structure of an active matrix substrate according to the present embodiment.

Fig. 2 is an equivalent circuit diagram showing the active matrix substrate.

Fig. 3 is an equivalent circuit diagram showing a liquid crystal display device using the active matrix substrate.

Fig. 4 is a perspective plan view showing an example of the structure of the active matrix substrate.

Fig. 5 is a perspective plan view showing an example of the structure of the active matrix substrate.

Fig. 6 is an equivalent circuit diagram showing the active matrix substrate.

Fig. 7 is an equivalent circuit diagram showing the active matrix substrate.

Fig. 8 is a perspective plan view showing an example of the structure of the active matrix substrate.

Fig. 9 is a perspective plan view showing an example of the structure of the active matrix substrate.

Fig. 10 is a perspective plan view showing an example of the structure of the active matrix substrate.

Fig. 11 is a perspective plan view showing an example of the structure of the active matrix substrate.

Fig. 12 is an equivalent circuit diagram showing the active matrix substrate.

Fig. 13 is a timing chart showing a driving method of the active matrix substrate.

Fig. 14 is a schematic diagram illustrating the configuration of a video signal.

Fig. 15(a) is a schematic diagram illustrating the arrangement of the luminance regions of the active matrix substrate.

Fig. 15(b) is a reference diagram for explaining fig. 15 (a).

Fig. 16 is a block diagram showing a configuration of the liquid crystal display device of the present embodiment.

Fig. 17(a) is a schematic diagram illustrating a pixel structure in a field timing manner.

Fig. 17(b) is a schematic diagram illustrating a pixel structure in the field timing mode.

Fig. 18 is a schematic diagram illustrating a driving method in a field timing manner.

Fig. 19(a) is a schematic diagram illustrating an advantage of the field timing scheme.

Fig. 19(b) is a schematic diagram illustrating an advantage of the field timing scheme.

Fig. 20 is a block diagram showing a structure of a field sequential liquid crystal display device.

Fig. 21(a) is a schematic diagram showing a case where the spatial frequency characteristic is low.

Fig. 21(b) is a schematic diagram showing a case where the spatial frequency characteristic is high.

Fig. 22(a) is a schematic diagram showing a display device having a small lighting area.

Fig. 22(b) is a schematic diagram showing a display device having a large lighting area.

Fig. 23 is a graph illustrating transmission characteristics.

Fig. 24 is a block diagram showing a configuration of a television receiver according to the present embodiment.

Fig. 25 is a perspective view showing a configuration of a television receiver according to the present embodiment.

Fig. 26 is a graph showing an example of luminance distribution of the present display device.

Fig. 27 is a graph showing an example of luminance distribution of the present display device.

Fig. 28 is a perspective plan view showing an example of the structure of the active matrix substrate.

Fig. 29 is a perspective plan view showing an example of the structure of the active matrix substrate.

Fig. 30 is an equivalent circuit diagram of the active matrix substrate shown in fig. 29.

Fig. 31 is a timing chart showing another driving method of the active matrix substrate.

Fig. 32 is a timing chart showing another driving method of the active matrix substrate.

Fig. 33 is a timing chart showing another driving method of the active matrix substrate.

Fig. 34 is a sectional view showing the structure of the liquid crystal panel of the present embodiment.

Fig. 35 is a timing chart showing another driving method of the active matrix substrate.

Fig. 36 is a plan view showing a structure of a conventional active matrix substrate.

(description of the drawing reference numerals)

5 pixel region

12a、12b TFT

15 data signal line

16 scanning signal line

17a sub-pixel electrode of sub-1 st

17b sub-pixel electrode of No. 2

11a, 11b contact hole

20 st 1 holding capacitance wiring

21 nd 2 nd holding capacitance wiring

Detailed Description

An embodiment of the present invention will be described below with reference to fig. 1 to 35.

Fig. 1 is a perspective plan view showing the structure of an active matrix substrate according to the present embodiment. As shown in fig. 1, the active matrix substrate 10 includes: pixel regions 5 arranged in a matrix, scanning signal lines 16 (in the column direction, the left-right direction in the figure) and data signal lines 15 (in the row direction, the up-down direction in the figure) orthogonal to each other, a 1 st storage capacitor line 20, and a 2 nd storage capacitor line 21.

In the pixel region 5, a 1 st TFT (thin film transistor) 12a, a 2 nd TFT12b, a 1 st sub-pixel electrode 17a, and a 2 nd sub-pixel electrode 17b are formed.

The 2 nd sub-pixel electrode 17b has a shape in which a part of a rectangle is hollowed out, and has an outer frame 17x having a large rectangle and an inner frame (outer edge of the hollowed-out part) 17y having a small rectangle. A1 st sub-pixel electrode 17a having a rectangular shape is provided inside the inner frame 17 y. That is, the active matrix substrate has a structure in which the 2 nd sub-pixel electrode 17b surrounds the 1 st sub-pixel electrode 17a having a rectangular shape.

A gap region 26 is formed between the outer frame 17z of the 1 st sub-pixel electrode 17a and the inner frame 17y of the 2 nd sub-pixel electrode; the 1 st storage capacitor line 20 is surrounded in a frame shape, and overlaps the gap region 26, a region in the vicinity of the outer frame of the 1 st sub-pixel electrode 17a, and a region in the vicinity of the inner frame of the 2 nd sub-pixel electrode 17 b. Further, a storage capacitor upper electrode 30a is provided so as to overlap the 1 st storage capacitor line 20 and the 1 st sub-pixel electrode 17a, and the storage capacitor upper electrode 30a is connected to the 1 st sub-pixel electrode 17a through a contact hole 11 a. In addition, the lower end portion (one edge in the row direction) of the 2 nd sub-pixel electrode 17b overlaps the scanning signal line 16 in the column direction (left-right direction in the figure). In the above configuration, the frame-shaped black display region (lowest luminance region) is formed between the high luminance region 47a (1 st luminance region) and the low luminance region 47b (2 nd luminance region) by the 1 st storage capacitor line 20.

The 1 st TFT12a and the 2 nd TFT12b are formed near the intersection of the signal lines (15, 16), and the source 9a of the 1 st TFT12a and the source 9b of the 2 nd TFT12b are both connected to the data signal line 15. The drain 8a of the 1 st TFT12a is connected to the storage capacitor upper electrode 30a via the drain lead line 7a, and the drain 8b of the 2 nd TFT12b is connected to the 2 nd sub-pixel electrode 17b via the drain lead line 7b and the contact hole 11 b.

The 2 nd storage capacitor line 21 is formed so as to cross the upper half portion of the 2 nd sub-pixel electrode 17b (on the opposite side of the side where the TFT12a and the TFT12b are located with the 1 st sub-pixel electrode 17a interposed therebetween) in the column direction (in the left-right direction in the drawing), and the storage capacitor upper electrode 30b is provided so as to overlap the 2 nd storage capacitor line 21 and the 2 nd sub-pixel electrode 17 b. The storage capacitor upper electrode 30b is connected to the 2 nd sub-pixel electrode 17b through the contact hole 11 c.

In fig. 1, the 1 st storage capacitor line 20 is surrounded by a frame shape, and overlaps the gap region 26, a region in the vicinity of the outer frame of the 1 st sub-pixel electrode 17a, and a region in the vicinity of the inner frame of the 2 nd sub-pixel electrode 17b, but is not limited thereto. For example, as in the pixel region 5 ' shown in fig. 28, the 1 st storage capacitor wire 20 ' and the 2 nd storage capacitor wire 21 ' may be formed along the column direction (the left-right direction in the figure) so as to sandwich the 1 st sub-pixel electrode 17 a. The drain of the 1 st TFT12a is connected to the storage capacitor upper electrode 30a formed on the 1 st storage capacitor line 20 ' via a drain lead line 7a ', the drain lead line 7a ' passing under the 1 st sub-pixel electrode 17 a. Further, the drain lead line 7 a' is connected to the 1 st sub-pixel electrode 17a through the contact hole 11 a. The drain of the 2 nd TFT12b is connected to the storage capacitor upper electrode 30b formed on the 2 nd storage capacitor line 21 'via the drain lead line 7 b'. The storage capacitor upper electrode 30b is connected to the 2 nd sub-pixel electrode 17b through the contact hole 11 b. In the structure shown in fig. 28, there is no lowest luminance region formed by the light-shielding body between the high luminance region 47a and the low luminance region 47b, and therefore, a structure is formed in which the high luminance region 47a and the low luminance region 47b are adjacent.

The structure shown in fig. 1 can be represented by the circuit shown in fig. 2. That is, the 1 st sub-pixel electrode 17a is connected to the data signal line 15 via the 1 st TFT12a, and the 2 nd sub-pixel electrode 17b is connected to the data signal line 15 via the 2 nd TFT12 b. In addition, the gates of the 1 st TFT12a and the 2 nd TFT12b are both connected to the scanning signal line 16. A holding capacitance Cs1 is formed between the holding capacitance upper electrode 30a connected to the 1 st sub-pixel electrode 17a and the 1 st holding capacitance line 20, and a holding capacitance Cs2 is formed between the holding capacitance upper electrode 30b connected to the 2 nd sub-pixel electrode 17b and the 2 nd holding capacitance line 21.

As described below, Cs signals (storage capacitor opposing voltages) having different phases are supplied to the 1 st storage capacitor line 20 and the 2 nd storage capacitor line 21 in fig. 2. When dot inversion driving or V-row inversion driving is performed on each pixel, signal potentials supplied to two pixels adjacent in the column direction (left-right direction in the drawing) are of opposite polarities. Therefore, in this case, the 1 st storage capacitor wiring 20 of a pixel is connected to the 2 nd storage capacitor wiring 21 of an adjacent pixel, and the 2 nd storage capacitor wiring 21 of the pixel is connected to the 1 st storage capacitor wiring 20 of the adjacent pixel.

Fig. 3 shows an equivalent circuit of a liquid crystal display device (liquid crystal panel) including the active matrix substrate 10. As shown in fig. 3, the 1 st sub-pixel capacitance Csp1 is formed by the 1 st sub-pixel electrode 17a, the counter electrode (Vcom), and the liquid crystal layer therebetween, and the 2 nd sub-pixel capacitance Csp2 is formed by the 2 nd sub-pixel electrode 17b, the counter electrode (Vcom), and the liquid crystal layer therebetween.

A method for driving the liquid crystal display device of the present embodiment will be described below.

In this embodiment, a display signal voltage is supplied from the same data signal line to the 1 st sub-pixel electrode and the 2 nd sub-pixel electrode surrounding the 1 st sub-pixel electrode, and after each TFT is turned off, the voltages of the 1 st storage capacitor line and the 2 nd storage capacitor line are changed so as to be different from each other. Thereby, a high luminance region by the 1 st sub-pixel capacitance Csp1 and a low luminance region by the 2 nd sub-pixel capacitance Csp2 are formed in one pixel, wherein the low luminance region surrounds the high luminance region. In the above-described structure, the display signal voltages are supplied to the two sub-pixel electrodes using the same data signal line, and thus there is an advantage in that the number of data signal lines and the number of source drivers for driving the data signal lines do not need to be increased.

Fig. 13 is a timing chart showing voltages of respective portions of the circuit shown in fig. 3. Vg denotes a voltage of a scanning signal line (gate of the 1 st TFT and the 2 nd TFT), Vs denotes a voltage of a data signal line (source voltage), Vcs1 denotes a voltage of the 1 st holding capacitance wiring, Vcs2 denotes a voltage of the 2 nd holding capacitance wiring, Vlc1 denotes a voltage of the 1 st sub-pixel electrode, and Vlc2 denotes a voltage of the 2 nd sub-pixel electrode. In addition, the liquid crystal display device generally performs ac driving such as frame inversion, line inversion, and dot inversion so as not to polarize the liquid crystal. That is, the source voltage (Vsp) having a positive polarity with respect to the middle value Vsc of the source voltage is supplied to the nth frame, the source voltage (Vsn) having a negative polarity with respect to Vsc is supplied to the next frame, that is, the (n +1) th frame, and dot inversion is performed every frame. Further, the oscillation is started with the amplitude voltage Vad, and the voltage of the 1 st storage capacitor line and the voltage of the 2 nd storage capacitor line are obtained, and the phase difference between the two is 180 degrees.

Hereinafter, the change of each voltage waveform with time in the n frame of fig. 13 will be described.

First, at time T0, Vcs1 becomes Vcom-Vad, and Vcs2 becomes Vcom + Vad. Vcom is a voltage of the counter electrode.

At time T1, Vg changes from VgL to VgH, and each TFT is turned on. As a result, Vlc1 and Vlc2 rise to Vsp, and the holding capacitances Cs1 and Cs2 and the sub-pixel capacitances Csp1 and Csp2 are charged.

At time T2, Vg changes from VgH to VgL, each TFT is turned off, and the holding capacitances Cs1 and Cs2 and the sub-pixel capacitances Csp1 and Csp2 are insulated from the data signal line. Then, a pull-in effect (pull-in effect) is generated due to the influence of parasitic capacitance or the like, and Vlc1 becomes Vsp-Vd1, and Vlc2 becomes Vsp-Vd 2.

At time T3, Vcs1 changes from Vcom-Vad to Vcom + Vad, and Vcs2 changes from Vcom + Vad to Vcom-Vad. As a result, Vlc1 ═ Vsp-Vd1+2 × K × Vad, and Vlc2 ═ Vsp-Vd2-2 × K × Vad. Here, K is Ccs/(Clc + Ccs), Ccs is a capacitance value of each holding capacitance (Cs1, Cs2), and Clc is a capacitance value of each sub-pixel capacitance (Csp1, Csp 2).

At time T4, Vcs1 changes from Vcom + Vad to Vcom-Vad, and Vcs2 changes from Vcom-Vad to Vcom + Vad. As a result, Vlc1 ═ Vsp-Vd1, and Vlc2 ═ Vsp-Vd 2.

At time T5, Vcs1 changes from Vcom-Vad to Vcom + Vad, and Vcs2 changes from Vcom + Vad to Vcom-Vad. As a result, Vlc1 ═ Vsp-Vd1+2 × K × Vad, and Vlc2 ═ Vsp-Vd2-2 × K × Vad.

Subsequently, T4 and T5 are repeated at integral multiples of the horizontal scanning period 1H until Vg becomes Vgh and writing is performed. Therefore, the effective value of Vlc1 is Vsp-Vd1+ KVad, and the effective value of Vlc2 is Vsp-Vd 2-KVad.

As described above, in the n-th frame, since the effective voltages (V1 and V2) of the sub-pixel capacitances (the 1 st sub-pixel capacitance Csp1 and the 2 nd sub-pixel capacitance Csp2) are V1 ═ Vsp-Vd1+ K × Vad-Vcom and V2 ═ Vsp-Vd2-K × Vad-Vcom, a high luminance region obtained by the 1 st sub-pixel capacitance Csp1 and a low luminance region obtained by the 2 nd sub-pixel capacitance Csp2 surrounding the high luminance region are formed in one pixel.

The change of each voltage waveform with time in the n +1 frame is explained below.

First, at time T0, Vcs1 becomes Vcom + Vad, and Vcs2 becomes Vcom-Vad. Vcom is a voltage of the counter electrode.

At time T1, Vg changes from VgL to VgH, and each TFT is turned on. As a result, Vlc1 and Vlc2 drop to Vsn, and the holding capacitances Cs1 and Cs2 and the sub-pixel capacitances Csp1 and Csp2 are charged.

At time T2, Vg changes from VgH to VgL, each TFT is turned off, and the holding capacitances Cs1 and Cs2 and the sub-pixel capacitances Csp1 and Csp2 are insulated from the data signal line. Then, the pull-in effect is generated by the influence of parasitic capacitance or the like, and Vlc1 ═ Vsn-Vd1 and Vlc2 ═ Vsn-Vd 2.

At time T3, Vcs1 changes from Vcom + Vad to Vcom-Vad, and Vcs2 changes from Vcom-Vad to Vcom + Vad. As a result, Vlc1 ═ Vsn-Vd1-2 × K × Vad, and Vlc2 ═ Vsn-Vd2+2 × K × Vad. Here, K is Ccs/(Clc + Ccs), Ccs is a capacitance value of each holding capacitance (Cs1, Cs2), and Clc is a capacitance value of each sub-pixel capacitance (Csp1, Csp 2).

At time T4, Vcs1 changes from Vcom-Vad to Vcom + Vad, and Vcs2 changes from Vcom + Vad to Vcom-Vad. As a result, Vlc1 ═ Vsn + Vd1, and Vlc2 ═ Vsn + Vd 2.

At time T5, Vcs1 changes from Vcom + Vad to Vcom-Vad, and Vcs2 changes from Vcom-Vad to Vcom + Vad. As a result, Vlc1 ═ Vsn-Vd1-2 × K × Vad, and Vlc2 ═ Vsn-Vd2+2 × K × Vad.

Subsequently, T4 and T5 are repeated at integral multiples of the horizontal scanning period 1H until Vg becomes Vgh and writing is performed. Therefore, the effective value of VLc1 is Vsn-Vd 1-KVad, and the effective value of VLc2 is Vsn-Vd2+ KVad.

As described above, in the n +1 th frame, since the effective voltages (V1 and V2) of the sub-pixel capacitances (Csp1 and Csp2) are V1-Vsn-Vd 1-K × Vad-Vcom and V2-Vsn-Vd 2+ K × Vad-Vcom, a high luminance region obtained by the 1 st sub-pixel capacitance Csp1 and a low luminance region obtained by the 2 nd sub-pixel capacitance Csp2 surrounding the high luminance region are formed in one pixel.

Further, as shown in fig. 35, it can be assumed that Vcs1 has a waveform that is maintained at "High" (or maintained at "Low") at T3 immediately after Vg becomes "L" (each TFT12a, 12b is off) at T2; similarly, it is assumed that Vcs2 has a waveform that is "Low" and maintained (or "High" and maintained) at T3 immediately after Vg is "L" at T2. That is, after each transistor is turned off, potential control is performed so that Vcs1 rises and the state after the rise is maintained in the frame, and at the same time, Vcs2 falls in synchronization with the rise of Vcs1 and the state after the fall is maintained in the frame. Alternatively, after each transistor is turned off, potential control is performed so that Vcs1 falls and the state after the fall is maintained in the frame, and simultaneously, Vcs2 rises in synchronization with the fall of Vcs1 and the state after the rise is maintained in the frame. The potential control shown in fig. 35 can be applied to a configuration in which the pixels adjacent vertically (in the direction along the data signal line) do not share the storage capacitor lines, and since the influence of the passivation of the waveforms of Vcs1 and Vcs2 on the effective drain potential can be reduced, the luminance unevenness can be effectively reduced.

As shown in fig. 31, it is possible to assume that the waveform of Vcs1 is "High" and maintained (or "Low" and maintained) at T3 immediately after Vg becomes "L" (each TFT12a, 12b is off) at T2, and assume that the waveform of Vcs2 is "Low" and maintained (or "Low" and maintained) at T4 after 1 horizontal period (1H) from T3. That is, after each transistor is turned off, potential control is performed so that Vcs1 rises and the state after the rise is maintained in the frame, and Vcs2 falls and the state after the fall is maintained in the frame with a period different from the rise of Vcs1 by 1H. Alternatively, after each transistor is turned off, potential control is performed so that Vcs1 falls and the state after the fall is maintained in the frame, and Vcs2 rises and the state after the rise is maintained in the frame with a period different from the rise of Vcs1 by 1H. The potential control shown in fig. 31 is advantageous in that it can be applied to a configuration in which the storage capacitor lines are not shared by vertically adjacent pixels (for example, fig. 1), and can also be applied to a configuration in which the storage capacitor lines are shared by vertically adjacent pixels (for example, fig. 8).

Next, the change with time of each voltage waveform in the n frames of fig. 31 will be described.

At time T2, Vg changes from VgH to VgL, each TFT is turned off, and the holding capacitances Cs1 and Cs2 and the sub-pixel capacitances Csp1 and Csp2 are insulated from the data signal line. Then, the pull-in effect is generated by the influence of parasitic capacitance or the like, and Vlc1 ═ Vsp-Vd1 and Vlc2 ═ Vsp-Vd 2.

At time T3, Vcs1 changes from Vcom-Vad to Vcom + Vad. At time T4 (after 1H of T3), Vcs2 changes from Vcom + Vad to Vcom-Vad. As a result, Vlc1 ═ Vsp-Vd1+2 × K × Vad, and Vlc2 ═ Vsp-Vd2-2 × K × Vad. Here, K is Ccs/(Clc + Ccs), Ccs is a capacitance value of each holding capacitance (Cs1, Cs2), and Clc is a capacitance value of each sub-pixel capacitance (Csp1, Csp 2).

According to the above, in the nth frame, the effective voltages (V1, V2) of the respective sub-pixel capacitances (the 1 st sub-pixel capacitance Csp1, the 2 nd sub-pixel capacitance Csp2) satisfy: since V1 ═ Vsp-Vd1+2 × K × Vad-Vcom and V2 ═ Vsp-Vd2-2 × K × Vad-Vcom, a clear sub-pixel obtained by the 1 st sub-pixel capacitance Csp1 and a dark sub-pixel obtained by the 2 nd sub-pixel capacitance Csp2 are formed in one pixel.

This reduces the influence of the passivation of the waveforms Vcs1 and Vcs2 on the effective drain potential, thereby effectively reducing the luminance unevenness.

Here, fig. 26 shows an example of luminance distribution between the high luminance region and the low luminance region in the present configuration. In addition, 256-gradation display is assumed, and the area ratio between the low-luminance region and the high-luminance region is assumed to be 1: 3. As shown by the curves a and b, the luminance (the amount of light per unit area) of the high luminance region is increased from 0 to 0.85 (the maximum luminance is set to 1) as the gradation increases until around the 128 gradation, and the luminance (the amount of light per unit area) of the low luminance region is set to 0 (the minimum luminance). Further, from around the 128 gradation to 255 gradations, as shown by a curve a and a curve b, the luminance of the high luminance region is increased from 0.85 to 1.0 as the gradation increases, and on the other hand, the luminance of the low luminance region is increased from 0 to 1.0. The luminance of each of the low-luminance region and the high-luminance region is integrated in area, and the resultant of the integrations is the total luminance of the entire pixel (curve c is a γ characteristic).

Thus, in the liquid crystal display device of the present embodiment, a high-luminance region and a low-luminance region surrounding the high-luminance region can be formed in each pixel. The following description: by forming a high-luminance region in each pixel and a low-luminance region surrounding the high-luminance region, a video having a high spatial frequency can be clearly displayed.

Fig. 21(a) is a schematic diagram showing a video with a low spatial frequency. Fig. 21(b) is a schematic diagram showing a video with a high spatial frequency. Here, the ratio of the amplitude of the input sinusoidal waveform, which is a video signal, to the amplitude of the output to the display is taken as the transmission characteristic. Fig. 22(a) is a schematic diagram showing a display device in which pixels having a large lighting area are arranged in a matrix, and fig. 22(b) is a schematic diagram showing a display device in which pixels having a small lighting area are arranged in a matrix. Fig. 23 shows the transmission characteristics of the display device shown in fig. 22(a) and the transmission characteristics of the display device shown in fig. 22 (b).

As can be seen from fig. 23, the display device having a small lighting area has better transmission characteristics than the display device having a large lighting area, that is, can more clearly display a video having a high spatial frequency as shown in fig. 21 (b). The present invention is based on the above principle, and has a pixel structure in which a high-luminance region and a low-luminance region surrounding the high-luminance region can be formed in one pixel, and the entire or most of the total luminance of the entire pixel is provided by the high-luminance region (light emission is concentrated in the center of the pixel) (occupies the majority of the display), thereby enabling halftone display. This can significantly improve the transmission characteristics in the high spatial frequency region, and clearly display a video having a high spatial frequency.

Further, as shown in fig. 15a, in the present active matrix substrate, since the high-luminance region is formed in the central portion of each pixel and the position of the high-luminance region of each pixel is the same between the pixels in the row direction (vertical direction in the drawing), the video signal shown in fig. 14 can be displayed more clearly than the configuration shown in fig. 15b, that is, the configuration in which the position of the high-luminance region of each pixel is shifted between the pixels in the row direction (vertical direction in the drawing).

In the present active matrix substrate shown in fig. 1, the 1 st storage capacitor wiring 20 is surrounded in a frame shape so as to overlap a region (gap region 26) between the 1 st pixel electrode and the 2 nd pixel electrode. Therefore, in the liquid crystal display device having the active matrix substrate of the present invention, it is possible to prevent a phenomenon such as a decrease in contrast due to light leakage from the gap region 26.

In addition, in the present embodiment, since the light-shielding body (the 1 st storage capacitor wiring 20) is provided on the active matrix substrate itself, there is no problem that the light-shielding effect is lowered due to misalignment when bonding the substrates, as in the case where the light-shielding body is provided on the color filter substrate.

In the configuration shown in fig. 1, the 1 st storage capacitor line 20 is surrounded in a frame shape in 1 pixel region, and since the 1 st storage capacitor line 20 has a plurality of vias, disconnection of the 1 st storage capacitor line can be effectively prevented.

The present active matrix substrate can also be formed into the structure shown in fig. 4. That is, in the pixel region 105, a 1 st TFT (thin film transistor) 112a, a 2 nd TFT112b, a 1 st sub-pixel electrode 117a, and a 2 nd sub-pixel electrode 117b are formed.

The 2 nd sub-pixel electrode 117b has a partially hollowed rectangular shape, and has a large outer frame 117x and a small inner frame (outer edge of the hollowed portion) 117 y. A 1 st sub-pixel electrode 117a having a rectangular shape is provided inside the inner frame 117 y. That is, in the present embodiment, the 2 nd sub-pixel electrode 117b surrounds the 1 st sub-pixel electrode 117a having a rectangular shape.

Gap regions (126a to 126d) are formed between the outer frame 117z of the 1 st sub-pixel electrode 117a and the inner frame 117y of the 2 nd sub-pixel electrode. The gap region is frame-shaped and includes a region 126a and a region 126b extending in a column direction (left-right direction in the figure), and a region 126c and a region 126d extending in a row direction (up-down direction in the figure). Here, the 1 st storage capacitor line 121 is formed so as to overlap the gap region 126a, the region in the vicinity of the outer frame of the 1 st sub-pixel electrode 117a, and the region in the vicinity of the inner frame of the 2 nd sub-pixel electrode 117 b; the 2 nd storage capacitor line 120 is formed so as to overlap the gap region 126b, the region in the vicinity of the outer frame of the 1 st sub-pixel electrode 117a, and the region in the vicinity of the inner frame of the 2 nd sub-pixel electrode 117 b. Further, a storage capacitor upper electrode 130a is provided so as to overlap the 1 st storage capacitor wiring 120 and the 1 st sub-pixel electrode 117a, and the storage capacitor upper electrode 130a and the 1 st sub-pixel electrode 117a are connected through a contact hole 111 a. The storage capacitor upper electrode 130b is provided so as to overlap the 2 nd storage capacitor line 121 and the 2 nd sub-pixel electrode 117 b.

The 1 st TFT112a and the 2 nd TFT112b are formed near the intersection of the signal lines (15, 16), and the source 109a of the 1 st TFT112a and the source 109b of the 2 nd TFT112b are both connected to the data signal line 15. The drain 108a of the 1 st TFT112a is connected to the storage capacitor upper electrode 130a via a drain lead line 107 a. Here, the drain lead line 107a is provided so as to overlap a region 126c extending in the row direction (vertical direction in the drawing), a region near the outer frame of the 1 st sub-pixel electrode 117a, and a region near the inner frame of the 2 nd sub-pixel electrode 117 b. The drain 108b of the 2 nd TFT112b is connected to the 2 nd sub-pixel electrode 117b through the drain lead line 107b and the contact hole 111 b. Further, the drain lead line 107b is provided so as to overlap a region 126d extending in the row direction (vertical direction in the figure), a region near the outer frame of the 1 st sub-pixel electrode 117a, and a region near the inner frame of the 2 nd sub-pixel electrode 117b, and is connected to the storage capacitor upper electrode 130 b.

As shown in fig. 5, in order to increase the aperture ratio, the portion of the drain lead line 107b that does not overlap the region 126d may be removed, and the 2 nd sub-pixel electrode 117b and the storage capacitor upper electrode 130b may be connected through the contact hole 111 c.

The active matrix substrate shown in fig. 4 and 5 described above can be implemented as the circuit shown in fig. 6. The driving method described with reference to fig. 13 can be applied to a liquid crystal display device having the active matrix substrate shown in fig. 4 and 5.

The present active matrix substrate can also have a structure as shown in fig. 8. That is, a 1 st TFT (thin film transistor) 212a, a 2 nd TFT212b, a 1 st sub-pixel electrode 217a, and a 2 nd sub-pixel electrode 217b are formed in the pixel region 205.

The 2 nd sub-pixel electrode 217b has a shape in which a part of a rectangle is hollowed out, and has a larger rectangle outer frame 217x and a smaller rectangle inner frame (outer edge of the hollowed-out part) 217 y. A 1 st sub-pixel electrode 217a having a rectangular shape is provided inside the inner frame 217 y. That is, the present embodiment is configured such that the 2 nd sub-pixel electrode 217b surrounds the 1 st sub-pixel electrode 217a having a rectangular shape.

In this structure, the scanning signal line 216 is provided at a substantially middle position of the pixel region 205. The scanning signal line 216 in the pixel region 205 is composed of 3 portions of a left end portion 216a, a frame portion 216b, and a right end portion 216c, where the left end portion 216a is the gate of the 1 st TFT212a and the 2 nd TFT212 b. The 1 st TFT212a and the 2 nd TFT212b are formed near the intersection of the signal lines (15, 216), and the source 209a of the 1 st TFT212a and the source 209b of the 2 nd TFT212b are both connected to the data signal line 15.

A gap area 226 is formed between the outer frame 217z of the 1 st sub-pixel electrode 217a and the inner frame 217y of the 2 nd sub-pixel electrode, and the frame portion 216b is formed so as to surround the scanning signal line 216 in a frame shape so as to overlap the gap area 226, the area in the vicinity of the outer frame of the 1 st sub-pixel electrode 217a, and the area in the vicinity of the inner frame of the 2 nd sub-pixel electrode 217 b. The drain 208a of the 1 st TFT212a is connected to the 1 st sub-pixel electrode 217a through a drain lead line and a contact hole 211 a.

Further, the 1 st storage capacitor wiring 220 and the 2 nd storage capacitor wiring 221 are formed in the upper and lower end portions (both edges in the row direction) of the pixel region 205 and in the column direction (the left and right direction in the figure). Further, a storage capacitor upper electrode 230a is provided so as to overlap the 1 st storage capacitor wiring 220, and the storage capacitor upper electrode 230a is connected to the drain 208 a. Further, a storage capacitor upper electrode 230b is provided so as to overlap the 2 nd storage capacitor wiring 221, and the storage capacitor upper electrode 230b is connected to the drain 208b and to the 2 nd sub-pixel electrode 217b through a contact hole 211 b.

According to the configuration shown in fig. 8, the 1 st storage capacitor 220 and the 2 nd storage capacitor line 221 can be shared between the pixels adjacent to each other vertically, and therefore the total number of storage capacitor lines can be reduced. In addition, in the 1 pixel region, the scanning signal line 216 is surrounded in a frame shape, and the scanning signal line 216 has a plurality of paths, so that disconnection of the scanning signal line can be effectively prevented.

The active matrix substrate shown in fig. 8 described above can be implemented as the circuit shown in fig. 7. The driving method described with reference to fig. 13 can be applied to a liquid crystal display device having the active matrix substrate shown in fig. 8.

The present active matrix substrate can also have a structure as shown in fig. 9. That is, in the pixel region 305, a 1 st TFT (thin film transistor) 312a, a 2 nd TFT312b, a 1 st sub-pixel electrode 317a, and a 2 nd sub-pixel electrode 317b are formed.

In the present structure, two

data signal lines

315a and 315b are provided for 1 pixel region 305. The data signal

lines

315a and 315b are formed in the row direction (vertical direction in the figure) and in the vicinity of the ends of both sides of the pixel region 305.

The 2 nd sub-pixel 317b has a partially hollowed rectangular shape, and has an outer frame 317x having a large rectangular shape and an inner frame 317y (outer edge of the hollowed portion) having a small rectangular shape. Inside the inner frame 317y, a 1 st sub-pixel electrode 317a having a rectangular shape is provided. That is, in this embodiment, the 1 st sub-pixel electrode 317a having a rectangular shape is surrounded by the 2 nd sub-pixel electrode 317 b.

A gap area 326 is formed between the outer frame 317z of the 1 st sub-pixel electrode 317a and the inner frame 317y of the 2 nd sub-pixel electrode, and the storage capacitor wiring 320 is surrounded in a frame shape so as to overlap the gap area 326, the area in the vicinity of the outer frame of the 1 st sub-pixel electrode 317a, and the area in the vicinity of the inner frame of the 2 nd sub-pixel electrode 317 b. Further, a storage capacitor upper electrode 330a is provided so as to overlap the storage capacitor wiring 320 and the 1 st sub-pixel electrode 317a, and the storage capacitor upper electrode 330a is connected to the 1 st sub-pixel electrode 317a through a contact hole 311 a. The storage capacitor upper electrode 330b is provided so as to overlap the storage capacitor wiring 320 and the 2 nd sub-pixel electrode 317b, and the storage capacitor upper electrode 330b is connected to the 2 nd sub-pixel electrode 317b through the contact hole 311 b.

The 1 st TFT312a is formed near an intersection of a scanning signal line and one of the data signal lines 315a, the source 309a of the 1 st TFT312a is connected to the data signal line 315a, and the drain 308a of the 1 st TFT312a is connected to the storage capacitor upper electrode 330a via a drain lead line. The 2 nd TFT312b is formed near an intersection of a scanning signal line and another data signal line 315b, the source 309b of the 2 nd TFT312b is connected to the data signal line 315b, and the drain 308b of the 1 st TFT312b is connected to the storage capacitor upper electrode 330b via a drain lead line.

The active matrix substrate shown in fig. 9 described above is realized by a circuit shown in fig. 12. Here, the two

data signal lines

315a and 315b arranged in the respective pixels are independently driven, and, for example, signal potentials are applied from source drivers controlled by a liquid crystal controller.

Fig. 27 shows an example of distribution of luminance (light amount per unit area) between the high luminance region and the low luminance region in the present configuration. In addition, assuming 256-gradation display, the area ratio between the low-luminance region and the high-luminance region is 1: 3. As shown in the curves a and b, the luminance in the high luminance region is increased from 0 to 1.0 (normalized maximum luminance) as the gradation increases until the vicinity of the 128 gradation, and the luminance in the low luminance region is set to 0 (normalized minimum luminance). Further, from around the 128 gradation level to the 255 gradation level, as shown by the curves a and b, the luminance in the high luminance region is set to 1.0, and the luminance in the low luminance region is increased from 0 to 1.0 as the gradation level increases. The luminance of each of the low-luminance region and the high-luminance region is integrated in area, and the resultant of the integrations is the total luminance of the entire pixel (curve c is a γ characteristic).

As shown in fig. 10, the active matrix substrate shown in fig. 8 may be formed in an MVA (Multi-domain vertical Alignment) structure. That is, slits (slits for controlling the alignment of liquid crystal molecules) 255 for controlling the alignment of liquid crystal molecules are provided in the 1 st sub-pixel electrode 217a and the 2 nd sub-pixel electrode 217b, and the slits 255 are formed in a horizontal V shape (a shape in which the V is rotated by 90 degrees). The MVA structure described above is: slits (electrode cut patterns) are provided in the pixel electrodes of the active matrix substrate, and projections (flanges) for controlling the alignment of liquid crystal molecules are provided in the counter electrode of the counter substrate, and the Fringe Field (Fringe Field) formed as described above is used. The orientation directions of the liquid crystal molecules are dispersed in a plurality of directions by the fringe field, thereby realizing a wide viewing angle. Similarly, the active matrix substrate shown in fig. 9 may be formed in an MVA structure (see fig. 11).

The active matrix substrate of the present embodiment can also have a structure shown in fig. 29. The active matrix substrate shown in fig. 29 includes: a pixel region 405 arranged in a matrix, a 1 st scanning signal line 416a and a 2 nd scanning signal line 416b located at a lower end and an upper end of the pixel region in a column direction (in the left-right direction in the figure), respectively, a data signal line 415 in a row direction (in the up-down direction in the figure), and a storage capacitor line 420.

The pixel region 405 includes a 1 st TFT412a, a 2 nd TFT412b, a 1 st sub-pixel electrode 417a, and a 2 nd sub-pixel electrode 417 b. The 2 nd sub-pixel 417b has a rectangular shape with a part hollowed out, and has an outer frame 417x having a large rectangular shape and an inner frame (outer edge of the hollowed-out part) 417y having a small rectangular shape. Inside the inner frame 417y, a 1 st sub-pixel electrode 417a having a rectangular shape is provided. That is, in this embodiment, the 1 st sub-pixel electrode 417a having a rectangular shape is surrounded by the 2 nd sub-pixel electrode 417 b.

Forming a holding capacitance wiring 420 so as to cross the central portion of the pixel region; a storage capacitor upper electrode 430b is provided so as to overlap the storage capacitor wiring 420 and the 2 nd sub-pixel electrode 417 b; the storage capacitor upper electrode 430a is provided so as to overlap the storage capacitor line 420 and the 1 st sub-pixel electrode 417 a.

Here, the 1 st TFT412a is formed near the intersection of the data signal line 415 and the 1 st scanning signal line 416a, and the 1 st scanning signal line 416a serves as the gate of the 1 st TFT412 a. The 2 nd TFT412b is formed near the intersection of the data signal line 415 and the 2 nd scanning signal line 416b, and the 2 nd scanning signal line 416b serves as the gate of the 2 nd TFT412 b. The source of the 1 st TFT412a and the source of the 2 nd TFT412b are both connected to the data signal line 415.

The drain of the 1 st TFT412a is connected to the storage capacitor upper electrode 430a via the drain lead line 407a, and the storage capacitor upper electrode 430a is connected to the 1 st sub-pixel electrode 417a via the contact hole 411 a. The drain of the 2 nd TFT412b is connected to the storage capacitor upper electrode 430b via the drain lead line 407b, and the storage capacitor upper electrode 430b is connected to the 2 nd pixel electrode 417b via the contact hole 411 b.

According to the above configuration, a circuit shown in fig. 30 can be realized. That is, the 1 st sub-pixel electrode 417a is connected to the data signal line 415 via the 1 st TFT412a, and the 2 nd sub-pixel electrode 417b is connected to the data signal line 415 via the 2 nd TFT412 b. The gate of the 1 st TFT412a is connected to the 1 st scan signal line 416a, and the gate of the 2 nd TFT412b is connected to the 2 nd scan signal line 416 b. Further, a storage capacitor CS is formed between the storage capacitor upper electrode 430a connected to the 1 st sub-pixel electrode 417a and the storage capacitor wiring 420, and similarly, a storage capacitor CS is formed between the storage capacitor upper electrode 430b connected to the 2 nd sub-pixel electrode 417b and the storage capacitor wiring 420. Scan signals (pulse signals) of different timings are supplied to the 1 st and 2 nd scan signal lines 21. Assume that the 1 st and 2 nd scan signal lines for the next stage are 416c and 416d, respectively, and assume that the 1 st TFT and the 2 nd TFT for the next stage are 417c and 417d, respectively.

Fig. 32 shows signal waveforms in the case where the circuit shown in fig. 30 is driven by dot inversion (S in the figure is a waveform of a potential signal supplied to the data signal line 415, and a to D are waveforms of pulse signals supplied to the scanning signal lines 416a to 416D, respectively).

As shown in fig. 32, in one horizontal period, on pulses (scanning signals) are supplied in the order of the 1 st scanning signal line 416a and the 2 nd scanning signal line 416b, and signal potentials V1 and V2 (both positive polarity) are supplied to the data signal line 415 in accordance with the on pulses. In addition, the on pulses supplied to the 1 st and 2 nd scan signal lines do not overlap in time. Thus, V1 is written to the 1 st sub-pixel electrode 417a via the 1 st TFT412a, and V2 is written to the 2 nd sub-pixel electrode 417b via the 2 nd TFT412 b. Further, in the next horizontal period, the on pulses are supplied in the order of the 1 st scanning signal line 416c and the 2 nd scanning signal line 416d of the next stage, and the signal potentials v1 and v2 (both negative polarities) are supplied to the data signal line 415 in accordance with the respective on pulses. Thereby, v1 is written to the 1 st sub-pixel electrode 417c of the next stage, and v2 is written to the 2 nd sub-pixel electrode 417d of the next stage.

In addition, when dot inversion driving is performed by the circuit shown in fig. 30, signal waveforms shown in fig. 33 (S in the figure is a waveform of a potential signal supplied to the data signal line 415, and a to D are waveforms of pulse signals supplied to the scanning signal lines 416a to 416D, respectively) can be realized.

That is, in one horizontal period, the on pulses (scanning signals) are supplied to the 1 st scanning signal line 416a and the 2 nd scanning signal line 416b, and the signal potentials V1 and V2 (both negative polarities) are supplied to the data signal line 415 in accordance with the respective on pulses. Here, it is set that the on pulse supplied to the 1 st scanning signal line and the on pulse supplied to the 2 nd scanning signal line partially overlap in time, and pulse end timings of both are different. For example, in the two on pulses, the start timing of the pulse is set to be synchronous, and the end timing of the on pulse supplied to the 1 st scanning signal line 416a is set to be earlier than the end timing of the pulse. For another example, the end timings of the two on pulses are staggered 1/2H (half of one horizontal period). In addition, the setting is performed: the potential supplied to the data signal line 415 may become v1 in synchronization with or before the start of each conduction pulse, and change from v1 to v2 in synchronization with or after the end of the timing of the previous end of the conduction pulse (conduction pulse supplied to the 1 st scan signal line) which has previously ended. Thus, v1 is written into the 1 st sub-pixel electrode 417a, and v1 is written into the 2 nd sub-pixel electrode 417b, followed by v 2. Further, in the next horizontal period, the on pulse is supplied to the 1 st scanning signal line 416c and the 2 nd scanning signal line 416d in the next stage at the above timing, and the signal potentials V1 and V2 (both positive polarities) are supplied to the data signal line 415 in accordance with the respective on pulses (that is, in synchronization with the timing of the preceding end of the on pulse supplied to the 1 st scanning signal line 416a, or after the end of the on pulse, the potential changes from V1 to V2). Thus, V1 is written to the 1 st sub-pixel electrode 417c of the next stage, and V1 is written to the 2 nd sub-pixel electrode 417d of the next stage, and then V2 is written.

Thus, v1 (having the same potential polarity as that to be written) is supplied to the 2 nd sub-pixel electrode 417b, and then v2 to be written is supplied, whereby the 2 nd sub-pixel electrode 417b can be charged satisfactorily. The 2 nd sub-pixel electrode 417b is connected to the 2 nd TFT412b controlled by the 2 nd scanning signal line 416 b. In particular, it is particularly effective in the case where the polarity of the signal potential supplied to the data signal line 415 is inverted every horizontal period (waveform distortion of the signal potential is large) as in the dot inversion driving or the H-line inversion driving, and in the case where the area of the 2 nd sub-pixel electrode 417b is large (charging time is long). In addition, since the driving method shown in fig. 33 makes the period of the on pulse longer than the driving method shown in fig. 32, the driving frequency of the scanning signal can be effectively suppressed.

The active matrix substrate and the color filter substrate obtained in the above embodiment are stacked, and resin is injected and sealed to form a liquid crystal display panel. The color filter substrate is formed of colored layers and a black matrix having light-shielding properties between the colored layers, and the colored layers are any one of red, green, and blue colored layers provided in a matrix form corresponding to each pixel of the active matrix substrate.

Fig. 34 shows a structure of the liquid crystal panel. As shown in fig. 34, the liquid crystal panel 80 includes, in order from the backlight light source side: a polarizing plate 41, the present active matrix substrate 10 including the glass substrate 28, an alignment film 82, a liquid crystal layer 43, a color filter substrate 84, and a polarizing plate 85. The color filter substrate 84 includes, in order from the liquid crystal layer 43 side, an alignment film 85, a common (opposite) electrode 86, a colored layer 87 (including a black matrix 99), and a glass substrate 88. A projection (flange) 86x for controlling the alignment of liquid crystal molecules is provided on the common (opposite) electrode 86. The liquid crystal molecule alignment control protrusion 86x may be formed of, for example, a photosensitive resin. As the planar shape (viewed from the direction perpendicular to the substrate surface) of the flange 86x, for example, a band shape (horizontal V-shape) bent in a zigzag shape at a certain period is exemplified. The liquid crystal display device of the present invention is formed by connecting a driver (liquid crystal driving LSI) or the like to the liquid crystal panel and attaching a polarizing plate and a backlight.

A television receiver to which the liquid crystal display device is applied will be described below.

Fig. 16 is a block diagram showing a circuit of a liquid crystal display device 601 in the television receiver. As shown in fig. 16, the liquid crystal display device 601 includes a Y/C separation circuit 500, a video chromaticity circuit 501, an a/D converter 502, a liquid crystal controller 503, a liquid crystal panel 504, a backlight drive circuit 505, a backlight 506, a microcomputer 507, and a gradation circuit 508. In the liquid crystal display device 601 having the above-described configuration, an input video signal of a television broadcast signal is first input to the Y/C separation circuit 500, and a luminance signal and a chrominance signal are separated. The luminance signal and the chrominance signal are converted into 3 primary colors of light, i.e., R, G, B, in the video chrominance circuit 501, and the analog RGB signal is converted into a digital RGB signal by the a/D converter 502 and input to the liquid crystal controller 503. RGB signals are input to the liquid crystal panel 504 at predetermined timings from the liquid crystal controller 503, and at the same time, gradation voltages of each of RGB are supplied from the gradation circuit 508 to the liquid crystal panel 504, whereby an image is displayed. The overall control of the system including the above-described processing is performed by the microcomputer 507. Further, the display can be performed based on various video signals as video signals, for example, video signals based on television broadcasting, video signals captured by a camera, video signals supplied through a network line, and the like.

The present active matrix substrate can also be used for a field sequential liquid crystal display device. The 1 pixel of the field sequential method shown in fig. 17a corresponds to the 3 pixels (R, G, B) of the color filter method shown in fig. 17b, and 3 colors (R, G, B) of 3 primary colors are continuously displayed in 1 pixel (only 1 color is displayed at a certain time). In the field sequential liquid crystal display device, for example, the driving shown in fig. 8 is performed. That is, 1 frame is divided into 3 subframes (1 st to 3 rd subframes), and when a video signal of R is transmitted in the 1 st subframe, the backlight is turned on to R (red), and the liquid crystal panel performs signal display of R. Similarly, in the 2 nd sub-frame, when a video signal of G is transmitted, the backlight is turned on to G (green), and the liquid crystal panel performs signal display of G. In the 3 rd sub-frame, when the video signal of B is transmitted, the backlight is turned on to be B (blue), and the liquid crystal panel performs signal display of B.

Unlike the configuration using color filters (the position of color information is shifted for each color as shown in fig. 19 (b)), the above-described configuration of the field sequential method has an advantage that the position of color information is not shifted for each color (one position at the center of a pixel as shown in fig. 19 (a)). Here, fig. 20 is a circuit block diagram showing a field sequential liquid crystal display device.

As shown in fig. 24, the liquid crystal display device 601 is connected to a tuner unit 600 that receives television broadcasts and outputs video signals, and is capable of displaying images (videos) based on the video signals output from the tuner unit 600. In this case, the television receiver 602 is formed by the liquid crystal display device 601 and the tuner section 600.

As shown in fig. 25, a television receiver 602 using a liquid crystal display device 601 is configured such that a 1 st enclosure 801 and a 2 nd enclosure 806 enclose and sandwich the liquid crystal display device 601. The 1 st enclosure 801 is formed with an opening 801a through which a video displayed on the liquid crystal display device 601 is transmitted. The 2 nd enclosure 806 has an operation circuit 805 for operating the liquid crystal display device 601 and a support member 808 is provided below the 2 nd enclosure 806, and the 2 nd enclosure 806 covers the back surface of the liquid crystal display device 601.

The present invention is not limited to the liquid crystal display device, and can be applied to an organic EL display device. For example, an organic EL display device is configured by disposing a color filter substrate, disposing the active matrix substrate at a position where the color filter substrate faces each other, disposing an organic EL layer between the two substrates, thereby forming an organic EL panel, and connecting a driver to an external lead-out end of the panel. The present invention can also be applied to a display device formed using an active matrix substrate, other than the liquid crystal display device or the organic EL display device.

Industrial applicability

The active matrix substrate of the present invention is suitable for a liquid crystal television, for example.

Claims

1. A display device, characterized in that:

comprises a plurality of pixels;

in each pixel, a 1 st luminance region and a 2 nd luminance region can be formed, and the 2 nd luminance region surrounds the 1 st luminance region and has a luminance lower than that of the 1 st luminance region.

2. The display device according to claim 1, wherein:

each pixel includes a 1 st switching element, a 2 nd switching element, a 1 st sub-pixel electrode connected to the 1 st switching element, and a 2 nd sub-pixel electrode connected to the 2 nd switching element and surrounding the 1 st sub-pixel electrode.

3. The display device according to claim 1, wherein:

the 1 st luminance region and the 2 nd luminance region are both in a shape having the same point as the center of gravity.

4. The display device according to claim 1, wherein:

the 1 st luminance region and the 2 nd luminance region are formed with a lowest luminance region therebetween.

5. The display device according to claim 1, wherein:

the 1 st luminance region and the 2 nd luminance region are adjacent to each other.

6. The display device according to claim 4, wherein:

includes an active matrix substrate and a color filter substrate; the minimum brightness region is formed of at least one of a black matrix provided on the color filter substrate and a light-shielding body provided on the active matrix substrate.

7. The display device according to claim 2, wherein:

the 1 st switching element and the 2 nd switching element are connected to the same data signal line.

8. The display device according to claim 7, wherein:

the 1 st switching element and the 2 nd switching element are connected to the same scanning signal line.

9. The display device according to claim 8, wherein:

a 1 st storage capacitor line and a 2 nd storage capacitor line, wherein the 1 st storage capacitor line and the 1 st sub-pixel electrode form a capacitance, and the 2 nd storage capacitor line and the 2 nd sub-pixel electrode form a capacitance;

the potential of the 1 st storage capacitor line and the potential of the 2 nd storage capacitor line can be controlled separately.

10. The display device according to claim 9, wherein:

the 1 st storage capacitor line and the 2 nd storage capacitor line are potential-controlled so that the phase difference between the potential waveforms of the two lines is 180 degrees.

11. The display device according to claim 9, wherein:

potential control is performed on the 1 st storage capacitor line so that a potential rises after each switching element is turned off and remains in that state until each switching element is turned off in the next frame, and potential control is performed on the 2 nd storage capacitor line so that a potential falls after each switching element is turned off and remains in that state until each switching element is turned off in the next frame; or,

the 1 st storage capacitor line is potential-controlled so that a potential decreases after each switching element is turned off and is maintained in that state until each switching element is turned off in the next frame, and the 2 nd storage capacitor line is potential-controlled so that a potential increases after each switching element is turned off and is maintained in that state until each switching element is turned off in the next frame.

12. The display device according to claim 2, wherein:

the 1 st switching element is connected to the 1 st scanning signal line, and the 2 nd switching element is connected to the 2 nd scanning signal line.

13. The display device according to claim 12, wherein:

the on pulse supplied to the 1 st scanning signal line and the on pulse supplied to the 2 nd scanning signal line are not temporally coincident.

14. The display device according to claim 12, wherein:

the on pulse supplied to the 1 st scanning signal line and the on pulse supplied to the 2 nd scanning signal line partially overlap in time, and the pulse end timings of the two are different.

15. The display device according to claim 14, wherein:

the pulse start timing of the on pulse supplied to the 1 st scanning signal line and the pulse start timing of the on pulse supplied to the 2 nd scanning signal line are synchronized, and the end timing of the on pulse supplied to the 1 st scanning signal line is earlier.

16. The display device according to claim 13 or 14, wherein:

the potential supplied to the data signal line changes in synchronization with or after the end of the preceding end of the previously ended on pulse.

17. The display device according to claim 7, wherein:

the potential supplied to the same data signal line is inverted in polarity during each horizontal period.

18. The display device according to claim 2, wherein:

the 1 st switching element and the 2 nd switching element are connected to a 1 st data signal line and a 2 nd data signal line, respectively, which are independent of each other.

19. The display device according to claim 18, wherein:

the 1 st luminance region and the 2 nd luminance region are formed by supplying different signal potentials to the 1 st data signal line and the 2 nd data signal line.

20. An active matrix substrate, characterized in that:

comprises a plurality of pixel regions;

in each pixel region, a 1 st switching element, a 2 nd switching element, a 1 st sub-pixel electrode connected to the 1 st switching element, and a 2 nd sub-pixel electrode connected to the 2 nd switching element and surrounding the 1 st sub-pixel electrode are provided.

21. The active matrix substrate according to claim 20, wherein:

22. The active matrix substrate according to claim 20, wherein:

one data signal line is arranged in each pixel region, the data signal line connecting the 1 st switching element and the 2 nd switching element, and,

a1 st storage capacitor line and a 2 nd storage capacitor line are provided, wherein the 1 st storage capacitor line and the 1 st sub-pixel electrode form a capacitance, and the 2 nd storage capacitor line and the 2 nd sub-pixel electrode form a capacitance.

23. The active matrix substrate according to claim 20, wherein:

a1 st data signal line and a 2 nd data signal line are arranged independently of each other in each pixel region, the 1 st data signal line being connected to the 1 st switching element, and the 2 nd data signal line being connected to the 2 nd switching element.

24. The active matrix substrate according to claim 20, wherein:

a light-shielding body is formed so as to overlap with a boundary portion between the 1 st sub-pixel electrode and the 2 nd sub-pixel electrode.

25. The active matrix substrate according to claim 20, wherein:

a part of the wiring drawn from the 1 st sub-pixel electrode or the 2 nd sub-pixel electrode overlaps with a boundary portion between the 1 st sub-pixel electrode and the 2 nd sub-pixel electrode.

26. The active matrix substrate according to claim 21, wherein:

a part of the scanning signal line overlaps a boundary portion between the 1 st sub-pixel electrode and the 2 nd sub-pixel electrode.

27. The active matrix substrate according to claim 22, wherein:

a part of the 1 st storage capacitor line overlaps a boundary portion between the 1 st sub-pixel electrode and the 2 nd sub-pixel electrode.

28. The active matrix substrate according to claim 26, wherein:

the scanning signal line is surrounded in a frame shape at a middle portion of the pixel and overlaps the boundary portion.

29. The active matrix substrate according to claim 27, wherein:

the 1 st storage capacitor line is surrounded in a frame shape at an intermediate portion of the pixel and overlaps the boundary portion.

30. The display device according to claim 11, wherein:

the potential of the 1 st storage capacitor line rises in synchronization with the potential of the 2 nd storage capacitor line, or the potential of the 1 st storage capacitor line falls in synchronization with the potential of the 2 nd storage capacitor line.

31. The display device according to claim 11, wherein:

the potential of the 1 st storage capacitor line may rise horizontally away from the potential of the 2 nd storage capacitor line, or the potential of the 1 st storage capacitor line may fall horizontally away from the potential of the 2 nd storage capacitor line.

32. A display device, characterized in that:

comprising the active matrix substrate of claim 20.

33. A display device, characterized in that:

a backlight comprising the active matrix substrate of claim 20 and emitting light in multiple colors in a time division manner; and performing field time sequence display.

34. A liquid crystal display device, characterized in that:

comprising a display device according to any one of claims 1, 32, 33.

35. A television receiver, characterized by:

comprising the display device according to any one of claims 1, 32, and 33 and a tuner section for receiving television broadcasting.