CN101364764A

CN101364764A - Voltage pump apparatus and operating method thereof

Info

Publication number: CN101364764A
Application number: CNA2007101431387A
Authority: CN
Inventors: 吴政颖; 林信章
Original assignee: Yield Microelectronics Corp
Current assignee: Yield Microelectronics Corp
Priority date: 2007-08-06
Filing date: 2007-08-06
Publication date: 2009-02-11
Anticipated expiration: 2027-08-06
Also published as: CN101364764B

Abstract

The invention discloses a voltage pumping device and the operation method thereof. The voltage pumping device consists of a plurality level of charge transfer units serially connected with each other, and an output unit, wherein each level of the charge transfer unit includes a first node for input, a second node for output, a first circuit and a first capacitor. The first circuit provided with a bias can be biased at the first node or the second node, so that the first capacitors of the charge transfer units of the odd-numbered levels and the even-numbered levels can be used for respectively receiving two sequential signals with reverse phase to carry out complementary switch operation, and can generate an output voltage with high negative level in combination with the switch of the output unit. The voltage pumping device has the advantages of eliminated matrix effect and high pump gain.

Description

Voltage pump apparatus and method of operation thereof

Technical field

The present invention relates to the technology of a kind of voltage pump (charge pump), especially refer to a kind of matrix effect and group's Pu gain (pumping gain) high voltage pump apparatus and method of operation thereof eliminated.

Background technology

General fast flash memory bank (FLASH memory) or electric read-only memory able to programme (the Electrically Erasable ProgramMable Read Only Memory that can erase, EEPROM) need negative voltage, carry out that data is erased or programing function so that produce enough relative potential differences with high positive voltage.

Fig. 1 (a) is a known voltage pump apparatus 10, it utilizes the PMOS electric crystal of serial connection to shift electric charge on the load capacitance of output node, the input node ground connection of this device, the drain of each PMOS electric crystal P0～P4 connects gate, connect (diode-connected) pattern with so-called diode and be serially connected, and the substrate (bulk) of PMOS electric crystal P0～P4 all is biased in power supply voltage quasi position VDD.Wherein, input node and electric crystal P0 drain are connected in node D0, the source electrode of electric crystal P0 and electric crystal P1 drain are connected node D1, the source electrode of electric crystal P1 and electric crystal P2 drain are connected in node D2, the source electrode of electric crystal P2 and electric crystal P3 are connected in node D3 at drain, and the source electrode of electric crystal P3 and electric crystal P4 drain are connected in node D4, and the source electrode of electric crystal P4 connects output node, node D1～D4 connects capacitor C 1～C4 respectively, and its capacitance is C.

Shown in Fig. 1 (a) and Fig. 1 (b), first capacitor C 1 is connected the first clock signal A with C3, capacitor C 2 is connected the second clock signal B with C4, the first clock signal A and the second clock signal B be inversion signal each other, signal level conversion between power supply voltage quasi position and the accurate position of ground connection.

When the first clock signal A voltage quasi position is in power supply voltage quasi position (V _DD), the voltage quasi position on node D1 and the D3 is respectively through the coupling of first capacitor C 1 and C3 and be raised V _C=V _DD* C/ (CP+C), wherein CP is the parasitic capacitance value of node D1 or D3; Simultaneously, the voltage quasi position of the second clock signal B is in the accurate position of ground connection, and the voltage quasi position on node D2 and the D4 has been lowered V through the coupling of capacitor C 2 and C4 respectively _C=V _DD* C/ (CP+C), wherein CP is the parasitic capacitance value of node D2 or D4.The voltage quasi position of node D2 and D4 is lowered because the voltage quasi position of node D1 and D3 is raised, so electric crystal P0, P2, P4 conducting, electric current flows to input node (earth terminal), node D2, D4 by node D1, D3, output node respectively.At this pulse wave V _DDBefore voltage quasi position finished, the meeting of the voltage quasi position of node D1, D3, output node was transferred to earth terminal, capacitor C 2 and C4 respectively because of the electric charge on C1, C3 and the load capacitance Cout and is reduced.

On the contrary, when the first clock signal A voltage quasi position is in the accurate position of ground connection, the voltage quasi position on node D1 and the D3 has been lowered V through the coupling of capacitor C 1 and C3 respectively _C=V _DD* C/ (CP+C).Simultaneously, the second clock signal B voltage quasi position is in power supply voltage quasi position (V _DD), the voltage quasi position on node D2 and the D4 is respectively through the coupling of capacitor C 2 and C4 and be raised V _C=V _DD* C/ (CP+C).Because the voltage quasi position on node D1 and the D3 is lowered, the voltage quasi position on node D2 and the D4 is raised, electric crystal P1, P3 conducting, and electric current flows to node D1, D3 by node D2, D4 respectively; Before finished the accurate position of this pulse wave earthed voltage, the voltage quasi position of node D2, D4 can reduce because the electric charge on capacitor C 2, C4 and the load capacitance Cout transfers to capacitor C 1 and C3 respectively.Therefore, under the continuous interactive effect to capacitor C 1～C4, electric current constantly flows to earth terminal by output node, makes the output node voltage quasi position reduce constantly, finally can reach required negative voltage through the first clock signal A and the second clock signal B.

The critical voltage of the PMOS electric crystal of above-mentioned voltage pump apparatus (threshold voltage) is because the potential difference (V between substrate and the source electrode _BS=V _DD-V _S, V wherein _SBeing negative voltage) the accurate position influence of source voltage that reduced raises, promptly so-called matrix effect (body effect), significantly the critical voltage of the electric crystal of matrix effect or rising can reduce the conductive performance (charge transfer effciency) of electric crystal; The critical voltage of PMOS electric crystal P0～P4 is more and more high among Fig. 1 a, and the PMOS electric crystal of expression serial connection is many more can be caused charge transfer effciency to heal poor and efficient load current can't be provided, so the negative voltage that produces is just few more.

Fig. 2 (a) is known another kind of voltage pump apparatus 20, shown in Fig. 2 (b), voltage pump apparatus 20 utilizes the electric charge on the NMOS electric crystal transfer output node load capacitance, be the PMOS electric crystal P0～P4 of voltage pump apparatus 10 is substituted by NMOS electric crystal N1～N4 with the difference of above-mentioned voltage pump apparatus 10, the drain of each N1～N4 connects gate and connects pattern and be serially connected with diode, the operation principle of Fig. 2 (a) is identical with Fig. 1 (a), also have tangible matrix effect or rising electric crystal critical voltage and reduced the conductive performance of electric crystal.

Summary of the invention

The invention provides a kind of voltage pump apparatus and method of operation thereof, can't eliminate basic effect, the problems such as output voltage of high negative accurate position are provided to solve in the prior art.

For reaching above-mentioned purpose, the present invention proposes a kind of voltage pump apparatus and method of operation thereof, comprise several grades of charge transfer units and an output unit between the input node that is serially connected with voltage pump apparatus and output node, charge transfer unit comprises the first node that is used to import, the Section Point that is used to export, be connected first circuit of two nodes and first electric capacity that connects Section Point, wherein the first node of the charge transfer unit of the first order connects the input node, and the first node of the charge transfer unit that all the other are at different levels and Section Point then are connected the Section Point and first circuit of previous stage charge transfer unit respectively; Output unit comprises the 3rd node, the second circuit that is used to import and connects its second electric capacity that wherein, second circuit connects first circuit of the charge transfer unit of the 3rd node, output node, second electric capacity and afterbody.

Owing to provide the bias voltage can activation or anergy charge transfer unit to first circuit of charge transfer unit, therefore the charge transfer unit of odd level and even level is can be respectively identical but be two anti-phase clock signals mutually and carry out complementary switching manipulation by its first electric capacity reception voltage quasi position amplitude, even both one provide the electric charge forwarding function, another then denys, and switch its on off state in turn, cooperate the switching manipulation of output unit, can produce the output voltage of a high negative accurate position at last.

Compared with prior art, the present invention has the following advantages: a kind of voltage pump apparatus and the method for operation thereof of providing of the present invention, and can eliminate matrix effect and the output voltage with high negative accurate position is provided, have the advantage of high side Pu gain.

Description of drawings

Fig. 1 (a) is the schematic diagram of a voltage pump apparatus in the prior art;

Fig. 1 (b) is for imposing on the clock signal schematic diagram of voltage pump apparatus among Fig. 1 (a);

Fig. 2 (a) is the schematic diagram of another voltage pump apparatus in the prior art;

Fig. 2 (b) is for imposing on the clock signal schematic diagram of voltage pump apparatus among Fig. 2 (a);

Fig. 3 (a) is the schematic diagram of first embodiment of voltage pump apparatus of the present invention;

Fig. 3 (b) is for imposing on the clock signal schematic diagram of first embodiment of the invention;

Fig. 4 (a) is the schematic diagram of second embodiment of voltage pump apparatus of the present invention;

Fig. 4 (b) is for imposing on the clock signal schematic diagram of second embodiment of the invention;

Fig. 5 is the structural representation of the 2nd grade of charge transfer unit of second embodiment of the invention.

The primary clustering symbol description is as follows:

30,40 voltage pump apparatus

31,32,41,42 charge transfer units

33,43 output units

34,35,44,45 first circuit

36,46 second circuits

37,38 first well bias circuits

39,49 second well bias circuits

Embodiment

The first embodiment of the present invention is shown in Fig. 3 (a), Fig. 3 (b), voltage pump apparatus 30 by be serially connected in the 1st grade charge transfer unit 31 between input node Nin and output node Nout, the 2nd grade charge transfer unit 32 and output unit 33 formed, for obtaining negative voltage, the supply voltage that input node Nin connects is the accurate position of ground connection, and output node Nout is used to provide output voltage.

The charge transfer unit of each grade comprises first node X, X ', Section Point Y, Y ', is connected in two internodal first circuit 34,35 and first capacitor C 1, the C2 that are connected Section Point Y, Y '; And first circuit 34,35 comprises the 4th node Z, Z ', the 5th node W, W ', the 8th node NW1, NW1 ', the first electric crystal M30, the M34 that belong to the PMOS electric crystal, the second electric crystal M31, M35, the 3rd electric crystal M32, M36, the 4th electric crystal M33, the M37 that belong to the NMOS electric crystal and the first well bias circuit 37,38.The first well bias circuit 37,38 comprises the 9th electric crystal Ma, Mc and the tenth electric crystal Mc, the Md that belongs to the PMOS electric crystal, and its function is for providing the 8th node NW1, a NW1 ' bias voltage.And the first electric crystal M30, M34 drain all are connected first node X, X ' with gate, and source electrode connects Section Point Y, Y ', and substrate connects the 8th node NW1, NW2; The second electric crystal M31, M35 drain connect first node X, X ', and gate connects the 4th node Z, Z ', and source electrode connects Section Point Y, Y ', and substrate connects the 8th node NW1, NW2; The 3rd electric crystal M32, M36 drain connect the 4th node Z, Z ', and gate connects Section Point Y, Y ', and source electrode connects first node X, X ', and substrate connects the 8th node NW1, NW2; The 4th electric crystal M33, M37 source electrode are connected the 5th node W, W ' with substrate, gate connects Section Point Y, Y ', and drain connects the 4th node Z, Z '; The 9th electric crystal Ma, Mc drain all are connected the 8th node NW1, NW2 with substrate, and gate connects Section Point Y, Y ', and source electrode connects first node X, X '; The tenth electric crystal Mb, Md drain all are connected the 8th node NW1, NW2 with substrate, and gate connects first node X, X ', and source electrode connects Section Point Y, Y '.The Section Point Y ' of the 2nd grade charge transfer unit 32 connects the 5th node W of the 1st grade charge transfer unit 31.In addition, first capacitor C 1, C2 connect clock pulse control unit (among the figure describe) respectively, are provided to receive it, the anti-phase first clock signal A and the second clock signal B each other.

Output unit 33 has comprised the 3rd node P, second circuit 36 and second capacitor C 3.Second circuit 36 comprises the 6th node Q, the 7th node NW3, belongs to the 5th electric crystal Me of PMOS electric crystal, the 6th electric crystal Mf, the 7th electric crystal M39, belong to the 8th electric crystal M38 of NMOS electric crystal, and the 5th electric crystal Me, the 6th electric crystal Mf form the second well bias circuit 39, so that the 7th node NW3 to be provided one second bias voltage.The 3rd node P connects the Section Point Y ' of the 2nd grade charge transfer unit 32, and the drain of the 5th electric crystal Me is connected the 7th node NW3 with substrate, and gate connects the 6th node Q, and source electrode connects the 3rd node P; The 6th electric crystal Mf drain all is connected the 7th node NW3 with substrate, and gate connects the 3rd node P, and source electrode connects the 6th node Q; The 7th electric crystal M39 drain all is connected the 3rd node P with gate, and source electrode connects the 6th node Q, and substrate connects the 7th node NW3; The 8th electric crystal M38 drain is connected the output node Nout of voltage pump apparatus 30 with substrate, gate connects the 6th node Q, and source electrode connects the 3rd node P; Second capacitor C 3 connects the 6th node Q and the first clock signal A.

With shown in Fig. 3 (b), suppose that the voltage quasi position amplitude of the first clock signal A and the second clock signal B is V as Fig. 3 (a) _DDThe coupling effect (couplingeffect) of first capacitor C 1, C2 and second capacitor C 3 is 100%, utilize the first clock signal A and second clock signal B operating charge buanch unit 31,32 and the output unit 33, it is switched between first pattern and second pattern.

(1) t=0

When initial, the first node X of the 1st grade charge transfer unit 31 (connecting input node Nin) ground connection, the voltage quasi position of the Section Point Y of the 1st grade charge transfer unit 31 is V _Y0, the voltage quasi position of the Section Point Y ' of the 2nd grade charge transfer unit 32 equals the voltage quasi position of the 3rd node P of output unit 33, is V _P0, the voltage quasi position of the 6th node Q of output unit 33 is V _Q0, the voltage quasi position of output node Nout is V _OUT0

(2) t=t ₀(first pattern)

Time is t ₀The time, the first clock signal A is raised to high levle by low level, and the second clock signal B drops to low level by high levle, the voltage quasi position increments of change V of the first clock signal A _DDAnd, make the 1st grade the voltage quasi position of Section Point Y of charge transfer unit 31 also have equivalent to change, i.e. V via the coupling effect of first capacitor C 1 _{Y, t0}=V _Y0+ V _DDIn like manner, the voltage quasi position increments of change V of the first clock signal A _DD,, make the voltage quasi position of output unit 33 the 6th node Q also have equivalent to change, i.e. V by the coupling effect of second capacitor C 3 _{Q, t0}=V _Q0+ V _DDThe voltage quasi position of the second clock signal B changes decrement V _DD,, make the 2nd grade the voltage quasi position of Section Point Y ' of charge transfer unit 32 also have equivalent to change, i.e. V via the coupling effect of first capacitor C 2 _{Y ', t0}=V _{P, t0}=V _P0-V _DDWherein, it is as follows the operation of charge transfer unit 31,32 and output unit 33 to be described in detail in detail respectively:

(a) the 1st grade charge transfer unit 31

In the first well bias circuit 37, the 9th not conducting of electric crystal Ma, because source electrode and the relative current potential between the gate are lower than the critical voltage of PMOS electric crystal | V _Tp0|, i.e. V _{SG, Ma}=V _{X, t0}-V _{Y, t0}=0-(V _Y0+ V _DD)＜| V _Tp0|; The tenth electric crystal Mb conducting, because source electrode is higher than critical voltage with relative current potential between the gate | V _Tp0|, i.e. V _{SG, Mb}=V _{Y, t0}-V _{X, t0}=V _Y0+ V _DD| V _Tp0|.So the voltage quasi position of the 8th node NW1 equals Section Point Y voltage quasi position, i.e. V _NW1=V _Y0+ V _DDIn other words, the first well bias circuit 37 allows the 1st grade the PMOS electric crystal of charge transfer unit 31, and the substrate (bulk node) that comprises the first electric crystal M30, the second electric crystal M31, the 3rd electric crystal M32, the 9th electric crystal Ma and the tenth electric crystal Mb all is biased in the 1st grade the charge transfer unit 31 to have on the Section Point Y of the accurate position of high voltage.Since all there is not relative current potential between the first electric crystal M30, the second electric crystal M31, the 3rd electric crystal M32, the 9th electric crystal Ma and the tenth electric crystal Mb source electrode and the gate, so their critical voltage is equal to | V _Tp0|, the critical voltage when promptly not having matrix effect (body effect).The first electric crystal M30 conducting, because source electrode is higher than critical voltage with relative current potential between the gate | V _Tp0|, i.e. V _{SG, M30}=V _{Y, t0}-V _{X, t0}=V _Y0+ V _DD| V _Tp0|, electric current flow to first node X by Section Point Y, and electric charge flow to first node X by first capacitor C 1, and before time t1 (t=t1_), Section Point Y voltage quasi position will be stabilized in | V _Tp0|, i.e. V _{Y, t1_}=| V _Tp0|; The charge transfer effciency of the first electric crystal M30 equals (V _Y0+ V _DD-V _{Y, t1_})/V _DDIf can reduce V _{Y, t1_}, the charge transfer effciency of the 1st grade charge transfer unit 31 can obtain further to improve.The 3rd not conducting of electric crystal M32, because source electrode is lower than PMOS electric crystal critical voltage with relative current potential between the gate | V _Tp0|, i.e. V _{SG, M32}=V _{X, t0}-V _{Y, t0}=0-(V _Y0+ V _DD)＜| V _Tp0|; The 4th electric crystal M33 conducting is because gate is higher than NMOS electric crystal critical voltage V with relative current potential between the source electrode _TN, i.e. V _{GS, M33}=V _{Y, t0}-V _{P, t0}=(V _Y0+ V _DD)-(V _P0-V _DD)=2V _DD+ V _Y0-V _P0V _TNSo the voltage quasi position of the 4th node Z equals the voltage quasi position of Section Point Y ', i.e. V _Z=V _P0-V _DD=V _{G, M31}＜0V, because the accurate position of the second electric crystal M31 gate voltage is also lower than the accurate position of the first electric crystal M30 gate voltage, so the second electric crystal M31 has more excellent charge transfer effciency than the first electric crystal M30, Section Point Y voltage quasi position will compare | V _Tp0| lower, even near 0V, promptly

, the therefore auxiliary first electric crystal M30 of the second electric crystal M31 and promoted the charge transfer effciency of the 1st grade charge transfer unit 31.

(b) the 2nd grade charge transfer unit 32

The 9th electric crystal Mc conducting, because source electrode is higher than PMOS electric crystal critical voltage with relative current potential between the gate | V _Tp0|, i.e. V _{SG, Mc}=V _{Y, t0}-V _{P, t0}=(V _Y0+ V _DD)-(V _P0-V _DD)=2V _DD+ V _Y0-V _P0| V _Tp0|; Not conducting of electric crystal Md, because the relative current potential subcritical voltage between source electrode and the gate | V _Tp0|, i.e. V _{SG, Md}=V _{P, t0}-V _{Y, t0}=(V _P0-V _DD)-(V _Y0+ V _DD)=V _P0-V _Y0-2V _DD＜| V _Tp0|; Therefore the voltage quasi position of the 8th node NW2 equals the voltage quasi position of Section Point Y, i.e. V _NW1=V _Y0+ V _DDIn other words, the first well bias circuit 38 allows the 2nd grade the PMOS electric crystal of charge transfer unit 32, and the substrate that comprises the first electric crystal M34, the second electric crystal M35, the 3rd electric crystal M36, the 9th electric crystal Mc and the tenth electric crystal Md all is biased in the 2nd grade the charge transfer unit 32 to have on the Section Point Y ' of the accurate position of high voltage.Since no relative current potential between the first electric crystal M34, the second electric crystal M35, the 3rd electric crystal M36, the 9th electric crystal Mc and the tenth electric crystal Md source electrode and the gate, so their critical voltage is equal to | V _Tp0|, the critical voltage when promptly not having matrix effect (body effect).The first not conducting of electric crystal M34, because the relative current potential subcritical voltage between source electrode and the gate | V _Tp0|, i.e. V _{SG, M34}=V _{P, t0}-V _{Y, t0}=(V _P0-V _DD)-(V _{Y, t0}+ V _DD)=V _P0-V _Y0-2V _DD＜| V _Tp0|; The 3rd electric crystal M36 conducting, because source electrode is high-order in PMOS electric crystal critical voltage with the relative electricity between the gate | V _Tp0|, i.e. V _{SG, M36}=V _{Y, t0}-V _{P, t0}=(V _Y0+VDD)-(V _P0-V _DD)=2V _DD+ V _Y0-V _P0| V _Tp0|; The 4th not conducting of electric crystal M37 is because gate is lower than NMOS electric crystal critical voltage V with relative current potential between the source electrode _TN, i.e. V _{-GS, M37}=V _{P, t0}-V _{Q, t0}=(V _P0-V _DD)-(V _Q0+ V _DD)=(V _P0-V _Q0)-2V _DD＜V _TNThe second not conducting of electric crystal M35 is because the accurate position of gate voltage equals Section Point Y voltage quasi position, i.e. V _{G, M35}=V _Y=V _Y0+ V _DD, source electrode is lower than PMOS electric crystal critical voltage with relative current potential between the gate | V _Tp0|, i.e. V _{SG, M35}=V _{P, t0}-V _{G, M35}=(VP ₀-V _DD)-(V _Y0+ V _DD)=(V _P0-V _Y0)-2 _VDD＜| V _Tp0|.Because of the first electric crystal M34, second all not conductings of electric crystal M35 are not so the 2nd grade charge transfer unit 32 has the electric charge forwarding function when time t0.

(c) output unit 33

The 5th not conducting of electric crystal Me, because source electrode is lower than PMOS electric crystal critical voltage with relative current potential between the gate | V _Tp0|, i.e. V _{SG, Me}=V _{P, t0}-V _{Q, t0}=(V _P0-V _DD)-(V _Q0+ V _DD)=V _P0-V _Q0-2V _DD＜| V _Tp0|; The 6th electric crystal Mf conducting, because source electrode is higher than critical voltage with relative current potential between the gate | V _Tp0|, i.e. V _{SG, Mf}=V _{Q, t0}-V _{P, t0}=(V _Q0+ V _DD)-(V _P0-V _DD)=2V _DD+ V _Q0-V _P0| V _Tp0|, the voltage quasi position of the 7th node NW3 equals the 6th node Q voltage quasi position, i.e. V _NW3=V _Q0+ V _DDNo relative current potential between the 5th electric crystal Me, the 6th electric crystal Mf and the 7th electric crystal M39 source electrode and the gate, so their critical voltage is equal to | V _Tp0|, the critical voltage when promptly not having matrix effect (body effect).Electric crystal M39 conducting, because source electrode is higher than critical voltage with relative current potential between the gate | V _Tp0|, i.e. V _{SG, M39}=V _{Q, t0}-V _{P, t0}=(V _Q0+ V _DD)-(V _P0-V _DD)=2V _DD+ V _Q0-V _P0| V _Tp0|; The 8th electric crystal M38 conducting is because gate is higher than critical voltage V with relative current potential between the source electrode _TN, i.e. V _{GS, M38}=V _{Q, t0}-V _{P, t0}=(V _Q0+ V _DD)-(V _P0-V _DD)=2V _DD+ V _Q0-V _P0V _TNSo electric current flow to the 3rd node P by output node Nout, electric charge flow to input first capacitor C 2 by load capacitance Cout, and before time t1 (t=t1_), the voltage quasi position of the output node Nout of voltage pump apparatus 30 will be from initial value V _OUT0Reduce gradually and be stabilized in V _P0-V _DD, i.e. V _{OUT1_}=V _P0-V _DD, V _{Pt1_}=V _P0-V _DD, V _{Qt1_}=V _P0-V _DD+ | V _Tp0|.

(3) t=t1 (second pattern)

Time is t ₁The time, the first clock signal A drops to low level by high levle, and the second clock signal B is raised to high levle by low level.The voltage quasi position of the first clock signal A changes decrement V _DD,, make the 1st grade the voltage quasi position of Section Point Y of charge transfer unit 31 also have equivalent to change, i.e. V via the coupling effect of first capacitor C 1 _{Y, t1}=V _{Y, t1_}-V _DD=0-V _DDIn like manner, the voltage quasi position of the first clock signal A changes decrement V _DD,, make output unit 33 the 6th node Q voltage quasi position also have equivalent to change, i.e. V by the coupling effect of second capacitor C 3 _{Q, t1}=V _{Q, t1_}-V _DD=(V _P0-V _DD+ | V _Tp0|)-V _DD=V _P0-2V _DD+ | V _Tp0|.The voltage quasi position increments of change V of the second clock signal B _DD,, make the 2nd grade charge transfer unit 32 Section Point Y ' voltage quasi positions also have equivalent to change, i.e. V via the coupling effect of first capacitor C 2 _{P, t1}=V _{P, t1_}+ V _DD=(V _P0-V _DD)+V _DD=V _P0

(a) the 1st grade charge transfer unit 31

The 9th electric crystal Ma conducting, because source electrode and the relative current potential between the gate are higher than the critical voltage of PMOS electric crystal | V _Tp0|, i.e. V _{SG, Ma}=V _{X, t1}-V _{Y, t1}=0-(V _DD)=V _DD| V _Tp0|; Not conducting of electric crystal Mb, because the relative current potential subcritical voltage between source electrode and the gate | V _Tp0|, i.e. V _{SG, Mb}=V _{Y, t1}-V _{X, t1}=-V _DD＜| V _Tp0|, the voltage quasi position of the 8th node NW1 equals first node X voltage quasi position, i.e. V _NW1=0V.In other words, the first well bias circuit 37 allows the 1st grade the PMOS electric crystal of charge transfer unit 31, comprises that the substrate bias of the first electric crystal M30, the second electric crystal M31, the 3rd electric crystal M32, the 9th electric crystal Ma and the tenth electric crystal Mb has in the 1st grade charge transfer unit 31 on the first node X (promptly importing node Nin) of the accurate position of high voltage.The first electric crystal M30, the second electric crystal M31, the 3rd electric crystal M32, so no their critical voltage of relative current potential is equal between the 9th electric crystal Ma and the tenth electric crystal Mb source electrode and the gate | V _Tp0|, the critical voltage when promptly not having matrix effect (body effect).The first not conducting of electric crystal M30, because the relative current potential subcritical voltage between source electrode and the gate | V _Tp0|, i.e. V _{SG, M30}=V _{Y, t1}-V _{X, t1}=-V _DD＜| V _Tp0|; The 3rd electric crystal M32 conducting, because source electrode is high-order in PMOS electric crystal critical voltage with the relative electricity between the gate | V _Tp0|, i.e. V _{SG, M32}=V _{X, t1}-V _{Y, t1}=0-(V _DD)=V _DD| V _Tp0|; The 4th not conducting of electric crystal M33 is because gate is lower than NMOS electric crystal critical voltage VtN, i.e. V with relative current potential between the source electrode _{GS, M33}=V _{Y, t1}-V _{P, t1}=(V _DD)-V _P0＜V _TNThe second not conducting of electric crystal M31 is because the accurate position of gate voltage equals first node X voltage quasi position, V _{G, M31}=0V, source electrode is high-order in the critical voltage of PMOS electric crystal with the relative electricity between the gate | V _Tp0|, i.e. V _{SG, M31}=V _{Y, t1}-V _{X, t1}=-V _DD＜| V _Tp0|.When time t1, because the first electric crystal M30, second all not conductings of electric crystal M31 are not so the 1st grade charge transfer unit 31 has the electric charge forwarding function.

(b) the 2nd grade charge transfer unit 32

The 9th not conducting of electric crystal Mc, because source electrode is lower than PMOS electric crystal critical voltage with relative current potential between the gate | V _Tp0|, i.e. V _{SG, Mc}=V _{Y, t1}-V _{P, t1}=-V _DD-V _P0＜| V _Tp0|; The tenth electric crystal Md conducting, because source electrode is higher than critical voltage with relative current potential between the gate | V _Tp0|, i.e. V _{SG, Md}=V _{P, t1}-V _{Y, t1}=V _P0-(V _DD) | V _Tp0|, the voltage quasi position of the 8th node NW2 equals the 3rd node P voltage quasi position, i.e. V _NW2=V _P0In other words, the first well bias circuit 37 allows the 2nd grade the PMOS electric crystal of charge transfer unit 32, comprises that the substrate bias of the first electric crystal M34, the second electric crystal M35, the 3rd electric crystal M36, the 9th electric crystal Mc and the tenth electric crystal Md has in the 2nd grade charge transfer unit 32 on the Section Point Y ' of the accurate position of high voltage.No relative current potential between the first electric crystal M34, the second electric crystal M35, the 3rd electric crystal M36, the 9th electric crystal Mc and the tenth electric crystal Md source electrode and the gate, so that their critical voltage equals is equal | V _Tp0|, the critical voltage when promptly not having matrix effect (body effect).The first electric crystal M34 conducting, because source electrode is higher than critical voltage with relative current potential between the gate | V _Tp0|, i.e. V _{SG, M34}=V _{P, t1}-V _{Y, t1}=V _P0-(V _DD) | V _Tp0|, electric current flow to first node X ' by Section Point Y ', and electric charge flow to first capacitor C 1 by first capacitor C 2, and before time t2 (t=t2_), the voltage quasi position of Section Point Y ' will be stabilized in | V _Tp0|-V _DD, i.e. V _{P, t2_}=| V _Tp0|-V _DD, the charge transfer effciency of the first electric crystal M30 equals (V _{P, t1_}-V _{P, t2_})/V _DDIf can reduce V _{P, t2_}, the charge transfer effciency of the 2nd grade charge transfer unit 32 will obtain further to improve.The 3rd not conducting of electric crystal M36, because source electrode is lower than PMOS electric crystal critical voltage with relative current potential between the gate | V _Tp0|, i.e. V _{SG, M36}=V _{Y, t1}-V _{P, t1}=-V _DD-V _P0＜| V _Tp0|; The 4th electric crystal M37 conducting is because gate is higher than NMOS electric crystal critical voltage V with relative current potential between the source electrode _TN, i.e. V _{GS, M37}=V _{P, t1}-V _{Q, t1}=V _P0-(V _P0-2V _DD+ | V _Tp0|)=2V _DD-| V _Tp0| V _TN, the accurate position of the second electric crystal M35 gate voltage equals the 6th node Q voltage quasi position, i.e. V _{G, M35}=V _P0-2V _DD+ | V _Tp0|＜V _{G, M34}=-V _DD, the second electric crystal M35 has more excellent charge transfer effciency than the first electric crystal M34, so the 3rd node P voltage quasi position will compare | and V _Tp0|-V _DDLower, even approaching-V _DD, i.e. V _{P, t2}=-V _DD, the therefore auxiliary first electric crystal M34 of the second electric crystal M35 and promoted the charge transfer effciency of the 2nd grade charge transfer unit 32.

(c) output unit 33

The 5th electric crystal Me conducting, because source electrode is lower than PMOS electric crystal critical voltage with relative current potential between the gate | V _Tp0|, i.e. V _{SG, Me}=V _{P, t1}-V _{Q, t1}=V _P0-(V _P0-2V _DD+ | V _Tp0|)=2V _DD-| V _Tp0| | V _Tp0|; The 6th not conducting of electric crystal Mf, because source electrode is higher than critical voltage with relative current potential between the gate | V _Tp0|, V _{SG, Mf}=V _{Q, t1}-V _{P, t1}=(V _P0-2V _DD+ | V _Tp0|)-V _P0=| V _Tp0|-2V _DD＜| V _Tp0|, the voltage quasi position of the 7th node NW3 equals the 3rd node P voltage quasi position, i.e. V _NW3=V _P0In other words, the second well bias circuit 39 allows the PMOS electric crystal of output unit 33, comprises that the substrate bias of the 5th electric crystal Me, the 6th electric crystal Mf and the 7th electric crystal M39 has in output unit 33 on the 3rd node P of the accurate position of high voltage.Because no relative current potential between the 5th electric crystal Me, the 6th electric crystal Mf and the 7th electric crystal M39 source electrode and the gate, so that their critical voltage equals is equal | V _Tp0|, the critical voltage when promptly not having matrix effect (body effect).Not conducting of electric crystal M39, because the relative current potential subcritical voltage between source electrode and the gate | V _Tp0|, i.e. V _{SG, M39}=V _{Q, t1}-V _{P, t1}=(V _P0-2V _DD+ | V _Tp0|)-V _P0=| V _Tp0|-2V _DD＜| V _Tp0|; The 8th not conducting of electric crystal M38 is because the relative current potential subcritical voltage V between gate and the source electrode _TN, i.e. V _{GS, M38}=V _{Q, t1}-V _{P, t1}=(V _P0-2V _DD+ | V _Tp0|)-V _P0=| V _Tp0|-2V _DD＜V _TNSo output unit 33 does not have electric charge forwarding function, V _{OUT2_}=V _{OUT1_}=V _P0-V _DD, V _{Qt2_}=V _P0-2V _DD+ | V _Tp0|.

(4) t=t2 (first pattern)

When time t2, the first clock signal A is raised to high levle by low level, and the second clock signal B drops to low level by high levle.The voltage quasi position increments of change V of the first clock signal A _DDVia the coupling effect of first capacitor C 1, make the 1st grade the Section Point Y voltage quasi position of charge transfer unit 31 also have equivalent to change, i.e. V _{Y, t2}=V _{Yt2_}+ V _DD=-V _DD+ V _DD=0V.In like manner, the voltage quasi position increments of change V of the first clock signal A _DDVia the coupling effect of second capacitor C 3, make output unit 33 the 6th node Q voltage quasi position also have equivalent to change, i.e. V _{Q, t2}=V _{Qt2_}+ V _DD=(V _P0-2V _DD+ | V _Tp0|)+V _DD=V _P0-V _DD+ | V _Tp0|.The voltage quasi position of the second clock signal B changes decrement V _DDVia the coupling effect of first capacitor C 2, make the 2nd grade the Section Point Y ' voltage quasi position of charge transfer unit 32 also have equivalent to change, i.e. V _{P, t2}=V _{P, t2_}-V _DD=-V _DD-V _DD=-2V _DD

(a) the 1st grade of buanch unit 51

V _{Y, t2}=V _{X, t2}=0V, represent the 1st grade charge transfer unit 31 Section Point Y along with the first clock signal A at 0V ,-V _DDBetween change, shift electric charge fully from the 2nd grade charge transfer unit 32.

(b) the 2nd grade charge transfer unit 32

The 9th electric crystal Mc conducting is because V _{SG, Mc}=V _{Y, t2}-V _{P, t2}=0-(2V _DD)=2V _DD| V _Tp0|.The tenth not conducting of electric crystal Md is because V _{SG, Md}=V _{P, t2}-V _{Y, t2}=-2V _DD＜| V _Tp0|, the voltage quasi position of the 8th node NW2 equals the voltage quasi position of first node X ', i.e. V _NW2=V _{Y, t2}=0V; The first not conducting of electric crystal M34 is because V _{SG, M34}=V _{P, t2}-V _{Y, t2}=-2V _DD＜| V _Tp0|; The 3rd electric crystal M36 conducting is because V _{SG, M36}=V _{Y, t2}-V _{P, t2}=0-(2V _DD)=2V _DD| V _Tp0|; The 4th not conducting of electric crystal M37 is because V _{GS, M37}=V _{P, t2}-V _{Q, t2}=(2V _DD)-(V _P0-V _DD+ | V _Tp0|)=-V _P0-V _DD+ | V _Tp0|＜V _TNThe second not conducting of electric crystal M35 is because V _{SG, M35}=V _{P, t2}-V _{S, M35}=V _{P, t2}-V _{Y, t2}=-2V _DD＜| V _Tp0|.When time t2, because the first electric crystal M34, second all not conductings of electric crystal M35, the 2nd grade charge transfer unit 32 does not have the electric charge forwarding function.

(c) output unit 33

The 5th not conducting of electric crystal Me V _{SG, Me}=V _{P, t2}-V _{Q, t2}=(2V _DD)-(V _P0-V _DD+ | V _Tp0|)=| V _Tp0|-V _P0-V _DD＜| V _Tp0|: the 6th electric crystal Mf conducting, because V _{SG, Mf}=V _{Q, t2}-V _{P, t2}=(V _P0-V _DD+ | V _Tp0|)-(2V _DD)=V _DD+ | V _Tp0|+V _P0| V _Tp0|, the voltage quasi position of the 7th node NW3 equals the 6th node Q voltage quasi position, i.e. V _NW3=V _P0-V _DD+ | V _Tp0|; The 7th electric crystal M39 conducting is because V _{SG, M39}=V _{Q, t2}-V _{P, t2}=(V _P0-V _DD+ | V _Tp0|)-(2V _DD)=V _DD+ | V _Tp0|+V _P0| V _Tp0|; The 8th electric crystal M38 conducting is because V _{GS, M38}=V _{Q, t2}-V _{P, t2}=V _DD+ | V _Tp0|+V _P0V _TNSo electric current flow to the 3rd node P by output node Nout, electric charge flow to input first capacitor C 2 by load capacitance Cout, and before time t3 (t=t3_), the voltage quasi position of the output node Nout of voltage pump apparatus 30 will be from V _{OUT, t2}=V _P0-V _DDReduce gradually and be stabilized in-2V _DD, i.e. V _{OUT3_}=-2 _VDD, V _{Pt3_}=-2V _DD, V _{Qt3_}=-2V _DD+ | V _Tp0|.

(5) t=t3 (second pattern)

When time t3, the first clock signal A drops to low level by high levle, and the second clock signal B is raised to high levle by low level.The voltage quasi position of the first clock signal A changes decrement V _DDVia the coupling effect of first capacitor C 1, make the 1st grade the Section Point Y voltage quasi position of charge transfer unit 31 also have equivalent to change, i.e. V _{Y, t3}=V _{Y, t3_}-V _DD=0-V _DDIn like manner, the voltage quasi position of the first clock signal A changes decrement V _DD,, make output unit 33 the 6th node Q voltage quasi position also have equivalent to change, i.e. V via the coupling effect of second capacitor C 3 _{Q, t3}=V _{Q, t3_}-V _DD=(2V _DD+ | V _Tp0|)-V _DD=-3V _DD+ | V _Tp0|.The voltage quasi position increments of change V of the second clock signal B _DDVia the coupling effect of first capacitor C 2, make the 2nd grade the Section Point Y ' voltage quasi position of charge transfer unit 32 also have equivalent to change, i.e. V _{P, t3}=V _{P, t3_}+ V _DD=(2V _DD)+V _DD=-V _DD

(a) the 1st grade charge transfer unit 31

The 9th electric crystal Ma conducting is because V _{SG, Ma}=V _{X, t3}-V _{Y, t3}=0-(V _DD)=V _DD| V _Tp0|; The tenth not conducting of electric crystal Mb is because V _{SG, Mb}=V _{Y, t3}-V _{X, t3}=(V _DD)-0＜| V _Tp0|, so the voltage quasi position of the 8th node NW1 equals first node X voltage quasi position, i.e. V _NW1=0V.The first not conducting of electric crystal M30 is because V _{SG, M30}=V _{Y, t1}-V _{X, t1}=-V _DD＜| V _Tp0|; The 3rd electric crystal M32 conducting is because V _{SG, M32}=V _{X, t3}-V _{Y, t3}=0-(V _DD)=V _DD| V _Tp0|; The 4th not conducting of electric crystal M33, V _{SG, M33}=V _{Y, t3}-V _{P, t3}=(V _DD)-V _P0＜V _TNThe second not conducting of electric crystal M31, because the accurate position of gate voltage equals first node X voltage quasi position (0V), source electrode is lower than PMOS electric crystal critical voltage with relative current potential between the gate | V _Tp0|, i.e. V _{SG, M31}=V _{Y, t1}-V X _{, t1}=-V _DD＜| V _Tp0|.When time t3, because the first electric crystal M30, second all not conductings of electric crystal M31 are not so the 1st grade charge transfer unit 31 has the electric charge forwarding function.

(b) the 2nd grade charge transfer unit 32

V _{Y, t3}=V _{P, t3}=0V, represent the 2nd grade charge transfer unit 32 Section Point Y ' along with the second clock signal B at-V _DDWith-2V _DDBetween change, shift electric charge fully from output unit 33.

(c) output unit 33

The 5th electric crystal Me conducting is because V _{SG, Me}=V _{P, t3}-V _{Q, t3}=(V _DD)-(-3V _DD+ | V _Tp0|)=2V _DD-| V _Tp0| | V _Tp0|; The 6th not conducting of electric crystal Mf is because V _{SG, Mf}=V _{Q, t3}-V _{P, t3}=(3V _DD+ | V _Tp0|)-(V _DD)=| V _Tp0|-2V _DD＜| V _Tp0|, the voltage quasi position of the 7th node NW3 equals the voltage quasi position of the 3rd node P, i.e. V _NW1=V _{P, t3}=-V _DDNot conducting of electric crystal M39 is because V _{SG, M39}=V _{Q, t3}-V _{P, t3}=(3V _DD+ | V _Tp0|)-(V _DD)=| V _Tp0|-2V _DD＜| V _Tp0|; The 8th not conducting of electric crystal M38 is because V _{GS, M38}=V _{Q, t3}-V _{P, t3}=(3V _DD+ | V _Tp0|)-(V _DD)=| V _Tp0|-2V _DD＜V _TNSo output unit 33 does not have electric charge forwarding function, V _{OUT4_}=V _OUT3=-2V _DD, V _{Qt4_}=V _Qt3=-3V _DD+ | V _Tp0|.

(6) t=t4 (first pattern)

When time t4, the first clock signal A is raised to high levle by low level, and the second clock signal B drops to low level by high levle.The voltage quasi position increments of change V of the first clock signal A _DDVia the coupling effect of first capacitor C 1, make the 1st grade charge transfer unit 31 Section Point Y voltage quasi positions also have equivalent to change, i.e. V _{Y, t4}=V _{Yt4_}+ V _DD=-V _DD+ V _DD=0V.In like manner, the voltage quasi position increments of change V of the first clock signal A _DDVia the coupling effect of second capacitor C 3, make output unit 33 the 6th node Q voltage quasi position also have equivalent to change, i.e. V _{Q, t4}=V _{Qt4_}+ V _DD=(3V _DD+ | V _Tp0|)+V _DD=-2V _DD+ | V _Tp0|.The voltage quasi position of the second clock signal B changes decrement V _DDVia the coupling effect of first capacitor C 2, make the 2nd grade charge transfer unit 32 Section Point Y ' voltage quasi positions also have equivalent to change, i.e. V _{P, t4}=V _{P, t4_}-V _DD=-V _DD-V _DD=-2V _DD

(a) the 1st grade charge transfer unit 31

V _{Y, t4}=V _{X, t4}=0V, the Section Point Y of charge transfer unit 31 that represents the 1st grade is at 0V and-V _DDBetween change, shift electric charge fully from the 2nd grade charge transfer unit 32.

(b) the 2nd grade charge transfer unit 32

The 9th electric crystal Mc conducting is because V _{SG, Mc}=V _{Y, t4}-V _{P, t4}=0-(2V _DD)=2V _DD| V _Tp0|.The tenth not conducting of electric crystal Mb is because V _{SG, Md}=V _{P, t4}-V _{Y, t4}=-2V _DD＜| V _Tp0|, the voltage quasi position of the 8th node NW2 equals first node X ' voltage quasi position, i.e. V _NW2=0V; The first not conducting of electric crystal M34 is because V _{SG, M34}=VP, t4-V _{Y, t4}=-2V _DD＜| V _Tp0|; The 3rd electric crystal M36 conducting is because V _{SG, M36}=V _{Y, t4}-V _{P, t4}=0-(2V _DD)=2V _DD| V _Tp0|.The 4th not conducting of electric crystal M37 is because V _{SG, M37}=V _{P, t4}-V _{Q, t4}=(2V _DD)-(-2V _DD+ | V _Tp0|)=-| V _Tp0|＜V _TNThe second not conducting of electric crystal M35 is because V _{SG, M35}=V _{P, t4}-V _{S, M35}=V _{P, t4}-V _{Y, t4}=-2V _DD＜| V _Tp0|.Because of the first electric crystal M34, second all not conductings of electric crystal M35 are not so the 2nd grade charge transfer unit 32 has the electric charge forwarding function when time t4.

(c) output unit 33

V _{OUT, t4}=V _{P, t4}=-2V _DD, expression output node Nout voltage quasi position maintains-2V _DD, shift electric charge fully from load capacitance Cout.

The first above-mentioned pattern is the charge transfer unit 32 of the 2nd grade of the charge transfer unit 31 of the 1st grade of activation and output unit 33 and anergy, make the 1st grade charge transfer unit 31 shift electric charge fully from the 2nd grade charge transfer unit 32, and output unit 33 shifts the electric charge from output node Nout fully, and the 2nd grade charge transfer unit 32 is not then had an electric charge forwarding function; And the second above-mentioned pattern is the charge transfer unit 32 of activation even level and charge transfer unit 31 and this output unit of anergy odd level, make the 2nd grade charge transfer unit 31 shift electric charge from output unit 33 fully, 33 of output units are not had an electric charge forwarding function.Therefore, by by repeating to switch charge transfer unit 31,32 and output unit 33, finally can produce output voltage, i.e. V from output node Nout in first pattern and second pattern _OUT=-2V _DD, if want to obtain-N * V _DDVoltage, only need be connected in series the charge transfer unit and the output unit of N level.And the arrangement of the operating state of the voltage quasi position of above-mentioned each node of different time and each electric crystal, as shown in the following Table I.

Table one

Node	t＝0	t＝t0	t＝t1_	t＝t1	t＝t2_	t＝t2	t＝t3_	t＝t3	t＝t4_	t＝t4	t＝t5_
Node	t＝0	t＝t0	t＝t1_	t＝t1	t＝t2_	t＝t2	t＝t3_	t＝t3	t＝t4_	t＝t4	t＝t5_	Y	V _Y0	V _Y0+V _DD	0	-V _DD	-V _DD	0	0	-V _DD	-V _DD	0	-V _DD
P	V _P0	V _P0-V _DD	V _P0-V _DD	V _P0	-V _DD	-2V _DD	-2V _DD	-V _DD	-V _DD	-2V _DD	-2V _DD	Y	V _Y0	V _Y0+V _DD	0	-V _DD	-V _DD	0	0	-V _DD	-V _DD	0	-V _DD
P	V _P0	V _P0-V _DD	V _P0-V _DD	V _P0	-V _DD	-2V _DD	-2V _DD	-V _DD	-V _DD	-2V _DD	-2V _DD	Q	V _Q0	V _Q0+V _DD	V _P0-V _DD +\|Vtp0\|	V _P0-2V _DD +\|Vtp0\|	V _P0-2V _DD +\|Vtp0\|	V _P0-V _DD +\|Vtp0\|	-2V _DD+ \|Vtp0\|	-3V _DD+ \|Vtp0\|	-3V _DD+ \|Vtp0\|	-2V _DD+ \|Vtp0\|	-2V _DD+ \|Vtp0\|
OUT	V _OUT0	V _OUT0	V _P0-V _DD	V _P0-V _DD	V _P0-V _DD	V _P0-V _DD	-2V _DD	-2V _DD	-2V _DD	-2V _DD	-2V _DD	Q	V _Q0	V _Q0+V _DD	V _P0-V _DD +\|Vtp0\|	V _P0-2V _DD +\|Vtp0\|	V _P0-2V _DD +\|Vtp0\|	V _P0-V _DD +\|Vtp0\|	-2V _DD+ \|Vtp0\|	-3V _DD+ \|Vtp0\|	-3V _DD+ \|Vtp0\|	-2V _DD+ \|Vtp0\|	-2V _DD+ \|Vtp0\|
OUT	V _OUT0	V _OUT0	V _P0-V _DD	V _P0-V _DD	V _P0-V _DD	V _P0-V _DD	-2V _DD	-2V _DD	-2V _DD	-2V _DD	-2V _DD	Device 31	-	ON	ON	X	X	ON	ON	X	X	ON	ON
Device 32	-	X	X	ON	ON	X	X	ON	ON	X	X	Device 31	-	ON	ON	X	X	ON	ON	X	X	ON	ON
Device 32	-	X	X	ON	ON	X	X	ON	ON	X	X	Device 33	-	ON	ON	X	X	ON	ON	X	X	ON	ON

Shown in Fig. 4 (a) and 4 (b) figure, voltage pump apparatus 40 is by the charge transfer unit (41 that is serially connected with between input node Nin and output node Nout 2 grades, 42) and output unit 43 form, charge transfer unit has first circuit (44,45) with first capacitor C 1, C2, output unit 43 has second circuit 46, and has the second well bias circuit 47 in the second circuit, for obtaining negative voltage, input node Nin ground connection.The difference of second embodiment and first embodiment is that first circuit (44,45) in the charge transfer unit 31,32 does not have the first well bias circuit of first embodiment.

The PMOS electric crystal of the 1st grade charge transfer unit 41, comprise the first electric crystal M40, the second electric crystal M41 and the 3rd electric crystal M42, its N type wellblock is biased in the first node X of charge transfer unit 41, and the PMOS electric crystal of charge transfer unit 42 comprises that the N type wellblock of the first electric crystal M44, the second electric crystal M45 and the 3rd electric crystal M46 is biased in the first node X ' of charge transfer unit 42.

As Fig. 4 (a), Fig. 4 (b) is with shown in Figure 5, when the Section Point Y ' of the 2nd grade charge transfer unit 42 voltage quasi position is raise via the coupling effect of first capacitor C 2 by the second clock signal B, the voltage quasi position of the Section Point Y of the 1st grade charge transfer unit 41 is reduced via the coupling effect of first capacitor C 1 by the first clock signal A, first electric crystal M44 conducting this moment, simultaneously because the P+/N-well of forward bias voltage drop conducting connects the assistance of face diode, the conducting resistance (on-resistance) that has reduced by the first electric crystal M44 has increased ON time, and improves the charge transfer effciency of charge transfer unit 42.

More than disclosed only be several specific embodiment of the present invention, still, the present invention is not limited thereto, any those skilled in the art can think variation all should fall into protection scope of the present invention.

Claims

1. a voltage pump apparatus is characterized in that, comprising:

One input node connects a supply voltage;

One output node is used to provide an output voltage;

One clock pulse control unit is used to provide one first time pulse signal and one second time pulse signal that are anti-phase mutually;

At least the secondary charge transfer unit of serial connection, the described charge transfer unit of each grade comprises a first node, a Section Point, is connected two internodal one first circuit and one first electric capacity, and described first electric capacity is to connect described Section Point and described clock pulse control unit; And the described first node of the described charge transfer unit of the first order connects described input node, and the described first node of the described charge transfer unit that all the other are at different levels and described Section Point then are connected the described Section Point and described first circuit of the described charge transfer unit of previous stage respectively; And

One output unit, one second electric capacity that comprises one the 3rd node, a second circuit and connect described clock pulse control unit, described the 3rd node connects the described Section Point of the described charge transfer unit of afterbody, and described second circuit then connects described first circuit of the described charge transfer unit of described the 3rd node, described output node, described second electric capacity and afterbody.

2. voltage pump apparatus according to claim 1 is characterized in that, the accurate position of described supply voltage be accurate an of ground connection.

3. voltage pump apparatus according to claim 1, it is characterized in that, described first circuit comprises one the 4th node, one the 5th node, one first electric crystal, one second electric crystal, one the 3rd electric crystal and one the 4th electric crystal, the substrate of the substrate of described first electric crystal, described second electric crystal is connected described first node with the substrate of described the 3rd electric crystal, and described the 5th node connects the described Section Point of the described charge transfer unit of the substrate of described the 4th electric crystal and next stage; Described second circuit comprises one the 6th node, one the 7th node, one the 5th electric crystal, one the 6th electric crystal, one the 7th electric crystal and one the 8th electric crystal, described the 5th electric crystal, described the 6th electric crystal are connected described the 7th node with the substrate of one the 7th electric crystal, the substrate of described the 8th electric crystal connects described output node, and described the 6th node connects described the 5th node of the described charge transfer unit of described the 8th electric crystal, described second electric capacity and afterbody.

4. as voltage pump apparatus as described in the claim 3, it is characterized in that the drain of the drain of described first electric crystal of described first circuit, gate, described second electric crystal and the source electrode of described the 3rd electric crystal connect described first node; The gate of the gate of the source electrode of the source electrode of described first electric crystal, described second electric crystal, described the 3rd electric crystal and described the 4th electric crystal then connects described Section Point; The drain of the gate of described second electric crystal, described the 3rd electric crystal is connected described the 4th node with the drain of described the 4th electric crystal; The source electrode of described the 4th electric crystal connects described the 5th node; The source electrode of drain, gate and described the 8th electric crystal of the source electrode of described the 5th electric crystal of described second circuit, the gate of described the 6th electric crystal, described the 7th electric crystal connects described the 3rd node; The gate of the source electrode of the source electrode of the gate of described the 5th electric crystal, described the 6th electric crystal, described the 7th electric crystal and described the 8th electric crystal connects described the 6th node; The drain of the drain of described the 5th electric crystal and described the 6th electric crystal connects described the 7th node.

5. as voltage pump apparatus as described in claim 3 or 4, it is characterized in that, described first electric crystal, described second electric crystal, described the 3rd electric crystal, described the 5th electric crystal, described the 6th electric crystal and described the 7th electric crystal are the PMOS electric crystal, and described the 4th electric crystal and described the 8th electric crystal then are the NMOS electric crystal.

6. voltage pump apparatus according to claim 1, it is characterized in that, described first circuit comprises one the 4th node, one the 5th node, one the 8th node, one first electric crystal, one second electric crystal, one the 3rd electric crystal, one the 4th electric crystal and one first well bias circuit, the described first well bias circuit comprises one the 9th electric crystal and 1 the tenth electric crystal, is used to provide described the 8th node one first bias voltage; Described first electric crystal, described second electric crystal are connected described the 8th node with described the 3rd electric crystal substrate; Described the 5th node connects the described Section Point of described the 4th electric crystal substrate and the described charge transfer unit of next stage; Described second circuit comprises one the 6th node, one the 7th node, one second well bias circuit, one the 7th electric crystal and one the 8th electric crystal, the described second well bias circuit comprises one the 5th electric crystal and one the 6th electric crystal, be used to provide described the 7th node one second bias voltage, described the 5th electric crystal, described the 6th electric crystal is connected described the 7th node with one the 7th electric crystal substrate, described the 8th electric crystal substrate connects described output node, and described the 6th node connects described the 8th electric crystal, described the 5th node of described second electric capacity and the described charge transfer unit of afterbody.

7. as voltage pump apparatus as described in the claim 6, it is characterized in that the source electrode of the drain of the drain of described first electric crystal of described first circuit, gate, described second electric crystal, the source electrode of described the 3rd electric crystal, described the 9th electric crystal and the gate of described the tenth electric crystal connect described first node; The source electrode of the gate of the gate of the gate of the gate of the source electrode of the source electrode of described first electric crystal, described second electric crystal, described the 3rd electric crystal, described the 3rd electric crystal, described the 4th electric crystal, described the 9th electric crystal and described the tenth electric crystal then connects described Section Point; The drain of the gate of described second electric crystal, described the 3rd electric crystal is connected described the 4th node with the drain of described the 4th electric crystal; The source electrode of described the 4th electric crystal connects described the 5th node; The drain of the drain of described the 9th electric crystal, substrate, described the tenth electric crystal, substrate then connect described the 8th node; The source electrode of drain, gate and described the 8th electric crystal of the source electrode of described the 5th electric crystal of described second circuit, the gate of described the 6th electric crystal, described the 7th electric crystal connects described the 3rd node; The gate of the source electrode of the source electrode of the gate of described the 5th electric crystal, described the 6th electric crystal, described the 7th electric crystal and described the 8th electric crystal connects described the 6th node; The drain of the drain of described the 5th electric crystal and described the 6th electric crystal connects described the 7th node.

8. as voltage pump apparatus as described in claim 6 or 7, it is characterized in that, described first electric crystal, described second electric crystal, described the 3rd electric crystal, described the 5th electric crystal, described the 6th electric crystal, described the 7th electric crystal, described the 9th electric crystal, described the tenth electric crystal are the PMOS electric crystal, and described the 4th electric crystal and described the 8th electric crystal then are the NMOS electric crystal.

9. the method for operation of a voltage pump apparatus is characterized in that, comprises the following steps:

A, described first clock signal of generation and described second clock signal, its voltage quasi position amplitude is V _DD

B, apply described first clock signal and give described first electric capacity of described charge transfer unit of odd level and described second electric capacity of described output unit, apply described first electric capacity that described second clock pulse gives the described charge transfer unit of even level simultaneously;

C, at the described charge transfer unit of one first pattern activation odd level and the described charge transfer unit of described output unit and anergy even level, the described charge transfer unit of odd level is shifted fully from the electric charge of the described charge transfer unit of next stage even level and described output unit shift electric charge from described output node fully, the described charge transfer unit of even level does not then carry out electric charge to be shifted;

D, at the described charge transfer unit of one second pattern activation even level and the described charge transfer unit and the described output unit of anergy odd level, make the described charge transfer unit of even level shift electric charge from the described charge transfer unit of next stage odd level fully, the described charge transfer unit of odd level is transfer charge not then;

E, repeating step c finally produce described output voltage from described output node to steps d, and it can reach at most-N * V _DD

10. the method for operation of a voltage pump apparatus is characterized in that, comprises the following steps:

A, described first clock signal of generation and described second clock signal, the amplitude of its voltage quasi position is V _DD

B, apply described charge transfer unit and described output unit that described first clock signal gives odd level, apply the described charge transfer unit that described second clock pulse gives even level simultaneously;

C, described first electric crystal at the described charge transfer unit of one first pattern activation odd level, described second electric crystal, described the 6th electric crystal of described the 4th electric crystal and described output unit, described first electric crystal of the described charge transfer unit of described the 7th electric crystal and described the 8th electric crystal and anergy even level, second electric crystal and the 4th electric crystal, the described charge transfer unit of odd level is shifted fully from the electric charge of the described charge transfer unit of next stage even level and described output unit shift electric charge from described output node fully, the described charge transfer unit of even level does not then carry out electric charge to be shifted;

D, at described the 8th electric crystal, described the 9th electric crystal and described the tenth electric crystal of described first electric crystal, described second electric crystal, described the 4th electric crystal and the described output unit of the described charge transfer unit of described first electric crystal, described second electric crystal, described the 4th electric crystal and the anergy odd level of the described charge transfer unit of one second pattern activation even level, make the described charge transfer unit of even level shift electric charge from the described charge transfer unit of next stage odd level fully, the described charge transfer unit of odd level is transfer charge not then;

11. the method for operation of a voltage pump apparatus is characterized in that, comprises the following steps:

C, described first electric crystal at the described charge transfer unit of one first pattern activation odd level, described second electric crystal, described the 4th electric crystal, described the 6th electric crystal of described the tenth electric crystal and described output unit, described first electric crystal of the described charge transfer unit of described the 7th electric crystal and described the 8th electric crystal and anergy even level, second electric crystal and the 4th electric crystal and described the tenth electric crystal, the described charge transfer unit of odd level is shifted fully from the electric charge of the described charge transfer unit of next stage even level and described output unit shift electric charge from described output node fully, the described charge transfer unit of even level does not then carry out electric charge to be shifted;